1 /* 2 * QEMU educational PCI device 3 * 4 * Copyright (c) 2012-2015 Jiri Slaby 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include "hw/pci/pci.h" 26 #include "qemu/timer.h" 27 #include "qemu/main-loop.h" /* iothread mutex */ 28 #include "qapi/visitor.h" 29 30 #define EDU(obj) OBJECT_CHECK(EduState, obj, "edu") 31 32 #define FACT_IRQ 0x00000001 33 #define DMA_IRQ 0x00000100 34 35 #define DMA_START 0x40000 36 #define DMA_SIZE 4096 37 38 typedef struct { 39 PCIDevice pdev; 40 MemoryRegion mmio; 41 42 QemuThread thread; 43 QemuMutex thr_mutex; 44 QemuCond thr_cond; 45 bool stopping; 46 47 uint32_t addr4; 48 uint32_t fact; 49 #define EDU_STATUS_COMPUTING 0x01 50 #define EDU_STATUS_IRQFACT 0x80 51 uint32_t status; 52 53 uint32_t irq_status; 54 55 #define EDU_DMA_RUN 0x1 56 #define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1) 57 # define EDU_DMA_FROM_PCI 0 58 # define EDU_DMA_TO_PCI 1 59 #define EDU_DMA_IRQ 0x4 60 struct dma_state { 61 dma_addr_t src; 62 dma_addr_t dst; 63 dma_addr_t cnt; 64 dma_addr_t cmd; 65 } dma; 66 QEMUTimer dma_timer; 67 char dma_buf[DMA_SIZE]; 68 uint64_t dma_mask; 69 } EduState; 70 71 static void edu_raise_irq(EduState *edu, uint32_t val) 72 { 73 edu->irq_status |= val; 74 if (edu->irq_status) { 75 pci_set_irq(&edu->pdev, 1); 76 } 77 } 78 79 static void edu_lower_irq(EduState *edu, uint32_t val) 80 { 81 edu->irq_status &= ~val; 82 83 if (!edu->irq_status) { 84 pci_set_irq(&edu->pdev, 0); 85 } 86 } 87 88 static bool within(uint32_t addr, uint32_t start, uint32_t end) 89 { 90 return start <= addr && addr < end; 91 } 92 93 static void edu_check_range(uint32_t addr, uint32_t size1, uint32_t start, 94 uint32_t size2) 95 { 96 uint32_t end1 = addr + size1; 97 uint32_t end2 = start + size2; 98 99 if (within(addr, start, end2) && 100 end1 > addr && within(end1, start, end2)) { 101 return; 102 } 103 104 hw_error("EDU: DMA range 0x%.8x-0x%.8x out of bounds (0x%.8x-0x%.8x)!", 105 addr, end1 - 1, start, end2 - 1); 106 } 107 108 static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr) 109 { 110 dma_addr_t res = addr & edu->dma_mask; 111 112 if (addr != res) { 113 printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res); 114 } 115 116 return res; 117 } 118 119 static void edu_dma_timer(void *opaque) 120 { 121 EduState *edu = opaque; 122 bool raise_irq = false; 123 124 if (!(edu->dma.cmd & EDU_DMA_RUN)) { 125 return; 126 } 127 128 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) { 129 uint32_t dst = edu->dma.dst; 130 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE); 131 dst -= DMA_START; 132 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src), 133 edu->dma_buf + dst, edu->dma.cnt); 134 } else { 135 uint32_t src = edu->dma.src; 136 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE); 137 src -= DMA_START; 138 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst), 139 edu->dma_buf + src, edu->dma.cnt); 140 } 141 142 edu->dma.cmd &= ~EDU_DMA_RUN; 143 if (edu->dma.cmd & EDU_DMA_IRQ) { 144 raise_irq = true; 145 } 146 147 if (raise_irq) { 148 edu_raise_irq(edu, DMA_IRQ); 149 } 150 } 151 152 static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma, 153 bool timer) 154 { 155 if (write && (edu->dma.cmd & EDU_DMA_RUN)) { 156 return; 157 } 158 159 if (write) { 160 *dma = *val; 161 } else { 162 *val = *dma; 163 } 164 165 if (timer) { 166 timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); 167 } 168 } 169 170 static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size) 171 { 172 EduState *edu = opaque; 173 uint64_t val = ~0ULL; 174 175 if (size != 4) { 176 return val; 177 } 178 179 switch (addr) { 180 case 0x00: 181 val = 0x010000edu; 182 break; 183 case 0x04: 184 val = edu->addr4; 185 break; 186 case 0x08: 187 qemu_mutex_lock(&edu->thr_mutex); 188 val = edu->fact; 189 qemu_mutex_unlock(&edu->thr_mutex); 190 break; 191 case 0x20: 192 val = atomic_read(&edu->status); 193 break; 194 case 0x24: 195 val = edu->irq_status; 196 break; 197 case 0x80: 198 dma_rw(edu, false, &val, &edu->dma.src, false); 199 break; 200 case 0x88: 201 dma_rw(edu, false, &val, &edu->dma.dst, false); 202 break; 203 case 0x90: 204 dma_rw(edu, false, &val, &edu->dma.cnt, false); 205 break; 206 case 0x98: 207 dma_rw(edu, false, &val, &edu->dma.cmd, false); 208 break; 209 } 210 211 return val; 212 } 213 214 static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val, 215 unsigned size) 216 { 217 EduState *edu = opaque; 218 219 if (addr < 0x80 && size != 4) { 220 return; 221 } 222 223 if (addr >= 0x80 && size != 4 && size != 8) { 224 return; 225 } 226 227 switch (addr) { 228 case 0x04: 229 edu->addr4 = ~val; 230 break; 231 case 0x08: 232 if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) { 233 break; 234 } 235 /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only 236 * set in this function and it is under the iothread mutex. 237 */ 238 qemu_mutex_lock(&edu->thr_mutex); 239 edu->fact = val; 240 atomic_or(&edu->status, EDU_STATUS_COMPUTING); 241 qemu_cond_signal(&edu->thr_cond); 242 qemu_mutex_unlock(&edu->thr_mutex); 243 break; 244 case 0x20: 245 if (val & EDU_STATUS_IRQFACT) { 246 atomic_or(&edu->status, EDU_STATUS_IRQFACT); 247 } else { 248 atomic_and(&edu->status, ~EDU_STATUS_IRQFACT); 249 } 250 break; 251 case 0x60: 252 edu_raise_irq(edu, val); 253 break; 254 case 0x64: 255 edu_lower_irq(edu, val); 256 break; 257 case 0x80: 258 dma_rw(edu, true, &val, &edu->dma.src, false); 259 break; 260 case 0x88: 261 dma_rw(edu, true, &val, &edu->dma.dst, false); 262 break; 263 case 0x90: 264 dma_rw(edu, true, &val, &edu->dma.cnt, false); 265 break; 266 case 0x98: 267 if (!(val & EDU_DMA_RUN)) { 268 break; 269 } 270 dma_rw(edu, true, &val, &edu->dma.cmd, true); 271 break; 272 } 273 } 274 275 static const MemoryRegionOps edu_mmio_ops = { 276 .read = edu_mmio_read, 277 .write = edu_mmio_write, 278 .endianness = DEVICE_NATIVE_ENDIAN, 279 }; 280 281 /* 282 * We purposedly use a thread, so that users are forced to wait for the status 283 * register. 284 */ 285 static void *edu_fact_thread(void *opaque) 286 { 287 EduState *edu = opaque; 288 289 while (1) { 290 uint32_t val, ret = 1; 291 292 qemu_mutex_lock(&edu->thr_mutex); 293 while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 && 294 !edu->stopping) { 295 qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex); 296 } 297 298 if (edu->stopping) { 299 qemu_mutex_unlock(&edu->thr_mutex); 300 break; 301 } 302 303 val = edu->fact; 304 qemu_mutex_unlock(&edu->thr_mutex); 305 306 while (val > 0) { 307 ret *= val--; 308 } 309 310 /* 311 * We should sleep for a random period here, so that students are 312 * forced to check the status properly. 313 */ 314 315 qemu_mutex_lock(&edu->thr_mutex); 316 edu->fact = ret; 317 qemu_mutex_unlock(&edu->thr_mutex); 318 atomic_and(&edu->status, ~EDU_STATUS_COMPUTING); 319 320 if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) { 321 qemu_mutex_lock_iothread(); 322 edu_raise_irq(edu, FACT_IRQ); 323 qemu_mutex_unlock_iothread(); 324 } 325 } 326 327 return NULL; 328 } 329 330 static int pci_edu_init(PCIDevice *pdev) 331 { 332 EduState *edu = DO_UPCAST(EduState, pdev, pdev); 333 uint8_t *pci_conf = pdev->config; 334 335 timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu); 336 337 qemu_mutex_init(&edu->thr_mutex); 338 qemu_cond_init(&edu->thr_cond); 339 qemu_thread_create(&edu->thread, "edu", edu_fact_thread, 340 edu, QEMU_THREAD_JOINABLE); 341 342 pci_config_set_interrupt_pin(pci_conf, 1); 343 344 memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, 345 "edu-mmio", 1 << 20); 346 pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); 347 348 return 0; 349 } 350 351 static void pci_edu_uninit(PCIDevice *pdev) 352 { 353 EduState *edu = DO_UPCAST(EduState, pdev, pdev); 354 355 qemu_mutex_lock(&edu->thr_mutex); 356 edu->stopping = true; 357 qemu_mutex_unlock(&edu->thr_mutex); 358 qemu_cond_signal(&edu->thr_cond); 359 qemu_thread_join(&edu->thread); 360 361 qemu_cond_destroy(&edu->thr_cond); 362 qemu_mutex_destroy(&edu->thr_mutex); 363 364 timer_del(&edu->dma_timer); 365 } 366 367 static void edu_obj_uint64(Object *obj, struct Visitor *v, void *opaque, 368 const char *name, Error **errp) 369 { 370 uint64_t *val = opaque; 371 372 visit_type_uint64(v, val, name, errp); 373 } 374 375 static void edu_instance_init(Object *obj) 376 { 377 EduState *edu = EDU(obj); 378 379 edu->dma_mask = (1UL << 28) - 1; 380 object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64, 381 edu_obj_uint64, NULL, &edu->dma_mask, NULL); 382 } 383 384 static void edu_class_init(ObjectClass *class, void *data) 385 { 386 PCIDeviceClass *k = PCI_DEVICE_CLASS(class); 387 388 k->init = pci_edu_init; 389 k->exit = pci_edu_uninit; 390 k->vendor_id = PCI_VENDOR_ID_QEMU; 391 k->device_id = 0x11e8; 392 k->revision = 0x10; 393 k->class_id = PCI_CLASS_OTHERS; 394 } 395 396 static void pci_edu_register_types(void) 397 { 398 static const TypeInfo edu_info = { 399 .name = "edu", 400 .parent = TYPE_PCI_DEVICE, 401 .instance_size = sizeof(EduState), 402 .instance_init = edu_instance_init, 403 .class_init = edu_class_init, 404 }; 405 406 type_register_static(&edu_info); 407 } 408 type_init(pci_edu_register_types) 409