xref: /openbmc/qemu/hw/misc/eccmemctl.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * QEMU Sparc Sun4m ECC memory controller emulation
3  *
4  * Copyright (c) 2007 Robert Reif
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "hw/irq.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
29 #include "qemu/module.h"
30 #include "trace.h"
31 
32 /* There are 3 versions of this chip used in SMP sun4m systems:
33  * MCC (version 0, implementation 0) SS-600MP
34  * EMC (version 0, implementation 1) SS-10
35  * SMC (version 0, implementation 2) SS-10SX and SS-20
36  *
37  * Chipset docs:
38  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
39  * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
40  */
41 
42 #define ECC_MCC        0x00000000
43 #define ECC_EMC        0x10000000
44 #define ECC_SMC        0x20000000
45 
46 /* Register indexes */
47 #define ECC_MER        0               /* Memory Enable Register */
48 #define ECC_MDR        1               /* Memory Delay Register */
49 #define ECC_MFSR       2               /* Memory Fault Status Register */
50 #define ECC_VCR        3               /* Video Configuration Register */
51 #define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
52 #define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
53 #define ECC_DR         6               /* Diagnostic Register */
54 #define ECC_ECR0       7               /* Event Count Register 0 */
55 #define ECC_ECR1       8               /* Event Count Register 1 */
56 
57 /* ECC fault control register */
58 #define ECC_MER_EE     0x00000001      /* Enable ECC checking */
59 #define ECC_MER_EI     0x00000002      /* Enable Interrupts on
60                                           correctable errors */
61 #define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
62 #define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
63 #define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
64 #define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
65 #define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
66 #define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
67 #define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
68 #define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
69 #define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
70 #define ECC_MER_MRR    0x000003fc      /* MRR mask */
71 #define ECC_MER_A      0x00000400      /* Memory controller addr map select */
72 #define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
73 #define ECC_MER_VER    0x0f000000      /* Version */
74 #define ECC_MER_IMPL   0xf0000000      /* Implementation */
75 #define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
76 #define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
77 #define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
78 
79 /* ECC memory delay register */
80 #define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
81 #define ECC_MDR_MI     0x00001c00      /* MIH Delay */
82 #define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
83 #define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
84 #define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
85 #define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
86 #define ECC_MDR_RSC    0x80000000      /* Refresh load control */
87 #define ECC_MDR_MASK   0x7fffffff
88 
89 /* ECC fault status register */
90 #define ECC_MFSR_CE    0x00000001      /* Correctable error */
91 #define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
92 #define ECC_MFSR_TO    0x00000004      /* Timeout on write */
93 #define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
94 #define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
95 #define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
96 #define ECC_MFSR_ME    0x00010000      /* Multiple errors */
97 #define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
98 
99 /* ECC fault address register 0 */
100 #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
101 #define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
102 #define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
103 #define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
104 #define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
105 #define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
106 #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
107 #define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
108 #define ECC_MFARO_MID   0xf0000000     /* Module ID */
109 
110 /* ECC diagnostic register */
111 #define ECC_DR_CBX     0x00000001
112 #define ECC_DR_CB0     0x00000002
113 #define ECC_DR_CB1     0x00000004
114 #define ECC_DR_CB2     0x00000008
115 #define ECC_DR_CB4     0x00000010
116 #define ECC_DR_CB8     0x00000020
117 #define ECC_DR_CB16    0x00000040
118 #define ECC_DR_CB32    0x00000080
119 #define ECC_DR_DMODE   0x00000c00
120 
121 #define ECC_NREGS      9
122 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
123 
124 #define ECC_DIAG_SIZE  4
125 #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
126 
127 #define TYPE_ECC_MEMCTL "eccmemctl"
128 #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL)
129 
130 typedef struct ECCState {
131     SysBusDevice parent_obj;
132 
133     MemoryRegion iomem, iomem_diag;
134     qemu_irq irq;
135     uint32_t regs[ECC_NREGS];
136     uint8_t diag[ECC_DIAG_SIZE];
137     uint32_t version;
138 } ECCState;
139 
140 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
141                           unsigned size)
142 {
143     ECCState *s = opaque;
144 
145     switch (addr >> 2) {
146     case ECC_MER:
147         if (s->version == ECC_MCC)
148             s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
149         else if (s->version == ECC_EMC)
150             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
151         else if (s->version == ECC_SMC)
152             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
153         trace_ecc_mem_writel_mer(val);
154         break;
155     case ECC_MDR:
156         s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
157         trace_ecc_mem_writel_mdr(val);
158         break;
159     case ECC_MFSR:
160         s->regs[ECC_MFSR] =  val;
161         qemu_irq_lower(s->irq);
162         trace_ecc_mem_writel_mfsr(val);
163         break;
164     case ECC_VCR:
165         s->regs[ECC_VCR] =  val;
166         trace_ecc_mem_writel_vcr(val);
167         break;
168     case ECC_DR:
169         s->regs[ECC_DR] =  val;
170         trace_ecc_mem_writel_dr(val);
171         break;
172     case ECC_ECR0:
173         s->regs[ECC_ECR0] =  val;
174         trace_ecc_mem_writel_ecr0(val);
175         break;
176     case ECC_ECR1:
177         s->regs[ECC_ECR0] =  val;
178         trace_ecc_mem_writel_ecr1(val);
179         break;
180     }
181 }
182 
183 static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
184                              unsigned size)
185 {
186     ECCState *s = opaque;
187     uint32_t ret = 0;
188 
189     switch (addr >> 2) {
190     case ECC_MER:
191         ret = s->regs[ECC_MER];
192         trace_ecc_mem_readl_mer(ret);
193         break;
194     case ECC_MDR:
195         ret = s->regs[ECC_MDR];
196         trace_ecc_mem_readl_mdr(ret);
197         break;
198     case ECC_MFSR:
199         ret = s->regs[ECC_MFSR];
200         trace_ecc_mem_readl_mfsr(ret);
201         break;
202     case ECC_VCR:
203         ret = s->regs[ECC_VCR];
204         trace_ecc_mem_readl_vcr(ret);
205         break;
206     case ECC_MFAR0:
207         ret = s->regs[ECC_MFAR0];
208         trace_ecc_mem_readl_mfar0(ret);
209         break;
210     case ECC_MFAR1:
211         ret = s->regs[ECC_MFAR1];
212         trace_ecc_mem_readl_mfar1(ret);
213         break;
214     case ECC_DR:
215         ret = s->regs[ECC_DR];
216         trace_ecc_mem_readl_dr(ret);
217         break;
218     case ECC_ECR0:
219         ret = s->regs[ECC_ECR0];
220         trace_ecc_mem_readl_ecr0(ret);
221         break;
222     case ECC_ECR1:
223         ret = s->regs[ECC_ECR0];
224         trace_ecc_mem_readl_ecr1(ret);
225         break;
226     }
227     return ret;
228 }
229 
230 static const MemoryRegionOps ecc_mem_ops = {
231     .read = ecc_mem_read,
232     .write = ecc_mem_write,
233     .endianness = DEVICE_NATIVE_ENDIAN,
234     .valid = {
235         .min_access_size = 4,
236         .max_access_size = 4,
237     },
238 };
239 
240 static void ecc_diag_mem_write(void *opaque, hwaddr addr,
241                                uint64_t val, unsigned size)
242 {
243     ECCState *s = opaque;
244 
245     trace_ecc_diag_mem_writeb(addr, val);
246     s->diag[addr & ECC_DIAG_MASK] = val;
247 }
248 
249 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
250                                   unsigned size)
251 {
252     ECCState *s = opaque;
253     uint32_t ret = s->diag[(int)addr];
254 
255     trace_ecc_diag_mem_readb(addr, ret);
256     return ret;
257 }
258 
259 static const MemoryRegionOps ecc_diag_mem_ops = {
260     .read = ecc_diag_mem_read,
261     .write = ecc_diag_mem_write,
262     .endianness = DEVICE_NATIVE_ENDIAN,
263     .valid = {
264         .min_access_size = 1,
265         .max_access_size = 1,
266     },
267 };
268 
269 static const VMStateDescription vmstate_ecc = {
270     .name ="ECC",
271     .version_id = 3,
272     .minimum_version_id = 3,
273     .fields = (VMStateField[]) {
274         VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
275         VMSTATE_BUFFER(diag, ECCState),
276         VMSTATE_UINT32(version, ECCState),
277         VMSTATE_END_OF_LIST()
278     }
279 };
280 
281 static void ecc_reset(DeviceState *d)
282 {
283     ECCState *s = ECC_MEMCTL(d);
284 
285     if (s->version == ECC_MCC) {
286         s->regs[ECC_MER] &= ECC_MER_REU;
287     } else {
288         s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
289                              ECC_MER_DCI);
290     }
291     s->regs[ECC_MDR] = 0x20;
292     s->regs[ECC_MFSR] = 0;
293     s->regs[ECC_VCR] = 0;
294     s->regs[ECC_MFAR0] = 0x07c00000;
295     s->regs[ECC_MFAR1] = 0;
296     s->regs[ECC_DR] = 0;
297     s->regs[ECC_ECR0] = 0;
298     s->regs[ECC_ECR1] = 0;
299 }
300 
301 static void ecc_init(Object *obj)
302 {
303     ECCState *s = ECC_MEMCTL(obj);
304     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
305 
306     sysbus_init_irq(dev, &s->irq);
307 
308     memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);
309     sysbus_init_mmio(dev, &s->iomem);
310 }
311 
312 static void ecc_realize(DeviceState *dev, Error **errp)
313 {
314     ECCState *s = ECC_MEMCTL(dev);
315     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
316 
317     s->regs[0] = s->version;
318 
319     if (s->version == ECC_MCC) { // SS-600MP only
320         memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
321                               "ecc.diag", ECC_DIAG_SIZE);
322         sysbus_init_mmio(sbd, &s->iomem_diag);
323     }
324 }
325 
326 static Property ecc_properties[] = {
327     DEFINE_PROP_UINT32("version", ECCState, version, -1),
328     DEFINE_PROP_END_OF_LIST(),
329 };
330 
331 static void ecc_class_init(ObjectClass *klass, void *data)
332 {
333     DeviceClass *dc = DEVICE_CLASS(klass);
334 
335     dc->realize = ecc_realize;
336     dc->reset = ecc_reset;
337     dc->vmsd = &vmstate_ecc;
338     dc->props = ecc_properties;
339 }
340 
341 static const TypeInfo ecc_info = {
342     .name          = TYPE_ECC_MEMCTL,
343     .parent        = TYPE_SYS_BUS_DEVICE,
344     .instance_size = sizeof(ECCState),
345     .instance_init = ecc_init,
346     .class_init    = ecc_class_init,
347 };
348 
349 
350 static void ecc_register_types(void)
351 {
352     type_register_static(&ecc_info);
353 }
354 
355 type_init(ecc_register_types)
356