1 /* 2 * QEMU Sparc Sun4m ECC memory controller emulation 3 * 4 * Copyright (c) 2007 Robert Reif 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "trace.h" 28 29 /* There are 3 versions of this chip used in SMP sun4m systems: 30 * MCC (version 0, implementation 0) SS-600MP 31 * EMC (version 0, implementation 1) SS-10 32 * SMC (version 0, implementation 2) SS-10SX and SS-20 33 * 34 * Chipset docs: 35 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, 36 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf 37 */ 38 39 #define ECC_MCC 0x00000000 40 #define ECC_EMC 0x10000000 41 #define ECC_SMC 0x20000000 42 43 /* Register indexes */ 44 #define ECC_MER 0 /* Memory Enable Register */ 45 #define ECC_MDR 1 /* Memory Delay Register */ 46 #define ECC_MFSR 2 /* Memory Fault Status Register */ 47 #define ECC_VCR 3 /* Video Configuration Register */ 48 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ 49 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ 50 #define ECC_DR 6 /* Diagnostic Register */ 51 #define ECC_ECR0 7 /* Event Count Register 0 */ 52 #define ECC_ECR1 8 /* Event Count Register 1 */ 53 54 /* ECC fault control register */ 55 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ 56 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on 57 correctable errors */ 58 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ 59 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ 60 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ 61 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ 62 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ 63 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ 64 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ 65 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ 66 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ 67 #define ECC_MER_MRR 0x000003fc /* MRR mask */ 68 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ 69 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ 70 #define ECC_MER_VER 0x0f000000 /* Version */ 71 #define ECC_MER_IMPL 0xf0000000 /* Implementation */ 72 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ 73 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ 74 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ 75 76 /* ECC memory delay register */ 77 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ 78 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ 79 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ 80 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ 81 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ 82 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ 83 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ 84 #define ECC_MDR_MASK 0x7fffffff 85 86 /* ECC fault status register */ 87 #define ECC_MFSR_CE 0x00000001 /* Correctable error */ 88 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ 89 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ 90 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ 91 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ 92 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ 93 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ 94 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ 95 96 /* ECC fault address register 0 */ 97 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ 98 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ 99 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ 100 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ 101 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ 102 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ 103 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ 104 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ 105 #define ECC_MFARO_MID 0xf0000000 /* Module ID */ 106 107 /* ECC diagnostic register */ 108 #define ECC_DR_CBX 0x00000001 109 #define ECC_DR_CB0 0x00000002 110 #define ECC_DR_CB1 0x00000004 111 #define ECC_DR_CB2 0x00000008 112 #define ECC_DR_CB4 0x00000010 113 #define ECC_DR_CB8 0x00000020 114 #define ECC_DR_CB16 0x00000040 115 #define ECC_DR_CB32 0x00000080 116 #define ECC_DR_DMODE 0x00000c00 117 118 #define ECC_NREGS 9 119 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) 120 121 #define ECC_DIAG_SIZE 4 122 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) 123 124 #define TYPE_ECC_MEMCTL "eccmemctl" 125 #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL) 126 127 typedef struct ECCState { 128 SysBusDevice parent_obj; 129 130 MemoryRegion iomem, iomem_diag; 131 qemu_irq irq; 132 uint32_t regs[ECC_NREGS]; 133 uint8_t diag[ECC_DIAG_SIZE]; 134 uint32_t version; 135 } ECCState; 136 137 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, 138 unsigned size) 139 { 140 ECCState *s = opaque; 141 142 switch (addr >> 2) { 143 case ECC_MER: 144 if (s->version == ECC_MCC) 145 s->regs[ECC_MER] = (val & ECC_MER_MASK_0); 146 else if (s->version == ECC_EMC) 147 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); 148 else if (s->version == ECC_SMC) 149 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); 150 trace_ecc_mem_writel_mer(val); 151 break; 152 case ECC_MDR: 153 s->regs[ECC_MDR] = val & ECC_MDR_MASK; 154 trace_ecc_mem_writel_mdr(val); 155 break; 156 case ECC_MFSR: 157 s->regs[ECC_MFSR] = val; 158 qemu_irq_lower(s->irq); 159 trace_ecc_mem_writel_mfsr(val); 160 break; 161 case ECC_VCR: 162 s->regs[ECC_VCR] = val; 163 trace_ecc_mem_writel_vcr(val); 164 break; 165 case ECC_DR: 166 s->regs[ECC_DR] = val; 167 trace_ecc_mem_writel_dr(val); 168 break; 169 case ECC_ECR0: 170 s->regs[ECC_ECR0] = val; 171 trace_ecc_mem_writel_ecr0(val); 172 break; 173 case ECC_ECR1: 174 s->regs[ECC_ECR0] = val; 175 trace_ecc_mem_writel_ecr1(val); 176 break; 177 } 178 } 179 180 static uint64_t ecc_mem_read(void *opaque, hwaddr addr, 181 unsigned size) 182 { 183 ECCState *s = opaque; 184 uint32_t ret = 0; 185 186 switch (addr >> 2) { 187 case ECC_MER: 188 ret = s->regs[ECC_MER]; 189 trace_ecc_mem_readl_mer(ret); 190 break; 191 case ECC_MDR: 192 ret = s->regs[ECC_MDR]; 193 trace_ecc_mem_readl_mdr(ret); 194 break; 195 case ECC_MFSR: 196 ret = s->regs[ECC_MFSR]; 197 trace_ecc_mem_readl_mfsr(ret); 198 break; 199 case ECC_VCR: 200 ret = s->regs[ECC_VCR]; 201 trace_ecc_mem_readl_vcr(ret); 202 break; 203 case ECC_MFAR0: 204 ret = s->regs[ECC_MFAR0]; 205 trace_ecc_mem_readl_mfar0(ret); 206 break; 207 case ECC_MFAR1: 208 ret = s->regs[ECC_MFAR1]; 209 trace_ecc_mem_readl_mfar1(ret); 210 break; 211 case ECC_DR: 212 ret = s->regs[ECC_DR]; 213 trace_ecc_mem_readl_dr(ret); 214 break; 215 case ECC_ECR0: 216 ret = s->regs[ECC_ECR0]; 217 trace_ecc_mem_readl_ecr0(ret); 218 break; 219 case ECC_ECR1: 220 ret = s->regs[ECC_ECR0]; 221 trace_ecc_mem_readl_ecr1(ret); 222 break; 223 } 224 return ret; 225 } 226 227 static const MemoryRegionOps ecc_mem_ops = { 228 .read = ecc_mem_read, 229 .write = ecc_mem_write, 230 .endianness = DEVICE_NATIVE_ENDIAN, 231 .valid = { 232 .min_access_size = 4, 233 .max_access_size = 4, 234 }, 235 }; 236 237 static void ecc_diag_mem_write(void *opaque, hwaddr addr, 238 uint64_t val, unsigned size) 239 { 240 ECCState *s = opaque; 241 242 trace_ecc_diag_mem_writeb(addr, val); 243 s->diag[addr & ECC_DIAG_MASK] = val; 244 } 245 246 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, 247 unsigned size) 248 { 249 ECCState *s = opaque; 250 uint32_t ret = s->diag[(int)addr]; 251 252 trace_ecc_diag_mem_readb(addr, ret); 253 return ret; 254 } 255 256 static const MemoryRegionOps ecc_diag_mem_ops = { 257 .read = ecc_diag_mem_read, 258 .write = ecc_diag_mem_write, 259 .endianness = DEVICE_NATIVE_ENDIAN, 260 .valid = { 261 .min_access_size = 1, 262 .max_access_size = 1, 263 }, 264 }; 265 266 static const VMStateDescription vmstate_ecc = { 267 .name ="ECC", 268 .version_id = 3, 269 .minimum_version_id = 3, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), 272 VMSTATE_BUFFER(diag, ECCState), 273 VMSTATE_UINT32(version, ECCState), 274 VMSTATE_END_OF_LIST() 275 } 276 }; 277 278 static void ecc_reset(DeviceState *d) 279 { 280 ECCState *s = ECC_MEMCTL(d); 281 282 if (s->version == ECC_MCC) { 283 s->regs[ECC_MER] &= ECC_MER_REU; 284 } else { 285 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | 286 ECC_MER_DCI); 287 } 288 s->regs[ECC_MDR] = 0x20; 289 s->regs[ECC_MFSR] = 0; 290 s->regs[ECC_VCR] = 0; 291 s->regs[ECC_MFAR0] = 0x07c00000; 292 s->regs[ECC_MFAR1] = 0; 293 s->regs[ECC_DR] = 0; 294 s->regs[ECC_ECR0] = 0; 295 s->regs[ECC_ECR1] = 0; 296 } 297 298 static void ecc_init(Object *obj) 299 { 300 ECCState *s = ECC_MEMCTL(obj); 301 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 302 303 sysbus_init_irq(dev, &s->irq); 304 305 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); 306 sysbus_init_mmio(dev, &s->iomem); 307 } 308 309 static void ecc_realize(DeviceState *dev, Error **errp) 310 { 311 ECCState *s = ECC_MEMCTL(dev); 312 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 313 314 s->regs[0] = s->version; 315 316 if (s->version == ECC_MCC) { // SS-600MP only 317 memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, 318 "ecc.diag", ECC_DIAG_SIZE); 319 sysbus_init_mmio(sbd, &s->iomem_diag); 320 } 321 } 322 323 static Property ecc_properties[] = { 324 DEFINE_PROP_UINT32("version", ECCState, version, -1), 325 DEFINE_PROP_END_OF_LIST(), 326 }; 327 328 static void ecc_class_init(ObjectClass *klass, void *data) 329 { 330 DeviceClass *dc = DEVICE_CLASS(klass); 331 332 dc->realize = ecc_realize; 333 dc->reset = ecc_reset; 334 dc->vmsd = &vmstate_ecc; 335 dc->props = ecc_properties; 336 } 337 338 static const TypeInfo ecc_info = { 339 .name = TYPE_ECC_MEMCTL, 340 .parent = TYPE_SYS_BUS_DEVICE, 341 .instance_size = sizeof(ECCState), 342 .instance_init = ecc_init, 343 .class_init = ecc_class_init, 344 }; 345 346 347 static void ecc_register_types(void) 348 { 349 type_register_static(&ecc_info); 350 } 351 352 type_init(ecc_register_types) 353