1 /* 2 * QEMU Sparc Sun4m ECC memory controller emulation 3 * 4 * Copyright (c) 2007 Robert Reif 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/sysbus.h" 28 #include "qemu/module.h" 29 #include "trace.h" 30 31 /* There are 3 versions of this chip used in SMP sun4m systems: 32 * MCC (version 0, implementation 0) SS-600MP 33 * EMC (version 0, implementation 1) SS-10 34 * SMC (version 0, implementation 2) SS-10SX and SS-20 35 * 36 * Chipset docs: 37 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, 38 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf 39 */ 40 41 #define ECC_MCC 0x00000000 42 #define ECC_EMC 0x10000000 43 #define ECC_SMC 0x20000000 44 45 /* Register indexes */ 46 #define ECC_MER 0 /* Memory Enable Register */ 47 #define ECC_MDR 1 /* Memory Delay Register */ 48 #define ECC_MFSR 2 /* Memory Fault Status Register */ 49 #define ECC_VCR 3 /* Video Configuration Register */ 50 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ 51 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ 52 #define ECC_DR 6 /* Diagnostic Register */ 53 #define ECC_ECR0 7 /* Event Count Register 0 */ 54 #define ECC_ECR1 8 /* Event Count Register 1 */ 55 56 /* ECC fault control register */ 57 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ 58 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on 59 correctable errors */ 60 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ 61 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ 62 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ 63 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ 64 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ 65 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ 66 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ 67 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ 68 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ 69 #define ECC_MER_MRR 0x000003fc /* MRR mask */ 70 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ 71 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ 72 #define ECC_MER_VER 0x0f000000 /* Version */ 73 #define ECC_MER_IMPL 0xf0000000 /* Implementation */ 74 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ 75 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ 76 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ 77 78 /* ECC memory delay register */ 79 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ 80 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ 81 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ 82 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ 83 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ 84 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ 85 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ 86 #define ECC_MDR_MASK 0x7fffffff 87 88 /* ECC fault status register */ 89 #define ECC_MFSR_CE 0x00000001 /* Correctable error */ 90 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ 91 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ 92 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ 93 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ 94 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ 95 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ 96 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ 97 98 /* ECC fault address register 0 */ 99 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ 100 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ 101 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ 102 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ 103 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ 104 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ 105 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ 106 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ 107 #define ECC_MFARO_MID 0xf0000000 /* Module ID */ 108 109 /* ECC diagnostic register */ 110 #define ECC_DR_CBX 0x00000001 111 #define ECC_DR_CB0 0x00000002 112 #define ECC_DR_CB1 0x00000004 113 #define ECC_DR_CB2 0x00000008 114 #define ECC_DR_CB4 0x00000010 115 #define ECC_DR_CB8 0x00000020 116 #define ECC_DR_CB16 0x00000040 117 #define ECC_DR_CB32 0x00000080 118 #define ECC_DR_DMODE 0x00000c00 119 120 #define ECC_NREGS 9 121 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) 122 123 #define ECC_DIAG_SIZE 4 124 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) 125 126 #define TYPE_ECC_MEMCTL "eccmemctl" 127 #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL) 128 129 typedef struct ECCState { 130 SysBusDevice parent_obj; 131 132 MemoryRegion iomem, iomem_diag; 133 qemu_irq irq; 134 uint32_t regs[ECC_NREGS]; 135 uint8_t diag[ECC_DIAG_SIZE]; 136 uint32_t version; 137 } ECCState; 138 139 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, 140 unsigned size) 141 { 142 ECCState *s = opaque; 143 144 switch (addr >> 2) { 145 case ECC_MER: 146 if (s->version == ECC_MCC) 147 s->regs[ECC_MER] = (val & ECC_MER_MASK_0); 148 else if (s->version == ECC_EMC) 149 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); 150 else if (s->version == ECC_SMC) 151 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); 152 trace_ecc_mem_writel_mer(val); 153 break; 154 case ECC_MDR: 155 s->regs[ECC_MDR] = val & ECC_MDR_MASK; 156 trace_ecc_mem_writel_mdr(val); 157 break; 158 case ECC_MFSR: 159 s->regs[ECC_MFSR] = val; 160 qemu_irq_lower(s->irq); 161 trace_ecc_mem_writel_mfsr(val); 162 break; 163 case ECC_VCR: 164 s->regs[ECC_VCR] = val; 165 trace_ecc_mem_writel_vcr(val); 166 break; 167 case ECC_DR: 168 s->regs[ECC_DR] = val; 169 trace_ecc_mem_writel_dr(val); 170 break; 171 case ECC_ECR0: 172 s->regs[ECC_ECR0] = val; 173 trace_ecc_mem_writel_ecr0(val); 174 break; 175 case ECC_ECR1: 176 s->regs[ECC_ECR0] = val; 177 trace_ecc_mem_writel_ecr1(val); 178 break; 179 } 180 } 181 182 static uint64_t ecc_mem_read(void *opaque, hwaddr addr, 183 unsigned size) 184 { 185 ECCState *s = opaque; 186 uint32_t ret = 0; 187 188 switch (addr >> 2) { 189 case ECC_MER: 190 ret = s->regs[ECC_MER]; 191 trace_ecc_mem_readl_mer(ret); 192 break; 193 case ECC_MDR: 194 ret = s->regs[ECC_MDR]; 195 trace_ecc_mem_readl_mdr(ret); 196 break; 197 case ECC_MFSR: 198 ret = s->regs[ECC_MFSR]; 199 trace_ecc_mem_readl_mfsr(ret); 200 break; 201 case ECC_VCR: 202 ret = s->regs[ECC_VCR]; 203 trace_ecc_mem_readl_vcr(ret); 204 break; 205 case ECC_MFAR0: 206 ret = s->regs[ECC_MFAR0]; 207 trace_ecc_mem_readl_mfar0(ret); 208 break; 209 case ECC_MFAR1: 210 ret = s->regs[ECC_MFAR1]; 211 trace_ecc_mem_readl_mfar1(ret); 212 break; 213 case ECC_DR: 214 ret = s->regs[ECC_DR]; 215 trace_ecc_mem_readl_dr(ret); 216 break; 217 case ECC_ECR0: 218 ret = s->regs[ECC_ECR0]; 219 trace_ecc_mem_readl_ecr0(ret); 220 break; 221 case ECC_ECR1: 222 ret = s->regs[ECC_ECR0]; 223 trace_ecc_mem_readl_ecr1(ret); 224 break; 225 } 226 return ret; 227 } 228 229 static const MemoryRegionOps ecc_mem_ops = { 230 .read = ecc_mem_read, 231 .write = ecc_mem_write, 232 .endianness = DEVICE_NATIVE_ENDIAN, 233 .valid = { 234 .min_access_size = 4, 235 .max_access_size = 4, 236 }, 237 }; 238 239 static void ecc_diag_mem_write(void *opaque, hwaddr addr, 240 uint64_t val, unsigned size) 241 { 242 ECCState *s = opaque; 243 244 trace_ecc_diag_mem_writeb(addr, val); 245 s->diag[addr & ECC_DIAG_MASK] = val; 246 } 247 248 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, 249 unsigned size) 250 { 251 ECCState *s = opaque; 252 uint32_t ret = s->diag[(int)addr]; 253 254 trace_ecc_diag_mem_readb(addr, ret); 255 return ret; 256 } 257 258 static const MemoryRegionOps ecc_diag_mem_ops = { 259 .read = ecc_diag_mem_read, 260 .write = ecc_diag_mem_write, 261 .endianness = DEVICE_NATIVE_ENDIAN, 262 .valid = { 263 .min_access_size = 1, 264 .max_access_size = 1, 265 }, 266 }; 267 268 static const VMStateDescription vmstate_ecc = { 269 .name ="ECC", 270 .version_id = 3, 271 .minimum_version_id = 3, 272 .fields = (VMStateField[]) { 273 VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), 274 VMSTATE_BUFFER(diag, ECCState), 275 VMSTATE_UINT32(version, ECCState), 276 VMSTATE_END_OF_LIST() 277 } 278 }; 279 280 static void ecc_reset(DeviceState *d) 281 { 282 ECCState *s = ECC_MEMCTL(d); 283 284 if (s->version == ECC_MCC) { 285 s->regs[ECC_MER] &= ECC_MER_REU; 286 } else { 287 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | 288 ECC_MER_DCI); 289 } 290 s->regs[ECC_MDR] = 0x20; 291 s->regs[ECC_MFSR] = 0; 292 s->regs[ECC_VCR] = 0; 293 s->regs[ECC_MFAR0] = 0x07c00000; 294 s->regs[ECC_MFAR1] = 0; 295 s->regs[ECC_DR] = 0; 296 s->regs[ECC_ECR0] = 0; 297 s->regs[ECC_ECR1] = 0; 298 } 299 300 static void ecc_init(Object *obj) 301 { 302 ECCState *s = ECC_MEMCTL(obj); 303 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 304 305 sysbus_init_irq(dev, &s->irq); 306 307 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); 308 sysbus_init_mmio(dev, &s->iomem); 309 } 310 311 static void ecc_realize(DeviceState *dev, Error **errp) 312 { 313 ECCState *s = ECC_MEMCTL(dev); 314 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 315 316 s->regs[0] = s->version; 317 318 if (s->version == ECC_MCC) { // SS-600MP only 319 memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, 320 "ecc.diag", ECC_DIAG_SIZE); 321 sysbus_init_mmio(sbd, &s->iomem_diag); 322 } 323 } 324 325 static Property ecc_properties[] = { 326 DEFINE_PROP_UINT32("version", ECCState, version, -1), 327 DEFINE_PROP_END_OF_LIST(), 328 }; 329 330 static void ecc_class_init(ObjectClass *klass, void *data) 331 { 332 DeviceClass *dc = DEVICE_CLASS(klass); 333 334 dc->realize = ecc_realize; 335 dc->reset = ecc_reset; 336 dc->vmsd = &vmstate_ecc; 337 dc->props = ecc_properties; 338 } 339 340 static const TypeInfo ecc_info = { 341 .name = TYPE_ECC_MEMCTL, 342 .parent = TYPE_SYS_BUS_DEVICE, 343 .instance_size = sizeof(ECCState), 344 .instance_init = ecc_init, 345 .class_init = ecc_class_init, 346 }; 347 348 349 static void ecc_register_types(void) 350 { 351 type_register_static(&ecc_info); 352 } 353 354 type_init(ecc_register_types) 355