1 /* 2 * QEMU Sparc Sun4m ECC memory controller emulation 3 * 4 * Copyright (c) 2007 Robert Reif 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qemu/module.h" 28 #include "trace.h" 29 30 /* There are 3 versions of this chip used in SMP sun4m systems: 31 * MCC (version 0, implementation 0) SS-600MP 32 * EMC (version 0, implementation 1) SS-10 33 * SMC (version 0, implementation 2) SS-10SX and SS-20 34 * 35 * Chipset docs: 36 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, 37 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf 38 */ 39 40 #define ECC_MCC 0x00000000 41 #define ECC_EMC 0x10000000 42 #define ECC_SMC 0x20000000 43 44 /* Register indexes */ 45 #define ECC_MER 0 /* Memory Enable Register */ 46 #define ECC_MDR 1 /* Memory Delay Register */ 47 #define ECC_MFSR 2 /* Memory Fault Status Register */ 48 #define ECC_VCR 3 /* Video Configuration Register */ 49 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ 50 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ 51 #define ECC_DR 6 /* Diagnostic Register */ 52 #define ECC_ECR0 7 /* Event Count Register 0 */ 53 #define ECC_ECR1 8 /* Event Count Register 1 */ 54 55 /* ECC fault control register */ 56 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ 57 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on 58 correctable errors */ 59 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ 60 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ 61 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ 62 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ 63 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ 64 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ 65 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ 66 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ 67 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ 68 #define ECC_MER_MRR 0x000003fc /* MRR mask */ 69 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ 70 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ 71 #define ECC_MER_VER 0x0f000000 /* Version */ 72 #define ECC_MER_IMPL 0xf0000000 /* Implementation */ 73 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ 74 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ 75 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ 76 77 /* ECC memory delay register */ 78 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ 79 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ 80 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ 81 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ 82 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ 83 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ 84 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ 85 #define ECC_MDR_MASK 0x7fffffff 86 87 /* ECC fault status register */ 88 #define ECC_MFSR_CE 0x00000001 /* Correctable error */ 89 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ 90 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ 91 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ 92 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ 93 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ 94 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ 95 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ 96 97 /* ECC fault address register 0 */ 98 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ 99 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ 100 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ 101 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ 102 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ 103 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ 104 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ 105 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ 106 #define ECC_MFARO_MID 0xf0000000 /* Module ID */ 107 108 /* ECC diagnostic register */ 109 #define ECC_DR_CBX 0x00000001 110 #define ECC_DR_CB0 0x00000002 111 #define ECC_DR_CB1 0x00000004 112 #define ECC_DR_CB2 0x00000008 113 #define ECC_DR_CB4 0x00000010 114 #define ECC_DR_CB8 0x00000020 115 #define ECC_DR_CB16 0x00000040 116 #define ECC_DR_CB32 0x00000080 117 #define ECC_DR_DMODE 0x00000c00 118 119 #define ECC_NREGS 9 120 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) 121 122 #define ECC_DIAG_SIZE 4 123 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) 124 125 #define TYPE_ECC_MEMCTL "eccmemctl" 126 #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL) 127 128 typedef struct ECCState { 129 SysBusDevice parent_obj; 130 131 MemoryRegion iomem, iomem_diag; 132 qemu_irq irq; 133 uint32_t regs[ECC_NREGS]; 134 uint8_t diag[ECC_DIAG_SIZE]; 135 uint32_t version; 136 } ECCState; 137 138 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, 139 unsigned size) 140 { 141 ECCState *s = opaque; 142 143 switch (addr >> 2) { 144 case ECC_MER: 145 if (s->version == ECC_MCC) 146 s->regs[ECC_MER] = (val & ECC_MER_MASK_0); 147 else if (s->version == ECC_EMC) 148 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); 149 else if (s->version == ECC_SMC) 150 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); 151 trace_ecc_mem_writel_mer(val); 152 break; 153 case ECC_MDR: 154 s->regs[ECC_MDR] = val & ECC_MDR_MASK; 155 trace_ecc_mem_writel_mdr(val); 156 break; 157 case ECC_MFSR: 158 s->regs[ECC_MFSR] = val; 159 qemu_irq_lower(s->irq); 160 trace_ecc_mem_writel_mfsr(val); 161 break; 162 case ECC_VCR: 163 s->regs[ECC_VCR] = val; 164 trace_ecc_mem_writel_vcr(val); 165 break; 166 case ECC_DR: 167 s->regs[ECC_DR] = val; 168 trace_ecc_mem_writel_dr(val); 169 break; 170 case ECC_ECR0: 171 s->regs[ECC_ECR0] = val; 172 trace_ecc_mem_writel_ecr0(val); 173 break; 174 case ECC_ECR1: 175 s->regs[ECC_ECR0] = val; 176 trace_ecc_mem_writel_ecr1(val); 177 break; 178 } 179 } 180 181 static uint64_t ecc_mem_read(void *opaque, hwaddr addr, 182 unsigned size) 183 { 184 ECCState *s = opaque; 185 uint32_t ret = 0; 186 187 switch (addr >> 2) { 188 case ECC_MER: 189 ret = s->regs[ECC_MER]; 190 trace_ecc_mem_readl_mer(ret); 191 break; 192 case ECC_MDR: 193 ret = s->regs[ECC_MDR]; 194 trace_ecc_mem_readl_mdr(ret); 195 break; 196 case ECC_MFSR: 197 ret = s->regs[ECC_MFSR]; 198 trace_ecc_mem_readl_mfsr(ret); 199 break; 200 case ECC_VCR: 201 ret = s->regs[ECC_VCR]; 202 trace_ecc_mem_readl_vcr(ret); 203 break; 204 case ECC_MFAR0: 205 ret = s->regs[ECC_MFAR0]; 206 trace_ecc_mem_readl_mfar0(ret); 207 break; 208 case ECC_MFAR1: 209 ret = s->regs[ECC_MFAR1]; 210 trace_ecc_mem_readl_mfar1(ret); 211 break; 212 case ECC_DR: 213 ret = s->regs[ECC_DR]; 214 trace_ecc_mem_readl_dr(ret); 215 break; 216 case ECC_ECR0: 217 ret = s->regs[ECC_ECR0]; 218 trace_ecc_mem_readl_ecr0(ret); 219 break; 220 case ECC_ECR1: 221 ret = s->regs[ECC_ECR0]; 222 trace_ecc_mem_readl_ecr1(ret); 223 break; 224 } 225 return ret; 226 } 227 228 static const MemoryRegionOps ecc_mem_ops = { 229 .read = ecc_mem_read, 230 .write = ecc_mem_write, 231 .endianness = DEVICE_NATIVE_ENDIAN, 232 .valid = { 233 .min_access_size = 4, 234 .max_access_size = 4, 235 }, 236 }; 237 238 static void ecc_diag_mem_write(void *opaque, hwaddr addr, 239 uint64_t val, unsigned size) 240 { 241 ECCState *s = opaque; 242 243 trace_ecc_diag_mem_writeb(addr, val); 244 s->diag[addr & ECC_DIAG_MASK] = val; 245 } 246 247 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, 248 unsigned size) 249 { 250 ECCState *s = opaque; 251 uint32_t ret = s->diag[(int)addr]; 252 253 trace_ecc_diag_mem_readb(addr, ret); 254 return ret; 255 } 256 257 static const MemoryRegionOps ecc_diag_mem_ops = { 258 .read = ecc_diag_mem_read, 259 .write = ecc_diag_mem_write, 260 .endianness = DEVICE_NATIVE_ENDIAN, 261 .valid = { 262 .min_access_size = 1, 263 .max_access_size = 1, 264 }, 265 }; 266 267 static const VMStateDescription vmstate_ecc = { 268 .name ="ECC", 269 .version_id = 3, 270 .minimum_version_id = 3, 271 .fields = (VMStateField[]) { 272 VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), 273 VMSTATE_BUFFER(diag, ECCState), 274 VMSTATE_UINT32(version, ECCState), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 static void ecc_reset(DeviceState *d) 280 { 281 ECCState *s = ECC_MEMCTL(d); 282 283 if (s->version == ECC_MCC) { 284 s->regs[ECC_MER] &= ECC_MER_REU; 285 } else { 286 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | 287 ECC_MER_DCI); 288 } 289 s->regs[ECC_MDR] = 0x20; 290 s->regs[ECC_MFSR] = 0; 291 s->regs[ECC_VCR] = 0; 292 s->regs[ECC_MFAR0] = 0x07c00000; 293 s->regs[ECC_MFAR1] = 0; 294 s->regs[ECC_DR] = 0; 295 s->regs[ECC_ECR0] = 0; 296 s->regs[ECC_ECR1] = 0; 297 } 298 299 static void ecc_init(Object *obj) 300 { 301 ECCState *s = ECC_MEMCTL(obj); 302 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 303 304 sysbus_init_irq(dev, &s->irq); 305 306 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); 307 sysbus_init_mmio(dev, &s->iomem); 308 } 309 310 static void ecc_realize(DeviceState *dev, Error **errp) 311 { 312 ECCState *s = ECC_MEMCTL(dev); 313 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 314 315 s->regs[0] = s->version; 316 317 if (s->version == ECC_MCC) { // SS-600MP only 318 memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, 319 "ecc.diag", ECC_DIAG_SIZE); 320 sysbus_init_mmio(sbd, &s->iomem_diag); 321 } 322 } 323 324 static Property ecc_properties[] = { 325 DEFINE_PROP_UINT32("version", ECCState, version, -1), 326 DEFINE_PROP_END_OF_LIST(), 327 }; 328 329 static void ecc_class_init(ObjectClass *klass, void *data) 330 { 331 DeviceClass *dc = DEVICE_CLASS(klass); 332 333 dc->realize = ecc_realize; 334 dc->reset = ecc_reset; 335 dc->vmsd = &vmstate_ecc; 336 dc->props = ecc_properties; 337 } 338 339 static const TypeInfo ecc_info = { 340 .name = TYPE_ECC_MEMCTL, 341 .parent = TYPE_SYS_BUS_DEVICE, 342 .instance_size = sizeof(ECCState), 343 .instance_init = ecc_init, 344 .class_init = ecc_class_init, 345 }; 346 347 348 static void ecc_register_types(void) 349 { 350 type_register_static(&ecc_info); 351 } 352 353 type_init(ecc_register_types) 354