1 /* 2 * BCM2835 SOC MPHI emulation 3 * 4 * Very basic emulation, only providing the FIQ interrupt needed to 5 * allow the dwc-otg USB host controller driver in the Raspbian kernel 6 * to function. 7 * 8 * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/misc/bcm2835_mphi.h" 24 #include "migration/vmstate.h" 25 #include "qemu/error-report.h" 26 #include "qemu/log.h" 27 #include "qemu/main-loop.h" 28 mphi_raise_irq(BCM2835MphiState * s)29 static inline void mphi_raise_irq(BCM2835MphiState *s) 30 { 31 qemu_set_irq(s->irq, 1); 32 } 33 mphi_lower_irq(BCM2835MphiState * s)34 static inline void mphi_lower_irq(BCM2835MphiState *s) 35 { 36 qemu_set_irq(s->irq, 0); 37 } 38 mphi_reg_read(void * ptr,hwaddr addr,unsigned size)39 static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size) 40 { 41 BCM2835MphiState *s = ptr; 42 uint32_t val = 0; 43 44 switch (addr) { 45 case 0x28: /* outdda */ 46 val = s->outdda; 47 break; 48 case 0x2c: /* outddb */ 49 val = s->outddb; 50 break; 51 case 0x4c: /* ctrl */ 52 val = s->ctrl; 53 val |= 1 << 17; 54 break; 55 case 0x50: /* intstat */ 56 val = s->intstat; 57 break; 58 case 0x1f0: /* swirq_set */ 59 val = s->swirq; 60 break; 61 case 0x1f4: /* swirq_clr */ 62 val = s->swirq; 63 break; 64 default: 65 qemu_log_mask(LOG_UNIMP, "read from unknown register"); 66 break; 67 } 68 69 return val; 70 } 71 mphi_reg_write(void * ptr,hwaddr addr,uint64_t val,unsigned size)72 static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size) 73 { 74 BCM2835MphiState *s = ptr; 75 int do_irq = 0; 76 77 switch (addr) { 78 case 0x28: /* outdda */ 79 s->outdda = val; 80 break; 81 case 0x2c: /* outddb */ 82 s->outddb = val; 83 if (val & (1 << 29)) { 84 do_irq = 1; 85 } 86 break; 87 case 0x4c: /* ctrl */ 88 s->ctrl = val; 89 if (val & (1 << 16)) { 90 do_irq = -1; 91 } 92 break; 93 case 0x50: /* intstat */ 94 s->intstat = val; 95 if (val & ((1 << 16) | (1 << 29))) { 96 do_irq = -1; 97 } 98 break; 99 case 0x1f0: /* swirq_set */ 100 s->swirq |= val; 101 do_irq = 1; 102 break; 103 case 0x1f4: /* swirq_clr */ 104 s->swirq &= ~val; 105 do_irq = -1; 106 break; 107 default: 108 qemu_log_mask(LOG_UNIMP, "write to unknown register"); 109 return; 110 } 111 112 if (do_irq > 0) { 113 mphi_raise_irq(s); 114 } else if (do_irq < 0) { 115 mphi_lower_irq(s); 116 } 117 } 118 119 static const MemoryRegionOps mphi_mmio_ops = { 120 .read = mphi_reg_read, 121 .write = mphi_reg_write, 122 .impl.min_access_size = 4, 123 .impl.max_access_size = 4, 124 .endianness = DEVICE_LITTLE_ENDIAN, 125 }; 126 mphi_reset(DeviceState * dev)127 static void mphi_reset(DeviceState *dev) 128 { 129 BCM2835MphiState *s = BCM2835_MPHI(dev); 130 131 s->outdda = 0; 132 s->outddb = 0; 133 s->ctrl = 0; 134 s->intstat = 0; 135 s->swirq = 0; 136 } 137 mphi_realize(DeviceState * dev,Error ** errp)138 static void mphi_realize(DeviceState *dev, Error **errp) 139 { 140 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 141 BCM2835MphiState *s = BCM2835_MPHI(dev); 142 143 sysbus_init_irq(sbd, &s->irq); 144 } 145 mphi_init(Object * obj)146 static void mphi_init(Object *obj) 147 { 148 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 149 BCM2835MphiState *s = BCM2835_MPHI(obj); 150 151 memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE); 152 sysbus_init_mmio(sbd, &s->iomem); 153 } 154 155 const VMStateDescription vmstate_mphi_state = { 156 .name = "mphi", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .fields = (const VMStateField[]) { 160 VMSTATE_UINT32(outdda, BCM2835MphiState), 161 VMSTATE_UINT32(outddb, BCM2835MphiState), 162 VMSTATE_UINT32(ctrl, BCM2835MphiState), 163 VMSTATE_UINT32(intstat, BCM2835MphiState), 164 VMSTATE_UINT32(swirq, BCM2835MphiState), 165 VMSTATE_END_OF_LIST() 166 } 167 }; 168 mphi_class_init(ObjectClass * klass,void * data)169 static void mphi_class_init(ObjectClass *klass, void *data) 170 { 171 DeviceClass *dc = DEVICE_CLASS(klass); 172 173 dc->realize = mphi_realize; 174 device_class_set_legacy_reset(dc, mphi_reset); 175 dc->vmsd = &vmstate_mphi_state; 176 } 177 178 static const TypeInfo bcm2835_mphi_type_info = { 179 .name = TYPE_BCM2835_MPHI, 180 .parent = TYPE_SYS_BUS_DEVICE, 181 .instance_size = sizeof(BCM2835MphiState), 182 .instance_init = mphi_init, 183 .class_init = mphi_class_init, 184 }; 185 bcm2835_mphi_register_types(void)186 static void bcm2835_mphi_register_types(void) 187 { 188 type_register_static(&bcm2835_mphi_type_info); 189 } 190 191 type_init(bcm2835_mphi_register_types) 192