1 /* 2 * BCM2835 CPRMAN clock manager 3 * 4 * Copyright (c) 2020 Luc Michel <luc@lmichel.fr> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 /* 10 * This peripheral is roughly divided into 3 main parts: 11 * - the PLLs 12 * - the PLL channels 13 * - the clock muxes 14 * 15 * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more 16 * channels. Those channel are then connected to the clock muxes. Each mux has 17 * multiples sources (usually the xosc, some of the PLL channels and some "test 18 * debug" clocks). A mux is configured to select a given source through its 19 * control register. Each mux has one output clock that also goes out of the 20 * CPRMAN. This output clock usually connects to another peripheral in the SoC 21 * (so a given mux is dedicated to a peripheral). 22 * 23 * At each level (PLL, channel and mux), the clock can be altered through 24 * dividers (and multipliers in case of the PLLs), and can be disabled (in this 25 * case, the next levels see no clock). 26 * 27 * This can be sum-up as follows (this is an example and not the actual BCM2835 28 * clock tree): 29 * 30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals 31 * | |->[PLL channel] muxes takes [mux] 32 * | \->[PLL channel] inputs from [mux] 33 * | some channels [mux] 34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux] 35 * | \->[PLL channel] ...-->[mux] 36 * | [mux] 37 * \-->[PLL]--->[PLL channel] [mux] 38 * 39 * The page at https://elinux.org/The_Undocumented_Pi gives the actual clock 40 * tree configuration. 41 * 42 * The CPRMAN exposes clock outputs with the name of the clock mux suffixed 43 * with "-out" (e.g. "uart-out", "h264-out", ...). 44 */ 45 46 #include "qemu/osdep.h" 47 #include "qemu/log.h" 48 #include "migration/vmstate.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/misc/bcm2835_cprman.h" 51 #include "hw/misc/bcm2835_cprman_internals.h" 52 #include "trace.h" 53 54 /* PLL */ 55 56 static void pll_reset(DeviceState *dev) 57 { 58 CprmanPllState *s = CPRMAN_PLL(dev); 59 const PLLResetInfo *info = &PLL_RESET_INFO[s->id]; 60 61 *s->reg_cm = info->cm; 62 *s->reg_a2w_ctrl = info->a2w_ctrl; 63 memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana)); 64 *s->reg_a2w_frac = info->a2w_frac; 65 } 66 67 static bool pll_is_locked(const CprmanPllState *pll) 68 { 69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) 70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); 71 } 72 73 static void pll_update(CprmanPllState *pll) 74 { 75 uint64_t freq, ndiv, fdiv, pdiv; 76 77 if (!pll_is_locked(pll)) { 78 clock_update(pll->out, 0); 79 return; 80 } 81 82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); 83 84 if (!pdiv) { 85 clock_update(pll->out, 0); 86 return; 87 } 88 89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); 90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); 91 92 if (pll->reg_a2w_ana[1] & pll->prediv_mask) { 93 /* The prescaler doubles the parent frequency */ 94 ndiv *= 2; 95 fdiv *= 2; 96 } 97 98 /* 99 * We have a multiplier with an integer part (ndiv) and a fractional part 100 * (fdiv), and a divider (pdiv). 101 */ 102 freq = clock_get_hz(pll->xosc_in) * 103 ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); 104 freq /= pdiv; 105 freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH; 106 107 clock_update_hz(pll->out, freq); 108 } 109 110 static void pll_xosc_update(void *opaque) 111 { 112 pll_update(CPRMAN_PLL(opaque)); 113 } 114 115 static void pll_init(Object *obj) 116 { 117 CprmanPllState *s = CPRMAN_PLL(obj); 118 119 s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, s); 120 s->out = qdev_init_clock_out(DEVICE(s), "out"); 121 } 122 123 static const VMStateDescription pll_vmstate = { 124 .name = TYPE_CPRMAN_PLL, 125 .version_id = 1, 126 .minimum_version_id = 1, 127 .fields = (VMStateField[]) { 128 VMSTATE_CLOCK(xosc_in, CprmanPllState), 129 VMSTATE_END_OF_LIST() 130 } 131 }; 132 133 static void pll_class_init(ObjectClass *klass, void *data) 134 { 135 DeviceClass *dc = DEVICE_CLASS(klass); 136 137 dc->reset = pll_reset; 138 dc->vmsd = &pll_vmstate; 139 } 140 141 static const TypeInfo cprman_pll_info = { 142 .name = TYPE_CPRMAN_PLL, 143 .parent = TYPE_DEVICE, 144 .instance_size = sizeof(CprmanPllState), 145 .class_init = pll_class_init, 146 .instance_init = pll_init, 147 }; 148 149 150 /* PLL channel */ 151 152 static void pll_channel_reset(DeviceState *dev) 153 { 154 CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev); 155 const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id]; 156 157 *s->reg_a2w_ctrl = info->a2w_ctrl; 158 } 159 160 static bool pll_channel_is_enabled(CprmanPllChannelState *channel) 161 { 162 /* 163 * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does 164 * not set it when enabling the channel, but does clear it when disabling 165 * it. 166 */ 167 return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE) 168 && !(*channel->reg_cm & channel->hold_mask); 169 } 170 171 static void pll_channel_update(CprmanPllChannelState *channel) 172 { 173 uint64_t freq, div; 174 175 if (!pll_channel_is_enabled(channel)) { 176 clock_update(channel->out, 0); 177 return; 178 } 179 180 div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); 181 182 if (!div) { 183 /* 184 * It seems that when the divider value is 0, it is considered as 185 * being maximum by the hardware (see the Linux driver). 186 */ 187 div = R_A2W_PLLx_CHANNELy_DIV_MASK; 188 } 189 190 /* Some channels have an additional fixed divider */ 191 freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider); 192 193 clock_update_hz(channel->out, freq); 194 } 195 196 /* Update a PLL and all its channels */ 197 static void pll_update_all_channels(BCM2835CprmanState *s, 198 CprmanPllState *pll) 199 { 200 size_t i; 201 202 pll_update(pll); 203 204 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 205 CprmanPllChannelState *channel = &s->channels[i]; 206 if (channel->parent == pll->id) { 207 pll_channel_update(channel); 208 } 209 } 210 } 211 212 static void pll_channel_pll_in_update(void *opaque) 213 { 214 pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); 215 } 216 217 static void pll_channel_init(Object *obj) 218 { 219 CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj); 220 221 s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in", 222 pll_channel_pll_in_update, s); 223 s->out = qdev_init_clock_out(DEVICE(s), "out"); 224 } 225 226 static const VMStateDescription pll_channel_vmstate = { 227 .name = TYPE_CPRMAN_PLL_CHANNEL, 228 .version_id = 1, 229 .minimum_version_id = 1, 230 .fields = (VMStateField[]) { 231 VMSTATE_CLOCK(pll_in, CprmanPllChannelState), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static void pll_channel_class_init(ObjectClass *klass, void *data) 237 { 238 DeviceClass *dc = DEVICE_CLASS(klass); 239 240 dc->reset = pll_channel_reset; 241 dc->vmsd = &pll_channel_vmstate; 242 } 243 244 static const TypeInfo cprman_pll_channel_info = { 245 .name = TYPE_CPRMAN_PLL_CHANNEL, 246 .parent = TYPE_DEVICE, 247 .instance_size = sizeof(CprmanPllChannelState), 248 .class_init = pll_channel_class_init, 249 .instance_init = pll_channel_init, 250 }; 251 252 253 /* clock mux */ 254 255 static bool clock_mux_is_enabled(CprmanClockMuxState *mux) 256 { 257 return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE); 258 } 259 260 static void clock_mux_update(CprmanClockMuxState *mux) 261 { 262 uint64_t freq; 263 uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC); 264 bool enabled = clock_mux_is_enabled(mux); 265 266 *mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled); 267 268 if (!enabled) { 269 clock_update(mux->out, 0); 270 return; 271 } 272 273 freq = clock_get_hz(mux->srcs[src]); 274 275 if (mux->int_bits == 0 && mux->frac_bits == 0) { 276 clock_update_hz(mux->out, freq); 277 return; 278 } 279 280 /* 281 * The divider has an integer and a fractional part. The size of each part 282 * varies with the muxes (int_bits and frac_bits). Both parts are 283 * concatenated, with the integer part always starting at bit 12. 284 * 285 * 31 12 11 0 286 * ------------------------------ 287 * CM_DIV | | int | frac | | 288 * ------------------------------ 289 * <-----> <------> 290 * int_bits frac_bits 291 */ 292 div = extract32(*mux->reg_div, 293 R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits, 294 mux->int_bits + mux->frac_bits); 295 296 if (!div) { 297 clock_update(mux->out, 0); 298 return; 299 } 300 301 freq = muldiv64(freq, 1 << mux->frac_bits, div); 302 303 clock_update_hz(mux->out, freq); 304 } 305 306 static void clock_mux_src_update(void *opaque) 307 { 308 CprmanClockMuxState **backref = opaque; 309 CprmanClockMuxState *s = *backref; 310 CprmanClockMuxSource src = backref - s->backref; 311 312 if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) { 313 return; 314 } 315 316 clock_mux_update(s); 317 } 318 319 static void clock_mux_reset(DeviceState *dev) 320 { 321 CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev); 322 const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id]; 323 324 *clock->reg_ctl = info->cm_ctl; 325 *clock->reg_div = info->cm_div; 326 } 327 328 static void clock_mux_init(Object *obj) 329 { 330 CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj); 331 size_t i; 332 333 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { 334 char *name = g_strdup_printf("srcs[%zu]", i); 335 s->backref[i] = s; 336 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name, 337 clock_mux_src_update, 338 &s->backref[i]); 339 g_free(name); 340 } 341 342 s->out = qdev_init_clock_out(DEVICE(s), "out"); 343 } 344 345 static const VMStateDescription clock_mux_vmstate = { 346 .name = TYPE_CPRMAN_CLOCK_MUX, 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .fields = (VMStateField[]) { 350 VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState, 351 CPRMAN_NUM_CLOCK_MUX_SRC), 352 VMSTATE_END_OF_LIST() 353 } 354 }; 355 356 static void clock_mux_class_init(ObjectClass *klass, void *data) 357 { 358 DeviceClass *dc = DEVICE_CLASS(klass); 359 360 dc->reset = clock_mux_reset; 361 dc->vmsd = &clock_mux_vmstate; 362 } 363 364 static const TypeInfo cprman_clock_mux_info = { 365 .name = TYPE_CPRMAN_CLOCK_MUX, 366 .parent = TYPE_DEVICE, 367 .instance_size = sizeof(CprmanClockMuxState), 368 .class_init = clock_mux_class_init, 369 .instance_init = clock_mux_init, 370 }; 371 372 373 /* DSI0HSCK mux */ 374 375 static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s) 376 { 377 bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD); 378 Clock *src = src_is_plld ? s->plld_in : s->plla_in; 379 380 clock_update(s->out, clock_get(src)); 381 } 382 383 static void dsi0hsck_mux_in_update(void *opaque) 384 { 385 dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque)); 386 } 387 388 static void dsi0hsck_mux_init(Object *obj) 389 { 390 CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj); 391 DeviceState *dev = DEVICE(obj); 392 393 s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s); 394 s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s); 395 s->out = qdev_init_clock_out(DEVICE(s), "out"); 396 } 397 398 static const VMStateDescription dsi0hsck_mux_vmstate = { 399 .name = TYPE_CPRMAN_DSI0HSCK_MUX, 400 .version_id = 1, 401 .minimum_version_id = 1, 402 .fields = (VMStateField[]) { 403 VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState), 404 VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState), 405 VMSTATE_END_OF_LIST() 406 } 407 }; 408 409 static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data) 410 { 411 DeviceClass *dc = DEVICE_CLASS(klass); 412 413 dc->vmsd = &dsi0hsck_mux_vmstate; 414 } 415 416 static const TypeInfo cprman_dsi0hsck_mux_info = { 417 .name = TYPE_CPRMAN_DSI0HSCK_MUX, 418 .parent = TYPE_DEVICE, 419 .instance_size = sizeof(CprmanDsi0HsckMuxState), 420 .class_init = dsi0hsck_mux_class_init, 421 .instance_init = dsi0hsck_mux_init, 422 }; 423 424 425 /* CPRMAN "top level" model */ 426 427 static uint32_t get_cm_lock(const BCM2835CprmanState *s) 428 { 429 static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = { 430 [CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT, 431 [CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT, 432 [CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT, 433 [CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT, 434 [CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT, 435 }; 436 437 uint32_t r = 0; 438 size_t i; 439 440 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 441 r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; 442 } 443 444 return r; 445 } 446 447 static uint64_t cprman_read(void *opaque, hwaddr offset, 448 unsigned size) 449 { 450 BCM2835CprmanState *s = CPRMAN(opaque); 451 uint64_t r = 0; 452 size_t idx = offset / sizeof(uint32_t); 453 454 switch (idx) { 455 case R_CM_LOCK: 456 r = get_cm_lock(s); 457 break; 458 459 default: 460 r = s->regs[idx]; 461 } 462 463 trace_bcm2835_cprman_read(offset, r); 464 return r; 465 } 466 467 static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s, 468 size_t idx) 469 { 470 size_t i; 471 472 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 473 if (PLL_INIT_INFO[i].cm_offset == idx) { 474 pll_update_all_channels(s, &s->plls[i]); 475 return; 476 } 477 } 478 } 479 480 static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx) 481 { 482 size_t i; 483 484 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 485 if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) { 486 pll_channel_update(&s->channels[i]); 487 return; 488 } 489 } 490 } 491 492 static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx) 493 { 494 size_t i; 495 496 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 497 if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) || 498 (CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) { 499 /* matches CM_CTL or CM_DIV mux register */ 500 clock_mux_update(&s->clock_muxes[i]); 501 return; 502 } 503 } 504 } 505 506 #define CASE_PLL_A2W_REGS(pll_) \ 507 case R_A2W_ ## pll_ ## _CTRL: \ 508 case R_A2W_ ## pll_ ## _ANA0: \ 509 case R_A2W_ ## pll_ ## _ANA1: \ 510 case R_A2W_ ## pll_ ## _ANA2: \ 511 case R_A2W_ ## pll_ ## _ANA3: \ 512 case R_A2W_ ## pll_ ## _FRAC 513 514 static void cprman_write(void *opaque, hwaddr offset, 515 uint64_t value, unsigned size) 516 { 517 BCM2835CprmanState *s = CPRMAN(opaque); 518 size_t idx = offset / sizeof(uint32_t); 519 520 if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) { 521 trace_bcm2835_cprman_write_invalid_magic(offset, value); 522 return; 523 } 524 525 value &= ~R_CPRMAN_PASSWORD_MASK; 526 527 trace_bcm2835_cprman_write(offset, value); 528 s->regs[idx] = value; 529 530 switch (idx) { 531 case R_CM_PLLA ... R_CM_PLLH: 532 case R_CM_PLLB: 533 /* 534 * A given CM_PLLx register is shared by both the PLL and the channels 535 * of this PLL. 536 */ 537 update_pll_and_channels_from_cm(s, idx); 538 break; 539 540 CASE_PLL_A2W_REGS(PLLA) : 541 pll_update(&s->plls[CPRMAN_PLLA]); 542 break; 543 544 CASE_PLL_A2W_REGS(PLLC) : 545 pll_update(&s->plls[CPRMAN_PLLC]); 546 break; 547 548 CASE_PLL_A2W_REGS(PLLD) : 549 pll_update(&s->plls[CPRMAN_PLLD]); 550 break; 551 552 CASE_PLL_A2W_REGS(PLLH) : 553 pll_update(&s->plls[CPRMAN_PLLH]); 554 break; 555 556 CASE_PLL_A2W_REGS(PLLB) : 557 pll_update(&s->plls[CPRMAN_PLLB]); 558 break; 559 560 case R_A2W_PLLA_DSI0: 561 case R_A2W_PLLA_CORE: 562 case R_A2W_PLLA_PER: 563 case R_A2W_PLLA_CCP2: 564 case R_A2W_PLLC_CORE2: 565 case R_A2W_PLLC_CORE1: 566 case R_A2W_PLLC_PER: 567 case R_A2W_PLLC_CORE0: 568 case R_A2W_PLLD_DSI0: 569 case R_A2W_PLLD_CORE: 570 case R_A2W_PLLD_PER: 571 case R_A2W_PLLD_DSI1: 572 case R_A2W_PLLH_AUX: 573 case R_A2W_PLLH_RCAL: 574 case R_A2W_PLLH_PIX: 575 case R_A2W_PLLB_ARM: 576 update_channel_from_a2w(s, idx); 577 break; 578 579 case R_CM_GNRICCTL ... R_CM_SMIDIV: 580 case R_CM_TCNTCNT ... R_CM_VECDIV: 581 case R_CM_PULSECTL ... R_CM_PULSEDIV: 582 case R_CM_SDCCTL ... R_CM_ARMCTL: 583 case R_CM_AVEOCTL ... R_CM_EMMCDIV: 584 case R_CM_EMMC2CTL ... R_CM_EMMC2DIV: 585 update_mux_from_cm(s, idx); 586 break; 587 588 case R_CM_DSI0HSCK: 589 dsi0hsck_mux_update(&s->dsi0hsck_mux); 590 break; 591 } 592 } 593 594 #undef CASE_PLL_A2W_REGS 595 596 static const MemoryRegionOps cprman_ops = { 597 .read = cprman_read, 598 .write = cprman_write, 599 .endianness = DEVICE_LITTLE_ENDIAN, 600 .valid = { 601 /* 602 * Although this hasn't been checked against real hardware, nor the 603 * information can be found in a datasheet, it seems reasonable because 604 * of the "PASSWORD" magic value found in every registers. 605 */ 606 .min_access_size = 4, 607 .max_access_size = 4, 608 .unaligned = false, 609 }, 610 .impl = { 611 .max_access_size = 4, 612 }, 613 }; 614 615 static void cprman_reset(DeviceState *dev) 616 { 617 BCM2835CprmanState *s = CPRMAN(dev); 618 size_t i; 619 620 memset(s->regs, 0, sizeof(s->regs)); 621 622 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 623 device_cold_reset(DEVICE(&s->plls[i])); 624 } 625 626 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 627 device_cold_reset(DEVICE(&s->channels[i])); 628 } 629 630 device_cold_reset(DEVICE(&s->dsi0hsck_mux)); 631 632 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 633 device_cold_reset(DEVICE(&s->clock_muxes[i])); 634 } 635 636 clock_update_hz(s->xosc, s->xosc_freq); 637 } 638 639 static void cprman_init(Object *obj) 640 { 641 BCM2835CprmanState *s = CPRMAN(obj); 642 size_t i; 643 644 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 645 object_initialize_child(obj, PLL_INIT_INFO[i].name, 646 &s->plls[i], TYPE_CPRMAN_PLL); 647 set_pll_init_info(s, &s->plls[i], i); 648 } 649 650 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 651 object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name, 652 &s->channels[i], 653 TYPE_CPRMAN_PLL_CHANNEL); 654 set_pll_channel_init_info(s, &s->channels[i], i); 655 } 656 657 object_initialize_child(obj, "dsi0hsck-mux", 658 &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX); 659 s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK]; 660 661 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 662 char *alias; 663 664 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name, 665 &s->clock_muxes[i], 666 TYPE_CPRMAN_CLOCK_MUX); 667 set_clock_mux_init_info(s, &s->clock_muxes[i], i); 668 669 /* Expose muxes output as CPRMAN outputs */ 670 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name); 671 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias); 672 g_free(alias); 673 } 674 675 s->xosc = clock_new(obj, "xosc"); 676 s->gnd = clock_new(obj, "gnd"); 677 678 clock_set(s->gnd, 0); 679 680 memory_region_init_io(&s->iomem, obj, &cprman_ops, 681 s, "bcm2835-cprman", 0x2000); 682 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 683 } 684 685 static void connect_mux_sources(BCM2835CprmanState *s, 686 CprmanClockMuxState *mux, 687 const CprmanPllChannel *clk_mapping) 688 { 689 size_t i; 690 Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out; 691 Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out; 692 693 /* For sources from 0 to 3. Source 4 to 9 are mux specific */ 694 Clock * const CLK_SRC_MAPPING[] = { 695 [CPRMAN_CLOCK_SRC_GND] = s->gnd, 696 [CPRMAN_CLOCK_SRC_XOSC] = s->xosc, 697 [CPRMAN_CLOCK_SRC_TD0] = td0, 698 [CPRMAN_CLOCK_SRC_TD1] = td1, 699 }; 700 701 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { 702 CprmanPllChannel mapping = clk_mapping[i]; 703 Clock *src; 704 705 if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) { 706 src = s->gnd; 707 } else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) { 708 src = s->dsi0hsck_mux.out; 709 } else if (i < CPRMAN_CLOCK_SRC_PLLA) { 710 src = CLK_SRC_MAPPING[i]; 711 } else { 712 src = s->channels[mapping].out; 713 } 714 715 clock_set_source(mux->srcs[i], src); 716 } 717 } 718 719 static void cprman_realize(DeviceState *dev, Error **errp) 720 { 721 BCM2835CprmanState *s = CPRMAN(dev); 722 size_t i; 723 724 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 725 CprmanPllState *pll = &s->plls[i]; 726 727 clock_set_source(pll->xosc_in, s->xosc); 728 729 if (!qdev_realize(DEVICE(pll), NULL, errp)) { 730 return; 731 } 732 } 733 734 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 735 CprmanPllChannelState *channel = &s->channels[i]; 736 CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent; 737 Clock *parent_clk = s->plls[parent].out; 738 739 clock_set_source(channel->pll_in, parent_clk); 740 741 if (!qdev_realize(DEVICE(channel), NULL, errp)) { 742 return; 743 } 744 } 745 746 clock_set_source(s->dsi0hsck_mux.plla_in, 747 s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out); 748 clock_set_source(s->dsi0hsck_mux.plld_in, 749 s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out); 750 751 if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) { 752 return; 753 } 754 755 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 756 CprmanClockMuxState *clock_mux = &s->clock_muxes[i]; 757 758 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping); 759 760 if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) { 761 return; 762 } 763 } 764 } 765 766 static const VMStateDescription cprman_vmstate = { 767 .name = TYPE_BCM2835_CPRMAN, 768 .version_id = 1, 769 .minimum_version_id = 1, 770 .fields = (VMStateField[]) { 771 VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS), 772 VMSTATE_END_OF_LIST() 773 } 774 }; 775 776 static Property cprman_properties[] = { 777 DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000), 778 DEFINE_PROP_END_OF_LIST() 779 }; 780 781 static void cprman_class_init(ObjectClass *klass, void *data) 782 { 783 DeviceClass *dc = DEVICE_CLASS(klass); 784 785 dc->realize = cprman_realize; 786 dc->reset = cprman_reset; 787 dc->vmsd = &cprman_vmstate; 788 device_class_set_props(dc, cprman_properties); 789 } 790 791 static const TypeInfo cprman_info = { 792 .name = TYPE_BCM2835_CPRMAN, 793 .parent = TYPE_SYS_BUS_DEVICE, 794 .instance_size = sizeof(BCM2835CprmanState), 795 .class_init = cprman_class_init, 796 .instance_init = cprman_init, 797 }; 798 799 static void cprman_register_types(void) 800 { 801 type_register_static(&cprman_info); 802 type_register_static(&cprman_pll_info); 803 type_register_static(&cprman_pll_channel_info); 804 type_register_static(&cprman_clock_mux_info); 805 type_register_static(&cprman_dsi0hsck_mux_info); 806 } 807 808 type_init(cprman_register_types); 809