1 /* 2 * ASPEED SDRAM Memory Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qemu/error-report.h" 14 #include "hw/misc/aspeed_sdmc.h" 15 #include "hw/qdev-properties.h" 16 #include "migration/vmstate.h" 17 #include "qapi/error.h" 18 #include "trace.h" 19 #include "qemu/units.h" 20 #include "qemu/cutils.h" 21 #include "qapi/visitor.h" 22 23 /* Protection Key Register */ 24 #define R_PROT (0x00 / 4) 25 #define PROT_UNLOCKED 0x01 26 #define PROT_HARDLOCKED 0x10 /* AST2600 */ 27 #define PROT_SOFTLOCKED 0x00 28 29 #define PROT_KEY_UNLOCK 0xFC600309 30 #define PROT_2700_KEY_UNLOCK 0x1688A8A8 31 #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */ 32 33 /* Configuration Register */ 34 #define R_CONF (0x04 / 4) 35 36 /* Interrupt control/status */ 37 #define R_ISR (0x50 / 4) 38 39 /* Control/Status Register #1 (ast2500) */ 40 #define R_STATUS1 (0x60 / 4) 41 #define PHY_BUSY_STATE BIT(0) 42 #define PHY_PLL_LOCK_STATUS BIT(4) 43 44 /* Reserved */ 45 #define R_MCR6C (0x6c / 4) 46 47 #define R_ECC_TEST_CTRL (0x70 / 4) 48 #define ECC_TEST_FINISHED BIT(12) 49 #define ECC_TEST_FAIL BIT(13) 50 51 #define R_TEST_START_LEN (0x74 / 4) 52 #define R_TEST_FAIL_DQ (0x78 / 4) 53 #define R_TEST_INIT_VAL (0x7c / 4) 54 #define R_DRAM_SW (0x88 / 4) 55 #define R_DRAM_TIME (0x8c / 4) 56 #define R_ECC_ERR_INJECT (0xb4 / 4) 57 58 /* AST2700 Register */ 59 #define R_2700_PROT (0x00 / 4) 60 #define R_INT_STATUS (0x04 / 4) 61 #define R_INT_CLEAR (0x08 / 4) 62 #define R_INT_MASK (0x0c / 4) 63 #define R_MAIN_CONF (0x10 / 4) 64 #define R_MAIN_CONTROL (0x14 / 4) 65 #define R_MAIN_STATUS (0x18 / 4) 66 #define R_ERR_STATUS (0x1c / 4) 67 #define R_ECC_FAIL_STATUS (0x78 / 4) 68 #define R_ECC_FAIL_ADDR (0x7c / 4) 69 #define R_ECC_TESTING_CONTROL (0x80 / 4) 70 #define R_PROT_REGION_LOCK_STATUS (0x94 / 4) 71 #define R_TEST_FAIL_ADDR (0xd4 / 4) 72 #define R_TEST_FAIL_D0 (0xd8 / 4) 73 #define R_TEST_FAIL_D1 (0xdc / 4) 74 #define R_TEST_FAIL_D2 (0xe0 / 4) 75 #define R_TEST_FAIL_D3 (0xe4 / 4) 76 #define R_DBG_STATUS (0xf4 / 4) 77 #define R_PHY_INTERFACE_STATUS (0xf8 / 4) 78 #define R_GRAPHIC_MEM_BASE_ADDR (0x10c / 4) 79 #define R_PORT0_INTERFACE_MONITOR0 (0x240 / 4) 80 #define R_PORT0_INTERFACE_MONITOR1 (0x244 / 4) 81 #define R_PORT0_INTERFACE_MONITOR2 (0x248 / 4) 82 #define R_PORT1_INTERFACE_MONITOR0 (0x2c0 / 4) 83 #define R_PORT1_INTERFACE_MONITOR1 (0x2c4 / 4) 84 #define R_PORT1_INTERFACE_MONITOR2 (0x2c8 / 4) 85 #define R_PORT2_INTERFACE_MONITOR0 (0x340 / 4) 86 #define R_PORT2_INTERFACE_MONITOR1 (0x344 / 4) 87 #define R_PORT2_INTERFACE_MONITOR2 (0x348 / 4) 88 #define R_PORT3_INTERFACE_MONITOR0 (0x3c0 / 4) 89 #define R_PORT3_INTERFACE_MONITOR1 (0x3c4 / 4) 90 #define R_PORT3_INTERFACE_MONITOR2 (0x3c8 / 4) 91 #define R_PORT4_INTERFACE_MONITOR0 (0x440 / 4) 92 #define R_PORT4_INTERFACE_MONITOR1 (0x444 / 4) 93 #define R_PORT4_INTERFACE_MONITOR2 (0x448 / 4) 94 #define R_PORT5_INTERFACE_MONITOR0 (0x4c0 / 4) 95 #define R_PORT5_INTERFACE_MONITOR1 (0x4c4 / 4) 96 #define R_PORT5_INTERFACE_MONITOR2 (0x4c8 / 4) 97 98 /* 99 * Configuration register Ox4 (for Aspeed AST2400 SOC) 100 * 101 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is 102 * what we care about right now as it is checked by U-Boot to 103 * determine the RAM size. 104 */ 105 106 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ 107 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) 108 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) 109 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) 110 #define ASPEED_SDMC_ECC_ENABLE (1 << 7) 111 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ 112 #define ASPEED_SDMC_DRAM_BANK (1 << 5) 113 #define ASPEED_SDMC_DRAM_BURST (1 << 4) 114 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ 115 #define ASPEED_SDMC_VGA_8MB 0x0 116 #define ASPEED_SDMC_VGA_16MB 0x1 117 #define ASPEED_SDMC_VGA_32MB 0x2 118 #define ASPEED_SDMC_VGA_64MB 0x3 119 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) 120 121 #define ASPEED_SDMC_READONLY_MASK \ 122 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 123 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 124 /* 125 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) 126 * 127 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION 128 * should be set to 1 for the AST2500 SOC. 129 */ 130 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ 131 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) 132 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ 133 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ 134 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) 135 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) 136 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) 137 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ 138 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ 139 140 #define ASPEED_SDMC_AST2500_READONLY_MASK \ 141 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ 142 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 143 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 144 145 /* 146 * Main Configuration register Ox10 (for Aspeed AST2700 SOC and higher) 147 * 148 */ 149 #define ASPEED_SDMC_AST2700_RESERVED 0xFFFF2082 /* 31:16, 13, 7, 1 */ 150 #define ASPEED_SDMC_AST2700_DATA_SCRAMBLE (1 << 8) 151 #define ASPEED_SDMC_AST2700_ECC_ENABLE (1 << 6) 152 #define ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE (1 << 5) 153 #define ASPEED_SDMC_AST2700_DRAM_SIZE(x) ((x & 0x7) << 2) 154 155 #define ASPEED_SDMC_AST2700_READONLY_MASK \ 156 (ASPEED_SDMC_AST2700_RESERVED) 157 158 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) 159 { 160 AspeedSDMCState *s = ASPEED_SDMC(opaque); 161 162 addr >>= 2; 163 164 if (addr >= ARRAY_SIZE(s->regs)) { 165 qemu_log_mask(LOG_GUEST_ERROR, 166 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 167 __func__, addr * 4); 168 return 0; 169 } 170 171 trace_aspeed_sdmc_read(addr, s->regs[addr]); 172 return s->regs[addr]; 173 } 174 175 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 176 unsigned int size) 177 { 178 AspeedSDMCState *s = ASPEED_SDMC(opaque); 179 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 180 181 addr >>= 2; 182 183 if (addr >= ARRAY_SIZE(s->regs)) { 184 qemu_log_mask(LOG_GUEST_ERROR, 185 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 186 __func__, addr); 187 return; 188 } 189 190 trace_aspeed_sdmc_write(addr, data); 191 asc->write(s, addr, data); 192 } 193 194 static const MemoryRegionOps aspeed_sdmc_ops = { 195 .read = aspeed_sdmc_read, 196 .write = aspeed_sdmc_write, 197 .endianness = DEVICE_LITTLE_ENDIAN, 198 .valid.min_access_size = 4, 199 .valid.max_access_size = 4, 200 }; 201 202 static void aspeed_sdmc_reset(DeviceState *dev) 203 { 204 AspeedSDMCState *s = ASPEED_SDMC(dev); 205 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 206 207 memset(s->regs, 0, sizeof(s->regs)); 208 209 /* Set ram size bit and defaults values */ 210 s->regs[R_CONF] = asc->compute_conf(s, 0); 211 212 /* 213 * PHY status: 214 * - set phy status ok (set bit 1) 215 * - initial PVT calibration ok (clear bit 3) 216 * - runtime calibration ok (clear bit 5) 217 */ 218 s->regs[0x100] = BIT(1); 219 220 /* PHY eye window: set all as passing */ 221 s->regs[0x100 | (0x68 / 4)] = 0xff; 222 s->regs[0x100 | (0x7c / 4)] = 0xff; 223 s->regs[0x100 | (0x50 / 4)] = 0xfffffff; 224 } 225 226 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, 227 void *opaque, Error **errp) 228 { 229 AspeedSDMCState *s = ASPEED_SDMC(obj); 230 int64_t value = s->ram_size; 231 232 visit_type_int(v, name, &value, errp); 233 } 234 235 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, 236 void *opaque, Error **errp) 237 { 238 int i; 239 char *sz; 240 int64_t value; 241 AspeedSDMCState *s = ASPEED_SDMC(obj); 242 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 243 244 if (!visit_type_int(v, name, &value, errp)) { 245 return; 246 } 247 248 for (i = 0; asc->valid_ram_sizes[i]; i++) { 249 if (value == asc->valid_ram_sizes[i]) { 250 s->ram_size = value; 251 return; 252 } 253 } 254 255 sz = size_to_str(value); 256 error_setg(errp, "Invalid RAM size %s", sz); 257 g_free(sz); 258 } 259 260 static void aspeed_sdmc_initfn(Object *obj) 261 { 262 object_property_add(obj, "ram-size", "int", 263 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, 264 NULL, NULL); 265 } 266 267 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 268 { 269 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 270 AspeedSDMCState *s = ASPEED_SDMC(dev); 271 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 272 273 assert(asc->max_ram_size < 4 * GiB || asc->is_bus64bit); 274 s->max_ram_size = asc->max_ram_size; 275 276 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, 277 TYPE_ASPEED_SDMC, 0x1000); 278 sysbus_init_mmio(sbd, &s->iomem); 279 } 280 281 static const VMStateDescription vmstate_aspeed_sdmc = { 282 .name = "aspeed.sdmc", 283 .version_id = 2, 284 .minimum_version_id = 2, 285 .fields = (const VMStateField[]) { 286 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), 287 VMSTATE_END_OF_LIST() 288 } 289 }; 290 291 static Property aspeed_sdmc_properties[] = { 292 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), 293 DEFINE_PROP_BOOL("unlocked", AspeedSDMCState, unlocked, false), 294 DEFINE_PROP_END_OF_LIST(), 295 }; 296 297 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) 298 { 299 DeviceClass *dc = DEVICE_CLASS(klass); 300 dc->realize = aspeed_sdmc_realize; 301 dc->reset = aspeed_sdmc_reset; 302 dc->desc = "ASPEED SDRAM Memory Controller"; 303 dc->vmsd = &vmstate_aspeed_sdmc; 304 device_class_set_props(dc, aspeed_sdmc_properties); 305 } 306 307 static const TypeInfo aspeed_sdmc_info = { 308 .name = TYPE_ASPEED_SDMC, 309 .parent = TYPE_SYS_BUS_DEVICE, 310 .instance_size = sizeof(AspeedSDMCState), 311 .instance_init = aspeed_sdmc_initfn, 312 .class_init = aspeed_sdmc_class_init, 313 .class_size = sizeof(AspeedSDMCClass), 314 .abstract = true, 315 }; 316 317 static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s) 318 { 319 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 320 int i; 321 322 /* 323 * The bitfield value encoding the RAM size is the index of the 324 * possible RAM size array 325 */ 326 for (i = 0; asc->valid_ram_sizes[i]; i++) { 327 if (s->ram_size == asc->valid_ram_sizes[i]) { 328 return i; 329 } 330 } 331 332 /* 333 * Invalid RAM sizes should have been excluded when setting the 334 * SoC RAM size. 335 */ 336 g_assert_not_reached(); 337 } 338 339 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 340 { 341 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | 342 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 343 344 /* Make sure readonly bits are kept */ 345 data &= ~ASPEED_SDMC_READONLY_MASK; 346 347 return data | fixed_conf; 348 } 349 350 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, 351 uint32_t data) 352 { 353 if (reg == R_PROT) { 354 s->regs[reg] = 355 (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 356 return; 357 } 358 359 if (!s->regs[R_PROT]) { 360 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 361 return; 362 } 363 364 switch (reg) { 365 case R_CONF: 366 data = aspeed_2400_sdmc_compute_conf(s, data); 367 break; 368 default: 369 break; 370 } 371 372 s->regs[reg] = data; 373 } 374 375 static const uint64_t 376 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; 377 378 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) 379 { 380 DeviceClass *dc = DEVICE_CLASS(klass); 381 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 382 383 dc->desc = "ASPEED 2400 SDRAM Memory Controller"; 384 asc->max_ram_size = 512 * MiB; 385 asc->compute_conf = aspeed_2400_sdmc_compute_conf; 386 asc->write = aspeed_2400_sdmc_write; 387 asc->valid_ram_sizes = aspeed_2400_ram_sizes; 388 } 389 390 static const TypeInfo aspeed_2400_sdmc_info = { 391 .name = TYPE_ASPEED_2400_SDMC, 392 .parent = TYPE_ASPEED_SDMC, 393 .class_init = aspeed_2400_sdmc_class_init, 394 }; 395 396 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 397 { 398 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | 399 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 400 ASPEED_SDMC_CACHE_INITIAL_DONE | 401 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 402 403 /* Make sure readonly bits are kept */ 404 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 405 406 return data | fixed_conf; 407 } 408 409 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, 410 uint32_t data) 411 { 412 if (reg == R_PROT) { 413 s->regs[reg] = 414 (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 415 return; 416 } 417 418 if (!s->regs[R_PROT]) { 419 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 420 return; 421 } 422 423 switch (reg) { 424 case R_CONF: 425 data = aspeed_2500_sdmc_compute_conf(s, data); 426 break; 427 case R_STATUS1: 428 /* Will never return 'busy' */ 429 data &= ~PHY_BUSY_STATE; 430 break; 431 case R_ECC_TEST_CTRL: 432 /* Always done, always happy */ 433 data |= ECC_TEST_FINISHED; 434 data &= ~ECC_TEST_FAIL; 435 break; 436 default: 437 break; 438 } 439 440 s->regs[reg] = data; 441 } 442 443 static const uint64_t 444 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; 445 446 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) 447 { 448 DeviceClass *dc = DEVICE_CLASS(klass); 449 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 450 451 dc->desc = "ASPEED 2500 SDRAM Memory Controller"; 452 asc->max_ram_size = 1 * GiB; 453 asc->compute_conf = aspeed_2500_sdmc_compute_conf; 454 asc->write = aspeed_2500_sdmc_write; 455 asc->valid_ram_sizes = aspeed_2500_ram_sizes; 456 } 457 458 static const TypeInfo aspeed_2500_sdmc_info = { 459 .name = TYPE_ASPEED_2500_SDMC, 460 .parent = TYPE_ASPEED_SDMC, 461 .class_init = aspeed_2500_sdmc_class_init, 462 }; 463 464 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 465 { 466 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | 467 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 468 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 469 470 /* Make sure readonly bits are kept (use ast2500 mask) */ 471 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 472 473 return data | fixed_conf; 474 } 475 476 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, 477 uint32_t data) 478 { 479 /* Unprotected registers */ 480 switch (reg) { 481 case R_ISR: 482 case R_MCR6C: 483 case R_TEST_START_LEN: 484 case R_TEST_FAIL_DQ: 485 case R_TEST_INIT_VAL: 486 case R_DRAM_SW: 487 case R_DRAM_TIME: 488 case R_ECC_ERR_INJECT: 489 s->regs[reg] = data; 490 return; 491 } 492 493 if (s->regs[R_PROT] == PROT_HARDLOCKED) { 494 qemu_log_mask(LOG_GUEST_ERROR, 495 "%s: SDMC is locked until system reset!\n", 496 __func__); 497 return; 498 } 499 500 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) { 501 qemu_log_mask(LOG_GUEST_ERROR, 502 "%s: SDMC is locked! (write to MCR%02x blocked)\n", 503 __func__, reg * 4); 504 return; 505 } 506 507 switch (reg) { 508 case R_PROT: 509 if (data == PROT_KEY_UNLOCK) { 510 data = PROT_UNLOCKED; 511 } else if (data == PROT_KEY_HARDLOCK) { 512 data = PROT_HARDLOCKED; 513 } else { 514 data = PROT_SOFTLOCKED; 515 } 516 break; 517 case R_CONF: 518 data = aspeed_2600_sdmc_compute_conf(s, data); 519 break; 520 case R_STATUS1: 521 /* Will never return 'busy'. 'lock status' is always set */ 522 data &= ~PHY_BUSY_STATE; 523 data |= PHY_PLL_LOCK_STATUS; 524 break; 525 case R_ECC_TEST_CTRL: 526 /* Always done, always happy */ 527 data |= ECC_TEST_FINISHED; 528 data &= ~ECC_TEST_FAIL; 529 break; 530 default: 531 break; 532 } 533 534 s->regs[reg] = data; 535 } 536 537 static const uint64_t 538 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; 539 540 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) 541 { 542 DeviceClass *dc = DEVICE_CLASS(klass); 543 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 544 545 dc->desc = "ASPEED 2600 SDRAM Memory Controller"; 546 asc->max_ram_size = 2 * GiB; 547 asc->compute_conf = aspeed_2600_sdmc_compute_conf; 548 asc->write = aspeed_2600_sdmc_write; 549 asc->valid_ram_sizes = aspeed_2600_ram_sizes; 550 } 551 552 static const TypeInfo aspeed_2600_sdmc_info = { 553 .name = TYPE_ASPEED_2600_SDMC, 554 .parent = TYPE_ASPEED_SDMC, 555 .class_init = aspeed_2600_sdmc_class_init, 556 }; 557 558 static void aspeed_2700_sdmc_reset(DeviceState *dev) 559 { 560 AspeedSDMCState *s = ASPEED_SDMC(dev); 561 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 562 563 memset(s->regs, 0, sizeof(s->regs)); 564 565 /* Set ram size bit and defaults values */ 566 s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); 567 568 if (s->unlocked) { 569 s->regs[R_2700_PROT] = PROT_UNLOCKED; 570 } 571 } 572 573 static uint32_t aspeed_2700_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 574 { 575 uint32_t fixed_conf = ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE | 576 ASPEED_SDMC_AST2700_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 577 578 /* Make sure readonly bits are kept */ 579 data &= ~ASPEED_SDMC_AST2700_READONLY_MASK; 580 581 return data | fixed_conf; 582 } 583 584 static void aspeed_2700_sdmc_write(AspeedSDMCState *s, uint32_t reg, 585 uint32_t data) 586 { 587 /* Unprotected registers */ 588 switch (reg) { 589 case R_INT_STATUS: 590 case R_INT_CLEAR: 591 case R_INT_MASK: 592 case R_MAIN_STATUS: 593 case R_ERR_STATUS: 594 case R_ECC_FAIL_STATUS: 595 case R_ECC_FAIL_ADDR: 596 case R_PROT_REGION_LOCK_STATUS: 597 case R_TEST_FAIL_ADDR: 598 case R_TEST_FAIL_D0: 599 case R_TEST_FAIL_D1: 600 case R_TEST_FAIL_D2: 601 case R_TEST_FAIL_D3: 602 case R_DBG_STATUS: 603 case R_PHY_INTERFACE_STATUS: 604 case R_GRAPHIC_MEM_BASE_ADDR: 605 case R_PORT0_INTERFACE_MONITOR0: 606 case R_PORT0_INTERFACE_MONITOR1: 607 case R_PORT0_INTERFACE_MONITOR2: 608 case R_PORT1_INTERFACE_MONITOR0: 609 case R_PORT1_INTERFACE_MONITOR1: 610 case R_PORT1_INTERFACE_MONITOR2: 611 case R_PORT2_INTERFACE_MONITOR0: 612 case R_PORT2_INTERFACE_MONITOR1: 613 case R_PORT2_INTERFACE_MONITOR2: 614 case R_PORT3_INTERFACE_MONITOR0: 615 case R_PORT3_INTERFACE_MONITOR1: 616 case R_PORT3_INTERFACE_MONITOR2: 617 case R_PORT4_INTERFACE_MONITOR0: 618 case R_PORT4_INTERFACE_MONITOR1: 619 case R_PORT4_INTERFACE_MONITOR2: 620 case R_PORT5_INTERFACE_MONITOR0: 621 case R_PORT5_INTERFACE_MONITOR1: 622 case R_PORT5_INTERFACE_MONITOR2: 623 s->regs[reg] = data; 624 return; 625 } 626 627 if (s->regs[R_2700_PROT] == PROT_HARDLOCKED) { 628 qemu_log_mask(LOG_GUEST_ERROR, 629 "%s: SDMC is locked until system reset!\n", 630 __func__); 631 return; 632 } 633 634 if (reg != R_2700_PROT && s->regs[R_2700_PROT] == PROT_SOFTLOCKED) { 635 qemu_log_mask(LOG_GUEST_ERROR, 636 "%s: SDMC is locked! (write to MCR%02x blocked)\n", 637 __func__, reg * 4); 638 return; 639 } 640 641 switch (reg) { 642 case R_2700_PROT: 643 if (data == PROT_2700_KEY_UNLOCK) { 644 data = PROT_UNLOCKED; 645 } else if (data == PROT_KEY_HARDLOCK) { 646 data = PROT_HARDLOCKED; 647 } else { 648 data = PROT_SOFTLOCKED; 649 } 650 break; 651 case R_MAIN_CONF: 652 data = aspeed_2700_sdmc_compute_conf(s, data); 653 break; 654 case R_MAIN_STATUS: 655 /* Will never return 'busy'. */ 656 data &= ~PHY_BUSY_STATE; 657 break; 658 default: 659 break; 660 } 661 662 s->regs[reg] = data; 663 } 664 665 static const uint64_t 666 aspeed_2700_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 667 2048 * MiB, 4096 * MiB, 8192 * MiB, 0}; 668 669 static void aspeed_2700_sdmc_class_init(ObjectClass *klass, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(klass); 672 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 673 674 dc->desc = "ASPEED 2700 SDRAM Memory Controller"; 675 dc->reset = aspeed_2700_sdmc_reset; 676 677 asc->is_bus64bit = true; 678 asc->max_ram_size = 8 * GiB; 679 asc->compute_conf = aspeed_2700_sdmc_compute_conf; 680 asc->write = aspeed_2700_sdmc_write; 681 asc->valid_ram_sizes = aspeed_2700_ram_sizes; 682 } 683 684 static const TypeInfo aspeed_2700_sdmc_info = { 685 .name = TYPE_ASPEED_2700_SDMC, 686 .parent = TYPE_ASPEED_SDMC, 687 .class_init = aspeed_2700_sdmc_class_init, 688 }; 689 690 static void aspeed_sdmc_register_types(void) 691 { 692 type_register_static(&aspeed_sdmc_info); 693 type_register_static(&aspeed_2400_sdmc_info); 694 type_register_static(&aspeed_2500_sdmc_info); 695 type_register_static(&aspeed_2600_sdmc_info); 696 type_register_static(&aspeed_2700_sdmc_info); 697 } 698 699 type_init(aspeed_sdmc_register_types); 700