1 /* 2 * ASPEED SDRAM Memory Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qemu/error-report.h" 14 #include "hw/misc/aspeed_sdmc.h" 15 #include "hw/misc/aspeed_scu.h" 16 #include "hw/qdev-properties.h" 17 #include "migration/vmstate.h" 18 #include "qapi/error.h" 19 #include "trace.h" 20 #include "qemu/units.h" 21 #include "qemu/cutils.h" 22 #include "qapi/visitor.h" 23 24 /* Protection Key Register */ 25 #define R_PROT (0x00 / 4) 26 #define PROT_UNLOCKED 0x01 27 #define PROT_HARDLOCKED 0x10 /* AST2600 */ 28 #define PROT_SOFTLOCKED 0x00 29 30 #define PROT_KEY_UNLOCK 0xFC600309 31 #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */ 32 33 /* Configuration Register */ 34 #define R_CONF (0x04 / 4) 35 36 /* Interrupt control/status */ 37 #define R_ISR (0x50 / 4) 38 39 /* Control/Status Register #1 (ast2500) */ 40 #define R_STATUS1 (0x60 / 4) 41 #define PHY_BUSY_STATE BIT(0) 42 #define PHY_PLL_LOCK_STATUS BIT(4) 43 44 /* Reserved */ 45 #define R_MCR6C (0x6c / 4) 46 47 #define R_ECC_TEST_CTRL (0x70 / 4) 48 #define ECC_TEST_FINISHED BIT(12) 49 #define ECC_TEST_FAIL BIT(13) 50 51 #define R_TEST_START_LEN (0x74 / 4) 52 #define R_TEST_FAIL_DQ (0x78 / 4) 53 #define R_TEST_INIT_VAL (0x7c / 4) 54 #define R_DRAM_SW (0x88 / 4) 55 #define R_DRAM_TIME (0x8c / 4) 56 #define R_ECC_ERR_INJECT (0xb4 / 4) 57 58 /* 59 * Configuration register Ox4 (for Aspeed AST2400 SOC) 60 * 61 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is 62 * what we care about right now as it is checked by U-Boot to 63 * determine the RAM size. 64 */ 65 66 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ 67 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) 68 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) 69 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) 70 #define ASPEED_SDMC_ECC_ENABLE (1 << 7) 71 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ 72 #define ASPEED_SDMC_DRAM_BANK (1 << 5) 73 #define ASPEED_SDMC_DRAM_BURST (1 << 4) 74 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ 75 #define ASPEED_SDMC_VGA_8MB 0x0 76 #define ASPEED_SDMC_VGA_16MB 0x1 77 #define ASPEED_SDMC_VGA_32MB 0x2 78 #define ASPEED_SDMC_VGA_64MB 0x3 79 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) 80 #define ASPEED_SDMC_DRAM_64MB 0x0 81 #define ASPEED_SDMC_DRAM_128MB 0x1 82 #define ASPEED_SDMC_DRAM_256MB 0x2 83 #define ASPEED_SDMC_DRAM_512MB 0x3 84 85 #define ASPEED_SDMC_READONLY_MASK \ 86 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 87 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 88 /* 89 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) 90 * 91 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION 92 * should be set to 1 for the AST2500 SOC. 93 */ 94 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ 95 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) 96 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ 97 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ 98 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) 99 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) 100 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) 101 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ 102 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ 103 104 /* DRAM size definitions differs */ 105 #define ASPEED_SDMC_AST2500_128MB 0x0 106 #define ASPEED_SDMC_AST2500_256MB 0x1 107 #define ASPEED_SDMC_AST2500_512MB 0x2 108 #define ASPEED_SDMC_AST2500_1024MB 0x3 109 110 #define ASPEED_SDMC_AST2600_256MB 0x0 111 #define ASPEED_SDMC_AST2600_512MB 0x1 112 #define ASPEED_SDMC_AST2600_1024MB 0x2 113 #define ASPEED_SDMC_AST2600_2048MB 0x3 114 115 #define ASPEED_SDMC_AST2500_READONLY_MASK \ 116 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ 117 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 118 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 119 120 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) 121 { 122 AspeedSDMCState *s = ASPEED_SDMC(opaque); 123 124 addr >>= 2; 125 126 if (addr >= ARRAY_SIZE(s->regs)) { 127 qemu_log_mask(LOG_GUEST_ERROR, 128 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 129 __func__, addr * 4); 130 return 0; 131 } 132 133 trace_aspeed_sdmc_read(addr, s->regs[addr]); 134 return s->regs[addr]; 135 } 136 137 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 138 unsigned int size) 139 { 140 AspeedSDMCState *s = ASPEED_SDMC(opaque); 141 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 142 143 addr >>= 2; 144 145 if (addr >= ARRAY_SIZE(s->regs)) { 146 qemu_log_mask(LOG_GUEST_ERROR, 147 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 148 __func__, addr); 149 return; 150 } 151 152 trace_aspeed_sdmc_write(addr, data); 153 asc->write(s, addr, data); 154 } 155 156 static const MemoryRegionOps aspeed_sdmc_ops = { 157 .read = aspeed_sdmc_read, 158 .write = aspeed_sdmc_write, 159 .endianness = DEVICE_LITTLE_ENDIAN, 160 .valid.min_access_size = 4, 161 .valid.max_access_size = 4, 162 }; 163 164 static void aspeed_sdmc_reset(DeviceState *dev) 165 { 166 AspeedSDMCState *s = ASPEED_SDMC(dev); 167 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 168 169 memset(s->regs, 0, sizeof(s->regs)); 170 171 /* Set ram size bit and defaults values */ 172 s->regs[R_CONF] = asc->compute_conf(s, 0); 173 174 /* 175 * PHY status: 176 * - set phy status ok (set bit 1) 177 * - initial PVT calibration ok (clear bit 3) 178 * - runtime calibration ok (clear bit 5) 179 */ 180 s->regs[0x100] = BIT(1); 181 182 /* PHY eye window: set all as passing */ 183 s->regs[0x100 | (0x68 / 4)] = 0xff; 184 s->regs[0x100 | (0x7c / 4)] = 0xff; 185 s->regs[0x100 | (0x50 / 4)] = 0xfffffff; 186 } 187 188 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, 189 void *opaque, Error **errp) 190 { 191 AspeedSDMCState *s = ASPEED_SDMC(obj); 192 int64_t value = s->ram_size; 193 194 visit_type_int(v, name, &value, errp); 195 } 196 197 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, 198 void *opaque, Error **errp) 199 { 200 int i; 201 char *sz; 202 int64_t value; 203 AspeedSDMCState *s = ASPEED_SDMC(obj); 204 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 205 206 if (!visit_type_int(v, name, &value, errp)) { 207 return; 208 } 209 210 for (i = 0; asc->valid_ram_sizes[i]; i++) { 211 if (value == asc->valid_ram_sizes[i]) { 212 s->ram_size = value; 213 return; 214 } 215 } 216 217 sz = size_to_str(value); 218 error_setg(errp, "Invalid RAM size %s", sz); 219 g_free(sz); 220 } 221 222 static void aspeed_sdmc_initfn(Object *obj) 223 { 224 object_property_add(obj, "ram-size", "int", 225 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, 226 NULL, NULL); 227 } 228 229 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 230 { 231 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 232 AspeedSDMCState *s = ASPEED_SDMC(dev); 233 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 234 235 assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */ 236 s->max_ram_size = asc->max_ram_size; 237 238 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, 239 TYPE_ASPEED_SDMC, 0x1000); 240 sysbus_init_mmio(sbd, &s->iomem); 241 } 242 243 static const VMStateDescription vmstate_aspeed_sdmc = { 244 .name = "aspeed.sdmc", 245 .version_id = 1, 246 .minimum_version_id = 1, 247 .fields = (VMStateField[]) { 248 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), 249 VMSTATE_END_OF_LIST() 250 } 251 }; 252 253 static Property aspeed_sdmc_properties[] = { 254 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), 255 DEFINE_PROP_END_OF_LIST(), 256 }; 257 258 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) 259 { 260 DeviceClass *dc = DEVICE_CLASS(klass); 261 dc->realize = aspeed_sdmc_realize; 262 dc->reset = aspeed_sdmc_reset; 263 dc->desc = "ASPEED SDRAM Memory Controller"; 264 dc->vmsd = &vmstate_aspeed_sdmc; 265 device_class_set_props(dc, aspeed_sdmc_properties); 266 } 267 268 static const TypeInfo aspeed_sdmc_info = { 269 .name = TYPE_ASPEED_SDMC, 270 .parent = TYPE_SYS_BUS_DEVICE, 271 .instance_size = sizeof(AspeedSDMCState), 272 .instance_init = aspeed_sdmc_initfn, 273 .class_init = aspeed_sdmc_class_init, 274 .class_size = sizeof(AspeedSDMCClass), 275 .abstract = true, 276 }; 277 278 static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s) 279 { 280 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 281 int i; 282 283 /* 284 * The bitfield value encoding the RAM size is the index of the 285 * possible RAM size array 286 */ 287 for (i = 0; asc->valid_ram_sizes[i]; i++) { 288 if (s->ram_size == asc->valid_ram_sizes[i]) { 289 return i; 290 } 291 } 292 293 /* 294 * Invalid RAM sizes should have been excluded when setting the 295 * SoC RAM size. 296 */ 297 g_assert_not_reached(); 298 } 299 300 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 301 { 302 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | 303 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 304 305 /* Make sure readonly bits are kept */ 306 data &= ~ASPEED_SDMC_READONLY_MASK; 307 308 return data | fixed_conf; 309 } 310 311 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, 312 uint32_t data) 313 { 314 if (reg == R_PROT) { 315 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 316 return; 317 } 318 319 if (!s->regs[R_PROT]) { 320 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 321 return; 322 } 323 324 switch (reg) { 325 case R_CONF: 326 data = aspeed_2400_sdmc_compute_conf(s, data); 327 break; 328 default: 329 break; 330 } 331 332 s->regs[reg] = data; 333 } 334 335 static const uint64_t 336 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; 337 338 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) 339 { 340 DeviceClass *dc = DEVICE_CLASS(klass); 341 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 342 343 dc->desc = "ASPEED 2400 SDRAM Memory Controller"; 344 asc->max_ram_size = 512 * MiB; 345 asc->compute_conf = aspeed_2400_sdmc_compute_conf; 346 asc->write = aspeed_2400_sdmc_write; 347 asc->valid_ram_sizes = aspeed_2400_ram_sizes; 348 } 349 350 static const TypeInfo aspeed_2400_sdmc_info = { 351 .name = TYPE_ASPEED_2400_SDMC, 352 .parent = TYPE_ASPEED_SDMC, 353 .class_init = aspeed_2400_sdmc_class_init, 354 }; 355 356 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 357 { 358 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | 359 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 360 ASPEED_SDMC_CACHE_INITIAL_DONE | 361 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 362 363 /* Make sure readonly bits are kept */ 364 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 365 366 return data | fixed_conf; 367 } 368 369 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, 370 uint32_t data) 371 { 372 if (reg == R_PROT) { 373 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 374 return; 375 } 376 377 if (!s->regs[R_PROT]) { 378 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 379 return; 380 } 381 382 switch (reg) { 383 case R_CONF: 384 data = aspeed_2500_sdmc_compute_conf(s, data); 385 break; 386 case R_STATUS1: 387 /* Will never return 'busy' */ 388 data &= ~PHY_BUSY_STATE; 389 break; 390 case R_ECC_TEST_CTRL: 391 /* Always done, always happy */ 392 data |= ECC_TEST_FINISHED; 393 data &= ~ECC_TEST_FAIL; 394 break; 395 default: 396 break; 397 } 398 399 s->regs[reg] = data; 400 } 401 402 static const uint64_t 403 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; 404 405 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) 406 { 407 DeviceClass *dc = DEVICE_CLASS(klass); 408 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 409 410 dc->desc = "ASPEED 2500 SDRAM Memory Controller"; 411 asc->max_ram_size = 1 * GiB; 412 asc->compute_conf = aspeed_2500_sdmc_compute_conf; 413 asc->write = aspeed_2500_sdmc_write; 414 asc->valid_ram_sizes = aspeed_2500_ram_sizes; 415 } 416 417 static const TypeInfo aspeed_2500_sdmc_info = { 418 .name = TYPE_ASPEED_2500_SDMC, 419 .parent = TYPE_ASPEED_SDMC, 420 .class_init = aspeed_2500_sdmc_class_init, 421 }; 422 423 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 424 { 425 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | 426 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 427 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 428 429 /* Make sure readonly bits are kept (use ast2500 mask) */ 430 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 431 432 return data | fixed_conf; 433 } 434 435 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, 436 uint32_t data) 437 { 438 /* Unprotected registers */ 439 switch (reg) { 440 case R_ISR: 441 case R_MCR6C: 442 case R_TEST_START_LEN: 443 case R_TEST_FAIL_DQ: 444 case R_TEST_INIT_VAL: 445 case R_DRAM_SW: 446 case R_DRAM_TIME: 447 case R_ECC_ERR_INJECT: 448 s->regs[reg] = data; 449 return; 450 } 451 452 if (s->regs[R_PROT] == PROT_HARDLOCKED) { 453 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n", 454 __func__); 455 return; 456 } 457 458 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) { 459 qemu_log_mask(LOG_GUEST_ERROR, 460 "%s: SDMC is locked! (write to MCR%02x blocked)\n", 461 __func__, reg * 4); 462 return; 463 } 464 465 switch (reg) { 466 case R_PROT: 467 if (data == PROT_KEY_UNLOCK) { 468 data = PROT_UNLOCKED; 469 } else if (data == PROT_KEY_HARDLOCK) { 470 data = PROT_HARDLOCKED; 471 } else { 472 data = PROT_SOFTLOCKED; 473 } 474 break; 475 case R_CONF: 476 data = aspeed_2600_sdmc_compute_conf(s, data); 477 break; 478 case R_STATUS1: 479 /* Will never return 'busy'. 'lock status' is always set */ 480 data &= ~PHY_BUSY_STATE; 481 data |= PHY_PLL_LOCK_STATUS; 482 break; 483 case R_ECC_TEST_CTRL: 484 /* Always done, always happy */ 485 data |= ECC_TEST_FINISHED; 486 data &= ~ECC_TEST_FAIL; 487 break; 488 default: 489 break; 490 } 491 492 s->regs[reg] = data; 493 } 494 495 static const uint64_t 496 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; 497 498 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) 499 { 500 DeviceClass *dc = DEVICE_CLASS(klass); 501 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 502 503 dc->desc = "ASPEED 2600 SDRAM Memory Controller"; 504 asc->max_ram_size = 2 * GiB; 505 asc->compute_conf = aspeed_2600_sdmc_compute_conf; 506 asc->write = aspeed_2600_sdmc_write; 507 asc->valid_ram_sizes = aspeed_2600_ram_sizes; 508 } 509 510 static const TypeInfo aspeed_2600_sdmc_info = { 511 .name = TYPE_ASPEED_2600_SDMC, 512 .parent = TYPE_ASPEED_SDMC, 513 .class_init = aspeed_2600_sdmc_class_init, 514 }; 515 516 static void aspeed_sdmc_register_types(void) 517 { 518 type_register_static(&aspeed_sdmc_info); 519 type_register_static(&aspeed_2400_sdmc_info); 520 type_register_static(&aspeed_2500_sdmc_info); 521 type_register_static(&aspeed_2600_sdmc_info); 522 } 523 524 type_init(aspeed_sdmc_register_types); 525