1 /* 2 * ASPEED SDRAM Memory Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "hw/misc/aspeed_sdmc.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "qapi/error.h" 16 #include "trace.h" 17 18 /* Protection Key Register */ 19 #define R_PROT (0x00 / 4) 20 #define PROT_KEY_UNLOCK 0xFC600309 21 22 /* Configuration Register */ 23 #define R_CONF (0x04 / 4) 24 25 /* 26 * Configuration register Ox4 (for Aspeed AST2400 SOC) 27 * 28 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is 29 * what we care about right now as it is checked by U-Boot to 30 * determine the RAM size. 31 */ 32 33 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ 34 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) 35 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) 36 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) 37 #define ASPEED_SDMC_ECC_ENABLE (1 << 7) 38 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ 39 #define ASPEED_SDMC_DRAM_BANK (1 << 5) 40 #define ASPEED_SDMC_DRAM_BURST (1 << 4) 41 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ 42 #define ASPEED_SDMC_VGA_8MB 0x0 43 #define ASPEED_SDMC_VGA_16MB 0x1 44 #define ASPEED_SDMC_VGA_32MB 0x2 45 #define ASPEED_SDMC_VGA_64MB 0x3 46 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) 47 #define ASPEED_SDMC_DRAM_64MB 0x0 48 #define ASPEED_SDMC_DRAM_128MB 0x1 49 #define ASPEED_SDMC_DRAM_256MB 0x2 50 #define ASPEED_SDMC_DRAM_512MB 0x3 51 52 #define ASPEED_SDMC_READONLY_MASK \ 53 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 54 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 55 /* 56 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) 57 * 58 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION 59 * should be set to 1 for the AST2500 SOC. 60 */ 61 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ 62 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) 63 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ 64 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ 65 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) 66 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) 67 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) 68 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ 69 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ 70 71 /* DRAM size definitions differs */ 72 #define ASPEED_SDMC_AST2500_128MB 0x0 73 #define ASPEED_SDMC_AST2500_256MB 0x1 74 #define ASPEED_SDMC_AST2500_512MB 0x2 75 #define ASPEED_SDMC_AST2500_1024MB 0x3 76 77 #define ASPEED_SDMC_AST2500_READONLY_MASK \ 78 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ 79 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 80 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 81 82 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) 83 { 84 AspeedSDMCState *s = ASPEED_SDMC(opaque); 85 86 addr >>= 2; 87 88 if (addr >= ARRAY_SIZE(s->regs)) { 89 qemu_log_mask(LOG_GUEST_ERROR, 90 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 91 __func__, addr); 92 return 0; 93 } 94 95 return s->regs[addr]; 96 } 97 98 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 99 unsigned int size) 100 { 101 AspeedSDMCState *s = ASPEED_SDMC(opaque); 102 103 addr >>= 2; 104 105 if (addr >= ARRAY_SIZE(s->regs)) { 106 qemu_log_mask(LOG_GUEST_ERROR, 107 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 108 __func__, addr); 109 return; 110 } 111 112 if (addr != R_PROT && s->regs[R_PROT] != PROT_KEY_UNLOCK) { 113 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 114 return; 115 } 116 117 if (addr == R_CONF) { 118 /* Make sure readonly bits are kept */ 119 switch (s->silicon_rev) { 120 case AST2400_A0_SILICON_REV: 121 data &= ~ASPEED_SDMC_READONLY_MASK; 122 break; 123 case AST2500_A0_SILICON_REV: 124 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 125 break; 126 default: 127 g_assert_not_reached(); 128 } 129 } 130 131 s->regs[addr] = data; 132 } 133 134 static const MemoryRegionOps aspeed_sdmc_ops = { 135 .read = aspeed_sdmc_read, 136 .write = aspeed_sdmc_write, 137 .endianness = DEVICE_LITTLE_ENDIAN, 138 .valid.min_access_size = 4, 139 .valid.max_access_size = 4, 140 }; 141 142 static int ast2400_rambits(void) 143 { 144 switch (ram_size >> 20) { 145 case 64: 146 return ASPEED_SDMC_DRAM_64MB; 147 case 128: 148 return ASPEED_SDMC_DRAM_128MB; 149 case 256: 150 return ASPEED_SDMC_DRAM_256MB; 151 case 512: 152 return ASPEED_SDMC_DRAM_512MB; 153 default: 154 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid RAM size: 0x" 155 RAM_ADDR_FMT "\n", __func__, ram_size); 156 break; 157 } 158 159 /* set a minimum default */ 160 return ASPEED_SDMC_DRAM_64MB; 161 } 162 163 static int ast2500_rambits(void) 164 { 165 switch (ram_size >> 20) { 166 case 128: 167 return ASPEED_SDMC_AST2500_128MB; 168 case 256: 169 return ASPEED_SDMC_AST2500_256MB; 170 case 512: 171 return ASPEED_SDMC_AST2500_512MB; 172 case 1024: 173 return ASPEED_SDMC_AST2500_1024MB; 174 default: 175 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid RAM size: 0x" 176 RAM_ADDR_FMT "\n", __func__, ram_size); 177 break; 178 } 179 180 /* set a minimum default */ 181 return ASPEED_SDMC_AST2500_128MB; 182 } 183 184 static void aspeed_sdmc_reset(DeviceState *dev) 185 { 186 AspeedSDMCState *s = ASPEED_SDMC(dev); 187 188 memset(s->regs, 0, sizeof(s->regs)); 189 190 /* Set ram size bit and defaults values */ 191 switch (s->silicon_rev) { 192 case AST2400_A0_SILICON_REV: 193 s->regs[R_CONF] |= 194 ASPEED_SDMC_VGA_COMPAT | 195 ASPEED_SDMC_DRAM_SIZE(ast2400_rambits()); 196 break; 197 198 case AST2500_A0_SILICON_REV: 199 s->regs[R_CONF] |= 200 ASPEED_SDMC_HW_VERSION(1) | 201 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 202 ASPEED_SDMC_DRAM_SIZE(ast2500_rambits()); 203 break; 204 205 default: 206 g_assert_not_reached(); 207 } 208 } 209 210 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 211 { 212 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 213 AspeedSDMCState *s = ASPEED_SDMC(dev); 214 215 if (!is_supported_silicon_rev(s->silicon_rev)) { 216 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 217 s->silicon_rev); 218 return; 219 } 220 221 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, 222 TYPE_ASPEED_SDMC, 0x1000); 223 sysbus_init_mmio(sbd, &s->iomem); 224 } 225 226 static const VMStateDescription vmstate_aspeed_sdmc = { 227 .name = "aspeed.sdmc", 228 .version_id = 1, 229 .minimum_version_id = 1, 230 .fields = (VMStateField[]) { 231 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static Property aspeed_sdmc_properties[] = { 237 DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), 238 DEFINE_PROP_END_OF_LIST(), 239 }; 240 241 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) 242 { 243 DeviceClass *dc = DEVICE_CLASS(klass); 244 dc->realize = aspeed_sdmc_realize; 245 dc->reset = aspeed_sdmc_reset; 246 dc->desc = "ASPEED SDRAM Memory Controller"; 247 dc->vmsd = &vmstate_aspeed_sdmc; 248 dc->props = aspeed_sdmc_properties; 249 } 250 251 static const TypeInfo aspeed_sdmc_info = { 252 .name = TYPE_ASPEED_SDMC, 253 .parent = TYPE_SYS_BUS_DEVICE, 254 .instance_size = sizeof(AspeedSDMCState), 255 .class_init = aspeed_sdmc_class_init, 256 }; 257 258 static void aspeed_sdmc_register_types(void) 259 { 260 type_register_static(&aspeed_sdmc_info); 261 } 262 263 type_init(aspeed_sdmc_register_types); 264