1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "migration/vmstate.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "qemu/bitops.h" 19 #include "qemu/log.h" 20 #include "qemu/guest-random.h" 21 #include "qemu/module.h" 22 #include "trace.h" 23 24 #define TO_REG(offset) ((offset) >> 2) 25 26 #define PROT_KEY TO_REG(0x00) 27 #define SYS_RST_CTRL TO_REG(0x04) 28 #define CLK_SEL TO_REG(0x08) 29 #define CLK_STOP_CTRL TO_REG(0x0C) 30 #define FREQ_CNTR_CTRL TO_REG(0x10) 31 #define FREQ_CNTR_EVAL TO_REG(0x14) 32 #define IRQ_CTRL TO_REG(0x18) 33 #define D2PLL_PARAM TO_REG(0x1C) 34 #define MPLL_PARAM TO_REG(0x20) 35 #define HPLL_PARAM TO_REG(0x24) 36 #define FREQ_CNTR_RANGE TO_REG(0x28) 37 #define MISC_CTRL1 TO_REG(0x2C) 38 #define PCI_CTRL1 TO_REG(0x30) 39 #define PCI_CTRL2 TO_REG(0x34) 40 #define PCI_CTRL3 TO_REG(0x38) 41 #define SYS_RST_STATUS TO_REG(0x3C) 42 #define SOC_SCRATCH1 TO_REG(0x40) 43 #define SOC_SCRATCH2 TO_REG(0x44) 44 #define MAC_CLK_DELAY TO_REG(0x48) 45 #define MISC_CTRL2 TO_REG(0x4C) 46 #define VGA_SCRATCH1 TO_REG(0x50) 47 #define VGA_SCRATCH2 TO_REG(0x54) 48 #define VGA_SCRATCH3 TO_REG(0x58) 49 #define VGA_SCRATCH4 TO_REG(0x5C) 50 #define VGA_SCRATCH5 TO_REG(0x60) 51 #define VGA_SCRATCH6 TO_REG(0x64) 52 #define VGA_SCRATCH7 TO_REG(0x68) 53 #define VGA_SCRATCH8 TO_REG(0x6C) 54 #define HW_STRAP1 TO_REG(0x70) 55 #define RNG_CTRL TO_REG(0x74) 56 #define RNG_DATA TO_REG(0x78) 57 #define SILICON_REV TO_REG(0x7C) 58 #define PINMUX_CTRL1 TO_REG(0x80) 59 #define PINMUX_CTRL2 TO_REG(0x84) 60 #define PINMUX_CTRL3 TO_REG(0x88) 61 #define PINMUX_CTRL4 TO_REG(0x8C) 62 #define PINMUX_CTRL5 TO_REG(0x90) 63 #define PINMUX_CTRL6 TO_REG(0x94) 64 #define WDT_RST_CTRL TO_REG(0x9C) 65 #define PINMUX_CTRL7 TO_REG(0xA0) 66 #define PINMUX_CTRL8 TO_REG(0xA4) 67 #define PINMUX_CTRL9 TO_REG(0xA8) 68 #define WAKEUP_EN TO_REG(0xC0) 69 #define WAKEUP_CTRL TO_REG(0xC4) 70 #define HW_STRAP2 TO_REG(0xD0) 71 #define FREE_CNTR4 TO_REG(0xE0) 72 #define FREE_CNTR4_EXT TO_REG(0xE4) 73 #define CPU2_CTRL TO_REG(0x100) 74 #define CPU2_BASE_SEG1 TO_REG(0x104) 75 #define CPU2_BASE_SEG2 TO_REG(0x108) 76 #define CPU2_BASE_SEG3 TO_REG(0x10C) 77 #define CPU2_BASE_SEG4 TO_REG(0x110) 78 #define CPU2_BASE_SEG5 TO_REG(0x114) 79 #define CPU2_CACHE_CTRL TO_REG(0x118) 80 #define UART_HPLL_CLK TO_REG(0x160) 81 #define PCIE_CTRL TO_REG(0x180) 82 #define BMC_MMIO_CTRL TO_REG(0x184) 83 #define RELOC_DECODE_BASE1 TO_REG(0x188) 84 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 85 #define MAILBOX_DECODE_BASE TO_REG(0x190) 86 #define SRAM_DECODE_BASE1 TO_REG(0x194) 87 #define SRAM_DECODE_BASE2 TO_REG(0x198) 88 #define BMC_REV TO_REG(0x19C) 89 #define BMC_DEV_ID TO_REG(0x1A4) 90 91 #define SCU_IO_REGION_SIZE 0x1000 92 93 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 94 [SYS_RST_CTRL] = 0xFFCFFEDCU, 95 [CLK_SEL] = 0xF3F40000U, 96 [CLK_STOP_CTRL] = 0x19FC3E8BU, 97 [D2PLL_PARAM] = 0x00026108U, 98 [MPLL_PARAM] = 0x00030291U, 99 [HPLL_PARAM] = 0x00000291U, 100 [MISC_CTRL1] = 0x00000010U, 101 [PCI_CTRL1] = 0x20001A03U, 102 [PCI_CTRL2] = 0x20001A03U, 103 [PCI_CTRL3] = 0x04000030U, 104 [SYS_RST_STATUS] = 0x00000001U, 105 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 106 [MISC_CTRL2] = 0x00000023U, 107 [RNG_CTRL] = 0x0000000EU, 108 [PINMUX_CTRL2] = 0x0000F000U, 109 [PINMUX_CTRL3] = 0x01000000U, 110 [PINMUX_CTRL4] = 0x000000FFU, 111 [PINMUX_CTRL5] = 0x0000A000U, 112 [WDT_RST_CTRL] = 0x003FFFF3U, 113 [PINMUX_CTRL8] = 0xFFFF0000U, 114 [PINMUX_CTRL9] = 0x000FFFFFU, 115 [FREE_CNTR4] = 0x000000FFU, 116 [FREE_CNTR4_EXT] = 0x000000FFU, 117 [CPU2_BASE_SEG1] = 0x80000000U, 118 [CPU2_BASE_SEG4] = 0x1E600000U, 119 [CPU2_BASE_SEG5] = 0xC0000000U, 120 [UART_HPLL_CLK] = 0x00001903U, 121 [PCIE_CTRL] = 0x0000007BU, 122 [BMC_DEV_ID] = 0x00002402U 123 }; 124 125 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 126 /* AST2500 revision A1 */ 127 128 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 129 [SYS_RST_CTRL] = 0xFFCFFEDCU, 130 [CLK_SEL] = 0xF3F40000U, 131 [CLK_STOP_CTRL] = 0x19FC3E8BU, 132 [D2PLL_PARAM] = 0x00026108U, 133 [MPLL_PARAM] = 0x00030291U, 134 [HPLL_PARAM] = 0x93000400U, 135 [MISC_CTRL1] = 0x00000010U, 136 [PCI_CTRL1] = 0x20001A03U, 137 [PCI_CTRL2] = 0x20001A03U, 138 [PCI_CTRL3] = 0x04000030U, 139 [SYS_RST_STATUS] = 0x00000001U, 140 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 141 [MISC_CTRL2] = 0x00000023U, 142 [RNG_CTRL] = 0x0000000EU, 143 [PINMUX_CTRL2] = 0x0000F000U, 144 [PINMUX_CTRL3] = 0x03000000U, 145 [PINMUX_CTRL4] = 0x00000000U, 146 [PINMUX_CTRL5] = 0x0000A000U, 147 [WDT_RST_CTRL] = 0x023FFFF3U, 148 [PINMUX_CTRL8] = 0xFFFF0000U, 149 [PINMUX_CTRL9] = 0x000FFFFFU, 150 [FREE_CNTR4] = 0x000000FFU, 151 [FREE_CNTR4_EXT] = 0x000000FFU, 152 [CPU2_BASE_SEG1] = 0x80000000U, 153 [CPU2_BASE_SEG4] = 0x1E600000U, 154 [CPU2_BASE_SEG5] = 0xC0000000U, 155 [UART_HPLL_CLK] = 0x00001903U, 156 [PCIE_CTRL] = 0x0000007BU, 157 [BMC_DEV_ID] = 0x00002402U 158 }; 159 160 static uint32_t aspeed_scu_get_random(void) 161 { 162 uint32_t num; 163 qemu_guest_getrandom_nofail(&num, sizeof(num)); 164 return num; 165 } 166 167 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) 168 { 169 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 170 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); 171 172 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) 173 / asc->apb_divider; 174 } 175 176 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 177 { 178 AspeedSCUState *s = ASPEED_SCU(opaque); 179 int reg = TO_REG(offset); 180 181 if (reg >= ARRAY_SIZE(s->regs)) { 182 qemu_log_mask(LOG_GUEST_ERROR, 183 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 184 __func__, offset); 185 return 0; 186 } 187 188 switch (reg) { 189 case RNG_DATA: 190 /* On hardware, RNG_DATA works regardless of 191 * the state of the enable bit in RNG_CTRL 192 */ 193 s->regs[RNG_DATA] = aspeed_scu_get_random(); 194 break; 195 case WAKEUP_EN: 196 qemu_log_mask(LOG_GUEST_ERROR, 197 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 198 __func__, offset); 199 break; 200 } 201 202 return s->regs[reg]; 203 } 204 205 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, 206 unsigned size) 207 { 208 AspeedSCUState *s = ASPEED_SCU(opaque); 209 int reg = TO_REG(offset); 210 211 if (reg >= ARRAY_SIZE(s->regs)) { 212 qemu_log_mask(LOG_GUEST_ERROR, 213 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 214 __func__, offset); 215 return; 216 } 217 218 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 219 !s->regs[PROT_KEY]) { 220 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 221 return; 222 } 223 224 trace_aspeed_scu_write(offset, size, data); 225 226 switch (reg) { 227 case PROT_KEY: 228 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 229 return; 230 case CLK_SEL: 231 s->regs[reg] = data; 232 break; 233 case HW_STRAP1: 234 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { 235 s->regs[HW_STRAP1] |= data; 236 return; 237 } 238 /* Jump to assignment below */ 239 break; 240 case SILICON_REV: 241 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { 242 s->regs[HW_STRAP1] &= ~data; 243 } else { 244 qemu_log_mask(LOG_GUEST_ERROR, 245 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 246 __func__, offset); 247 } 248 /* Avoid assignment below, we've handled everything */ 249 return; 250 case FREQ_CNTR_EVAL: 251 case VGA_SCRATCH1 ... VGA_SCRATCH8: 252 case RNG_DATA: 253 case FREE_CNTR4: 254 case FREE_CNTR4_EXT: 255 qemu_log_mask(LOG_GUEST_ERROR, 256 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 257 __func__, offset); 258 return; 259 } 260 261 s->regs[reg] = data; 262 } 263 264 static const MemoryRegionOps aspeed_scu_ops = { 265 .read = aspeed_scu_read, 266 .write = aspeed_scu_write, 267 .endianness = DEVICE_LITTLE_ENDIAN, 268 .valid.min_access_size = 4, 269 .valid.max_access_size = 4, 270 .valid.unaligned = false, 271 }; 272 273 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) 274 { 275 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) { 276 return 25000000; 277 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { 278 return 48000000; 279 } else { 280 return 24000000; 281 } 282 } 283 284 /* 285 * Strapped frequencies for the AST2400 in MHz. They depend on the 286 * clkin frequency. 287 */ 288 static const uint32_t hpll_ast2400_freqs[][4] = { 289 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ 290 { 400, 375, 350, 425 }, /* 25MHz */ 291 }; 292 293 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 294 { 295 uint8_t freq_select; 296 bool clk_25m_in; 297 uint32_t clkin = aspeed_scu_get_clkin(s); 298 299 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { 300 return 0; 301 } 302 303 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { 304 uint32_t multiplier = 1; 305 306 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { 307 uint32_t n = (hpll_reg >> 5) & 0x3f; 308 uint32_t od = (hpll_reg >> 4) & 0x1; 309 uint32_t d = hpll_reg & 0xf; 310 311 multiplier = (2 - od) * ((n + 2) / (d + 1)); 312 } 313 314 return clkin * multiplier; 315 } 316 317 /* HW strapping */ 318 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); 319 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); 320 321 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; 322 } 323 324 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 325 { 326 uint32_t multiplier = 1; 327 uint32_t clkin = aspeed_scu_get_clkin(s); 328 329 if (hpll_reg & SCU_H_PLL_OFF) { 330 return 0; 331 } 332 333 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { 334 uint32_t p = (hpll_reg >> 13) & 0x3f; 335 uint32_t m = (hpll_reg >> 5) & 0xff; 336 uint32_t n = hpll_reg & 0x1f; 337 338 multiplier = ((m + 1) / (n + 1)) / (p + 1); 339 } 340 341 return clkin * multiplier; 342 } 343 344 static void aspeed_scu_reset(DeviceState *dev) 345 { 346 AspeedSCUState *s = ASPEED_SCU(dev); 347 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 348 349 memcpy(s->regs, asc->resets, sizeof(s->regs)); 350 s->regs[SILICON_REV] = s->silicon_rev; 351 s->regs[HW_STRAP1] = s->hw_strap1; 352 s->regs[HW_STRAP2] = s->hw_strap2; 353 s->regs[PROT_KEY] = s->hw_prot_key; 354 } 355 356 static uint32_t aspeed_silicon_revs[] = { 357 AST2400_A0_SILICON_REV, 358 AST2400_A1_SILICON_REV, 359 AST2500_A0_SILICON_REV, 360 AST2500_A1_SILICON_REV, 361 }; 362 363 bool is_supported_silicon_rev(uint32_t silicon_rev) 364 { 365 int i; 366 367 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 368 if (silicon_rev == aspeed_silicon_revs[i]) { 369 return true; 370 } 371 } 372 373 return false; 374 } 375 376 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 377 { 378 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 379 AspeedSCUState *s = ASPEED_SCU(dev); 380 381 if (!is_supported_silicon_rev(s->silicon_rev)) { 382 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 383 s->silicon_rev); 384 return; 385 } 386 387 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, 388 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 389 390 sysbus_init_mmio(sbd, &s->iomem); 391 } 392 393 static const VMStateDescription vmstate_aspeed_scu = { 394 .name = "aspeed.scu", 395 .version_id = 1, 396 .minimum_version_id = 1, 397 .fields = (VMStateField[]) { 398 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), 399 VMSTATE_END_OF_LIST() 400 } 401 }; 402 403 static Property aspeed_scu_properties[] = { 404 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 405 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 406 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 407 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), 408 DEFINE_PROP_END_OF_LIST(), 409 }; 410 411 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 412 { 413 DeviceClass *dc = DEVICE_CLASS(klass); 414 dc->realize = aspeed_scu_realize; 415 dc->reset = aspeed_scu_reset; 416 dc->desc = "ASPEED System Control Unit"; 417 dc->vmsd = &vmstate_aspeed_scu; 418 dc->props = aspeed_scu_properties; 419 } 420 421 static const TypeInfo aspeed_scu_info = { 422 .name = TYPE_ASPEED_SCU, 423 .parent = TYPE_SYS_BUS_DEVICE, 424 .instance_size = sizeof(AspeedSCUState), 425 .class_init = aspeed_scu_class_init, 426 .class_size = sizeof(AspeedSCUClass), 427 .abstract = true, 428 }; 429 430 static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) 431 { 432 DeviceClass *dc = DEVICE_CLASS(klass); 433 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 434 435 dc->desc = "ASPEED 2400 System Control Unit"; 436 asc->resets = ast2400_a0_resets; 437 asc->calc_hpll = aspeed_2400_scu_calc_hpll; 438 asc->apb_divider = 2; 439 } 440 441 static const TypeInfo aspeed_2400_scu_info = { 442 .name = TYPE_ASPEED_2400_SCU, 443 .parent = TYPE_ASPEED_SCU, 444 .instance_size = sizeof(AspeedSCUState), 445 .class_init = aspeed_2400_scu_class_init, 446 }; 447 448 static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) 449 { 450 DeviceClass *dc = DEVICE_CLASS(klass); 451 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 452 453 dc->desc = "ASPEED 2500 System Control Unit"; 454 asc->resets = ast2500_a1_resets; 455 asc->calc_hpll = aspeed_2500_scu_calc_hpll; 456 asc->apb_divider = 4; 457 } 458 459 static const TypeInfo aspeed_2500_scu_info = { 460 .name = TYPE_ASPEED_2500_SCU, 461 .parent = TYPE_ASPEED_SCU, 462 .instance_size = sizeof(AspeedSCUState), 463 .class_init = aspeed_2500_scu_class_init, 464 }; 465 466 static void aspeed_scu_register_types(void) 467 { 468 type_register_static(&aspeed_scu_info); 469 type_register_static(&aspeed_2400_scu_info); 470 type_register_static(&aspeed_2500_scu_info); 471 } 472 473 type_init(aspeed_scu_register_types); 474