1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "migration/vmstate.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "qemu/bitops.h" 19 #include "qemu/log.h" 20 #include "qemu/guest-random.h" 21 #include "qemu/module.h" 22 #include "trace.h" 23 24 #define TO_REG(offset) ((offset) >> 2) 25 26 #define PROT_KEY TO_REG(0x00) 27 #define SYS_RST_CTRL TO_REG(0x04) 28 #define CLK_SEL TO_REG(0x08) 29 #define CLK_STOP_CTRL TO_REG(0x0C) 30 #define FREQ_CNTR_CTRL TO_REG(0x10) 31 #define FREQ_CNTR_EVAL TO_REG(0x14) 32 #define IRQ_CTRL TO_REG(0x18) 33 #define D2PLL_PARAM TO_REG(0x1C) 34 #define MPLL_PARAM TO_REG(0x20) 35 #define HPLL_PARAM TO_REG(0x24) 36 #define FREQ_CNTR_RANGE TO_REG(0x28) 37 #define MISC_CTRL1 TO_REG(0x2C) 38 #define PCI_CTRL1 TO_REG(0x30) 39 #define PCI_CTRL2 TO_REG(0x34) 40 #define PCI_CTRL3 TO_REG(0x38) 41 #define SYS_RST_STATUS TO_REG(0x3C) 42 #define SOC_SCRATCH1 TO_REG(0x40) 43 #define SOC_SCRATCH2 TO_REG(0x44) 44 #define MAC_CLK_DELAY TO_REG(0x48) 45 #define MISC_CTRL2 TO_REG(0x4C) 46 #define VGA_SCRATCH1 TO_REG(0x50) 47 #define VGA_SCRATCH2 TO_REG(0x54) 48 #define VGA_SCRATCH3 TO_REG(0x58) 49 #define VGA_SCRATCH4 TO_REG(0x5C) 50 #define VGA_SCRATCH5 TO_REG(0x60) 51 #define VGA_SCRATCH6 TO_REG(0x64) 52 #define VGA_SCRATCH7 TO_REG(0x68) 53 #define VGA_SCRATCH8 TO_REG(0x6C) 54 #define HW_STRAP1 TO_REG(0x70) 55 #define RNG_CTRL TO_REG(0x74) 56 #define RNG_DATA TO_REG(0x78) 57 #define SILICON_REV TO_REG(0x7C) 58 #define PINMUX_CTRL1 TO_REG(0x80) 59 #define PINMUX_CTRL2 TO_REG(0x84) 60 #define PINMUX_CTRL3 TO_REG(0x88) 61 #define PINMUX_CTRL4 TO_REG(0x8C) 62 #define PINMUX_CTRL5 TO_REG(0x90) 63 #define PINMUX_CTRL6 TO_REG(0x94) 64 #define WDT_RST_CTRL TO_REG(0x9C) 65 #define PINMUX_CTRL7 TO_REG(0xA0) 66 #define PINMUX_CTRL8 TO_REG(0xA4) 67 #define PINMUX_CTRL9 TO_REG(0xA8) 68 #define WAKEUP_EN TO_REG(0xC0) 69 #define WAKEUP_CTRL TO_REG(0xC4) 70 #define HW_STRAP2 TO_REG(0xD0) 71 #define FREE_CNTR4 TO_REG(0xE0) 72 #define FREE_CNTR4_EXT TO_REG(0xE4) 73 #define CPU2_CTRL TO_REG(0x100) 74 #define CPU2_BASE_SEG1 TO_REG(0x104) 75 #define CPU2_BASE_SEG2 TO_REG(0x108) 76 #define CPU2_BASE_SEG3 TO_REG(0x10C) 77 #define CPU2_BASE_SEG4 TO_REG(0x110) 78 #define CPU2_BASE_SEG5 TO_REG(0x114) 79 #define CPU2_CACHE_CTRL TO_REG(0x118) 80 #define CHIP_ID0 TO_REG(0x150) 81 #define CHIP_ID1 TO_REG(0x154) 82 #define UART_HPLL_CLK TO_REG(0x160) 83 #define PCIE_CTRL TO_REG(0x180) 84 #define BMC_MMIO_CTRL TO_REG(0x184) 85 #define RELOC_DECODE_BASE1 TO_REG(0x188) 86 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 87 #define MAILBOX_DECODE_BASE TO_REG(0x190) 88 #define SRAM_DECODE_BASE1 TO_REG(0x194) 89 #define SRAM_DECODE_BASE2 TO_REG(0x198) 90 #define BMC_REV TO_REG(0x19C) 91 #define BMC_DEV_ID TO_REG(0x1A4) 92 93 #define AST2600_PROT_KEY TO_REG(0x00) 94 #define AST2600_SILICON_REV TO_REG(0x04) 95 #define AST2600_SILICON_REV2 TO_REG(0x14) 96 #define AST2600_SYS_RST_CTRL TO_REG(0x40) 97 #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) 98 #define AST2600_SYS_RST_CTRL2 TO_REG(0x50) 99 #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) 100 #define AST2600_CLK_STOP_CTRL TO_REG(0x80) 101 #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) 102 #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) 103 #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) 104 #define AST2600_DEBUG_CTRL TO_REG(0xC8) 105 #define AST2600_DEBUG_CTRL2 TO_REG(0xD8) 106 #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) 107 #define AST2600_HPLL_PARAM TO_REG(0x200) 108 #define AST2600_HPLL_EXT TO_REG(0x204) 109 #define AST2600_APLL_PARAM TO_REG(0x210) 110 #define AST2600_APLL_EXT TO_REG(0x214) 111 #define AST2600_MPLL_PARAM TO_REG(0x220) 112 #define AST2600_MPLL_EXT TO_REG(0x224) 113 #define AST2600_EPLL_PARAM TO_REG(0x240) 114 #define AST2600_EPLL_EXT TO_REG(0x244) 115 #define AST2600_DPLL_PARAM TO_REG(0x260) 116 #define AST2600_DPLL_EXT TO_REG(0x264) 117 #define AST2600_CLK_SEL TO_REG(0x300) 118 #define AST2600_CLK_SEL2 TO_REG(0x304) 119 #define AST2600_CLK_SEL3 TO_REG(0x308) 120 #define AST2600_CLK_SEL4 TO_REG(0x310) 121 #define AST2600_CLK_SEL5 TO_REG(0x314) 122 #define AST2600_HW_STRAP1 TO_REG(0x500) 123 #define AST2600_HW_STRAP1_CLR TO_REG(0x504) 124 #define AST2600_HW_STRAP1_PROT TO_REG(0x508) 125 #define AST2600_HW_STRAP2 TO_REG(0x510) 126 #define AST2600_HW_STRAP2_CLR TO_REG(0x514) 127 #define AST2600_HW_STRAP2_PROT TO_REG(0x518) 128 #define AST2600_RNG_CTRL TO_REG(0x524) 129 #define AST2600_RNG_DATA TO_REG(0x540) 130 #define AST2600_CHIP_ID0 TO_REG(0x5B0) 131 #define AST2600_CHIP_ID1 TO_REG(0x5B4) 132 133 #define AST2600_CLK TO_REG(0x40) 134 135 #define SCU_IO_REGION_SIZE 0x1000 136 137 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 138 [SYS_RST_CTRL] = 0xFFCFFEDCU, 139 [CLK_SEL] = 0xF3F40000U, 140 [CLK_STOP_CTRL] = 0x19FC3E8BU, 141 [D2PLL_PARAM] = 0x00026108U, 142 [MPLL_PARAM] = 0x00030291U, 143 [HPLL_PARAM] = 0x00000291U, 144 [MISC_CTRL1] = 0x00000010U, 145 [PCI_CTRL1] = 0x20001A03U, 146 [PCI_CTRL2] = 0x20001A03U, 147 [PCI_CTRL3] = 0x04000030U, 148 [SYS_RST_STATUS] = 0x00000001U, 149 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 150 [MISC_CTRL2] = 0x00000023U, 151 [RNG_CTRL] = 0x0000000EU, 152 [PINMUX_CTRL2] = 0x0000F000U, 153 [PINMUX_CTRL3] = 0x01000000U, 154 [PINMUX_CTRL4] = 0x000000FFU, 155 [PINMUX_CTRL5] = 0x0000A000U, 156 [WDT_RST_CTRL] = 0x003FFFF3U, 157 [PINMUX_CTRL8] = 0xFFFF0000U, 158 [PINMUX_CTRL9] = 0x000FFFFFU, 159 [FREE_CNTR4] = 0x000000FFU, 160 [FREE_CNTR4_EXT] = 0x000000FFU, 161 [CPU2_BASE_SEG1] = 0x80000000U, 162 [CPU2_BASE_SEG4] = 0x1E600000U, 163 [CPU2_BASE_SEG5] = 0xC0000000U, 164 [UART_HPLL_CLK] = 0x00001903U, 165 [PCIE_CTRL] = 0x0000007BU, 166 [BMC_DEV_ID] = 0x00002402U 167 }; 168 169 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 170 /* AST2500 revision A1 */ 171 172 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 173 [SYS_RST_CTRL] = 0xFFCFFEDCU, 174 [CLK_SEL] = 0xF3F40000U, 175 [CLK_STOP_CTRL] = 0x19FC3E8BU, 176 [D2PLL_PARAM] = 0x00026108U, 177 [MPLL_PARAM] = 0x00030291U, 178 [HPLL_PARAM] = 0x93000400U, 179 [MISC_CTRL1] = 0x00000010U, 180 [PCI_CTRL1] = 0x20001A03U, 181 [PCI_CTRL2] = 0x20001A03U, 182 [PCI_CTRL3] = 0x04000030U, 183 [SYS_RST_STATUS] = 0x00000001U, 184 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 185 [MISC_CTRL2] = 0x00000023U, 186 [RNG_CTRL] = 0x0000000EU, 187 [PINMUX_CTRL2] = 0x0000F000U, 188 [PINMUX_CTRL3] = 0x03000000U, 189 [PINMUX_CTRL4] = 0x00000000U, 190 [PINMUX_CTRL5] = 0x0000A000U, 191 [WDT_RST_CTRL] = 0x023FFFF3U, 192 [PINMUX_CTRL8] = 0xFFFF0000U, 193 [PINMUX_CTRL9] = 0x000FFFFFU, 194 [FREE_CNTR4] = 0x000000FFU, 195 [FREE_CNTR4_EXT] = 0x000000FFU, 196 [CPU2_BASE_SEG1] = 0x80000000U, 197 [CPU2_BASE_SEG4] = 0x1E600000U, 198 [CPU2_BASE_SEG5] = 0xC0000000U, 199 [CHIP_ID0] = 0x1234ABCDU, 200 [CHIP_ID1] = 0x88884444U, 201 [UART_HPLL_CLK] = 0x00001903U, 202 [PCIE_CTRL] = 0x0000007BU, 203 [BMC_DEV_ID] = 0x00002402U 204 }; 205 206 static uint32_t aspeed_scu_get_random(void) 207 { 208 uint32_t num; 209 qemu_guest_getrandom_nofail(&num, sizeof(num)); 210 return num; 211 } 212 213 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) 214 { 215 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 216 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); 217 218 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) 219 / asc->apb_divider; 220 } 221 222 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 223 { 224 AspeedSCUState *s = ASPEED_SCU(opaque); 225 int reg = TO_REG(offset); 226 227 if (reg >= ASPEED_SCU_NR_REGS) { 228 qemu_log_mask(LOG_GUEST_ERROR, 229 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 230 __func__, offset); 231 return 0; 232 } 233 234 switch (reg) { 235 case RNG_DATA: 236 /* On hardware, RNG_DATA works regardless of 237 * the state of the enable bit in RNG_CTRL 238 */ 239 s->regs[RNG_DATA] = aspeed_scu_get_random(); 240 break; 241 case WAKEUP_EN: 242 qemu_log_mask(LOG_GUEST_ERROR, 243 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 244 __func__, offset); 245 break; 246 } 247 248 return s->regs[reg]; 249 } 250 251 static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, 252 uint64_t data, unsigned size) 253 { 254 AspeedSCUState *s = ASPEED_SCU(opaque); 255 int reg = TO_REG(offset); 256 257 if (reg >= ASPEED_SCU_NR_REGS) { 258 qemu_log_mask(LOG_GUEST_ERROR, 259 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 260 __func__, offset); 261 return; 262 } 263 264 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 265 !s->regs[PROT_KEY]) { 266 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 267 } 268 269 trace_aspeed_scu_write(offset, size, data); 270 271 switch (reg) { 272 case PROT_KEY: 273 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 274 return; 275 case SILICON_REV: 276 case FREQ_CNTR_EVAL: 277 case VGA_SCRATCH1 ... VGA_SCRATCH8: 278 case RNG_DATA: 279 case FREE_CNTR4: 280 case FREE_CNTR4_EXT: 281 qemu_log_mask(LOG_GUEST_ERROR, 282 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 283 __func__, offset); 284 return; 285 } 286 287 s->regs[reg] = data; 288 } 289 290 static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, 291 uint64_t data, unsigned size) 292 { 293 AspeedSCUState *s = ASPEED_SCU(opaque); 294 int reg = TO_REG(offset); 295 296 if (reg >= ASPEED_SCU_NR_REGS) { 297 qemu_log_mask(LOG_GUEST_ERROR, 298 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 299 __func__, offset); 300 return; 301 } 302 303 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 304 !s->regs[PROT_KEY]) { 305 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 306 return; 307 } 308 309 trace_aspeed_scu_write(offset, size, data); 310 311 switch (reg) { 312 case PROT_KEY: 313 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 314 return; 315 case HW_STRAP1: 316 s->regs[HW_STRAP1] |= data; 317 return; 318 case SILICON_REV: 319 s->regs[HW_STRAP1] &= ~data; 320 return; 321 case FREQ_CNTR_EVAL: 322 case VGA_SCRATCH1 ... VGA_SCRATCH8: 323 case RNG_DATA: 324 case FREE_CNTR4: 325 case FREE_CNTR4_EXT: 326 case CHIP_ID0: 327 case CHIP_ID1: 328 qemu_log_mask(LOG_GUEST_ERROR, 329 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 330 __func__, offset); 331 return; 332 } 333 334 s->regs[reg] = data; 335 } 336 337 static const MemoryRegionOps aspeed_ast2400_scu_ops = { 338 .read = aspeed_scu_read, 339 .write = aspeed_ast2400_scu_write, 340 .endianness = DEVICE_LITTLE_ENDIAN, 341 .valid = { 342 .min_access_size = 1, 343 .max_access_size = 4, 344 }, 345 }; 346 347 static const MemoryRegionOps aspeed_ast2500_scu_ops = { 348 .read = aspeed_scu_read, 349 .write = aspeed_ast2500_scu_write, 350 .endianness = DEVICE_LITTLE_ENDIAN, 351 .valid.min_access_size = 4, 352 .valid.max_access_size = 4, 353 .valid.unaligned = false, 354 }; 355 356 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) 357 { 358 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) { 359 return 25000000; 360 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { 361 return 48000000; 362 } else { 363 return 24000000; 364 } 365 } 366 367 /* 368 * Strapped frequencies for the AST2400 in MHz. They depend on the 369 * clkin frequency. 370 */ 371 static const uint32_t hpll_ast2400_freqs[][4] = { 372 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ 373 { 400, 375, 350, 425 }, /* 25MHz */ 374 }; 375 376 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 377 { 378 uint8_t freq_select; 379 bool clk_25m_in; 380 uint32_t clkin = aspeed_scu_get_clkin(s); 381 382 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { 383 return 0; 384 } 385 386 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { 387 uint32_t multiplier = 1; 388 389 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { 390 uint32_t n = (hpll_reg >> 5) & 0x3f; 391 uint32_t od = (hpll_reg >> 4) & 0x1; 392 uint32_t d = hpll_reg & 0xf; 393 394 multiplier = (2 - od) * ((n + 2) / (d + 1)); 395 } 396 397 return clkin * multiplier; 398 } 399 400 /* HW strapping */ 401 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); 402 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); 403 404 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; 405 } 406 407 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 408 { 409 uint32_t multiplier = 1; 410 uint32_t clkin = aspeed_scu_get_clkin(s); 411 412 if (hpll_reg & SCU_H_PLL_OFF) { 413 return 0; 414 } 415 416 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { 417 uint32_t p = (hpll_reg >> 13) & 0x3f; 418 uint32_t m = (hpll_reg >> 5) & 0xff; 419 uint32_t n = hpll_reg & 0x1f; 420 421 multiplier = ((m + 1) / (n + 1)) / (p + 1); 422 } 423 424 return clkin * multiplier; 425 } 426 427 static void aspeed_scu_reset(DeviceState *dev) 428 { 429 AspeedSCUState *s = ASPEED_SCU(dev); 430 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 431 432 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 433 s->regs[SILICON_REV] = s->silicon_rev; 434 s->regs[HW_STRAP1] = s->hw_strap1; 435 s->regs[HW_STRAP2] = s->hw_strap2; 436 s->regs[PROT_KEY] = s->hw_prot_key; 437 } 438 439 static uint32_t aspeed_silicon_revs[] = { 440 AST2400_A0_SILICON_REV, 441 AST2400_A1_SILICON_REV, 442 AST2500_A0_SILICON_REV, 443 AST2500_A1_SILICON_REV, 444 AST2600_A0_SILICON_REV, 445 AST2600_A1_SILICON_REV, 446 AST2600_A2_SILICON_REV, 447 AST2600_A3_SILICON_REV, 448 }; 449 450 bool is_supported_silicon_rev(uint32_t silicon_rev) 451 { 452 int i; 453 454 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 455 if (silicon_rev == aspeed_silicon_revs[i]) { 456 return true; 457 } 458 } 459 460 return false; 461 } 462 463 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 464 { 465 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 466 AspeedSCUState *s = ASPEED_SCU(dev); 467 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 468 469 if (!is_supported_silicon_rev(s->silicon_rev)) { 470 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 471 s->silicon_rev); 472 return; 473 } 474 475 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, 476 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 477 478 sysbus_init_mmio(sbd, &s->iomem); 479 } 480 481 static const VMStateDescription vmstate_aspeed_scu = { 482 .name = "aspeed.scu", 483 .version_id = 2, 484 .minimum_version_id = 2, 485 .fields = (VMStateField[]) { 486 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), 487 VMSTATE_END_OF_LIST() 488 } 489 }; 490 491 static Property aspeed_scu_properties[] = { 492 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 493 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 494 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 495 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), 496 DEFINE_PROP_END_OF_LIST(), 497 }; 498 499 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 500 { 501 DeviceClass *dc = DEVICE_CLASS(klass); 502 dc->realize = aspeed_scu_realize; 503 dc->reset = aspeed_scu_reset; 504 dc->desc = "ASPEED System Control Unit"; 505 dc->vmsd = &vmstate_aspeed_scu; 506 device_class_set_props(dc, aspeed_scu_properties); 507 } 508 509 static const TypeInfo aspeed_scu_info = { 510 .name = TYPE_ASPEED_SCU, 511 .parent = TYPE_SYS_BUS_DEVICE, 512 .instance_size = sizeof(AspeedSCUState), 513 .class_init = aspeed_scu_class_init, 514 .class_size = sizeof(AspeedSCUClass), 515 .abstract = true, 516 }; 517 518 static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) 519 { 520 DeviceClass *dc = DEVICE_CLASS(klass); 521 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 522 523 dc->desc = "ASPEED 2400 System Control Unit"; 524 asc->resets = ast2400_a0_resets; 525 asc->calc_hpll = aspeed_2400_scu_calc_hpll; 526 asc->apb_divider = 2; 527 asc->nr_regs = ASPEED_SCU_NR_REGS; 528 asc->ops = &aspeed_ast2400_scu_ops; 529 } 530 531 static const TypeInfo aspeed_2400_scu_info = { 532 .name = TYPE_ASPEED_2400_SCU, 533 .parent = TYPE_ASPEED_SCU, 534 .instance_size = sizeof(AspeedSCUState), 535 .class_init = aspeed_2400_scu_class_init, 536 }; 537 538 static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 542 543 dc->desc = "ASPEED 2500 System Control Unit"; 544 asc->resets = ast2500_a1_resets; 545 asc->calc_hpll = aspeed_2500_scu_calc_hpll; 546 asc->apb_divider = 4; 547 asc->nr_regs = ASPEED_SCU_NR_REGS; 548 asc->ops = &aspeed_ast2500_scu_ops; 549 } 550 551 static const TypeInfo aspeed_2500_scu_info = { 552 .name = TYPE_ASPEED_2500_SCU, 553 .parent = TYPE_ASPEED_SCU, 554 .instance_size = sizeof(AspeedSCUState), 555 .class_init = aspeed_2500_scu_class_init, 556 }; 557 558 static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, 559 unsigned size) 560 { 561 AspeedSCUState *s = ASPEED_SCU(opaque); 562 int reg = TO_REG(offset); 563 564 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 565 qemu_log_mask(LOG_GUEST_ERROR, 566 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 567 __func__, offset); 568 return 0; 569 } 570 571 switch (reg) { 572 case AST2600_HPLL_EXT: 573 case AST2600_EPLL_EXT: 574 case AST2600_MPLL_EXT: 575 /* PLLs are always "locked" */ 576 return s->regs[reg] | BIT(31); 577 case AST2600_RNG_DATA: 578 /* 579 * On hardware, RNG_DATA works regardless of the state of the 580 * enable bit in RNG_CTRL 581 * 582 * TODO: Check this is true for ast2600 583 */ 584 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); 585 break; 586 } 587 588 return s->regs[reg]; 589 } 590 591 static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, 592 uint64_t data64, unsigned size) 593 { 594 AspeedSCUState *s = ASPEED_SCU(opaque); 595 int reg = TO_REG(offset); 596 /* Truncate here so bitwise operations below behave as expected */ 597 uint32_t data = data64; 598 599 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 600 qemu_log_mask(LOG_GUEST_ERROR, 601 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 602 __func__, offset); 603 return; 604 } 605 606 if (reg > PROT_KEY && !s->regs[PROT_KEY]) { 607 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 608 } 609 610 trace_aspeed_scu_write(offset, size, data); 611 612 switch (reg) { 613 case AST2600_PROT_KEY: 614 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 615 return; 616 case AST2600_HW_STRAP1: 617 case AST2600_HW_STRAP2: 618 if (s->regs[reg + 2]) { 619 return; 620 } 621 /* fall through */ 622 case AST2600_SYS_RST_CTRL: 623 case AST2600_SYS_RST_CTRL2: 624 case AST2600_CLK_STOP_CTRL: 625 case AST2600_CLK_STOP_CTRL2: 626 /* W1S (Write 1 to set) registers */ 627 s->regs[reg] |= data; 628 return; 629 case AST2600_SYS_RST_CTRL_CLR: 630 case AST2600_SYS_RST_CTRL2_CLR: 631 case AST2600_CLK_STOP_CTRL_CLR: 632 case AST2600_CLK_STOP_CTRL2_CLR: 633 case AST2600_HW_STRAP1_CLR: 634 case AST2600_HW_STRAP2_CLR: 635 /* 636 * W1C (Write 1 to clear) registers are offset by one address from 637 * the data register 638 */ 639 s->regs[reg - 1] &= ~data; 640 return; 641 642 case AST2600_RNG_DATA: 643 case AST2600_SILICON_REV: 644 case AST2600_SILICON_REV2: 645 case AST2600_CHIP_ID0: 646 case AST2600_CHIP_ID1: 647 /* Add read only registers here */ 648 qemu_log_mask(LOG_GUEST_ERROR, 649 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 650 __func__, offset); 651 return; 652 } 653 654 s->regs[reg] = data; 655 } 656 657 static const MemoryRegionOps aspeed_ast2600_scu_ops = { 658 .read = aspeed_ast2600_scu_read, 659 .write = aspeed_ast2600_scu_write, 660 .endianness = DEVICE_LITTLE_ENDIAN, 661 .valid.min_access_size = 4, 662 .valid.max_access_size = 4, 663 .valid.unaligned = false, 664 }; 665 666 static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { 667 [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, 668 [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, 669 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, 670 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, 671 [AST2600_DEBUG_CTRL] = 0x00000FFF, 672 [AST2600_DEBUG_CTRL2] = 0x000000FF, 673 [AST2600_SDRAM_HANDSHAKE] = 0x00000000, 674 [AST2600_HPLL_PARAM] = 0x1000408F, 675 [AST2600_APLL_PARAM] = 0x1000405F, 676 [AST2600_MPLL_PARAM] = 0x1008405F, 677 [AST2600_EPLL_PARAM] = 0x1004077F, 678 [AST2600_DPLL_PARAM] = 0x1078405F, 679 [AST2600_CLK_SEL] = 0xF3940000, 680 [AST2600_CLK_SEL2] = 0x00700000, 681 [AST2600_CLK_SEL3] = 0x00000000, 682 [AST2600_CLK_SEL4] = 0xF3F40000, 683 [AST2600_CLK_SEL5] = 0x30000000, 684 [AST2600_CHIP_ID0] = 0x1234ABCD, 685 [AST2600_CHIP_ID1] = 0x88884444, 686 }; 687 688 static void aspeed_ast2600_scu_reset(DeviceState *dev) 689 { 690 AspeedSCUState *s = ASPEED_SCU(dev); 691 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 692 693 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 694 695 /* 696 * A0 reports A0 in _REV, but subsequent revisions report A1 regardless 697 * of actual revision. QEMU and Linux only support A1 onwards so this is 698 * sufficient. 699 */ 700 s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; 701 s->regs[AST2600_SILICON_REV2] = s->silicon_rev; 702 s->regs[AST2600_HW_STRAP1] = s->hw_strap1; 703 s->regs[AST2600_HW_STRAP2] = s->hw_strap2; 704 s->regs[PROT_KEY] = s->hw_prot_key; 705 } 706 707 static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) 708 { 709 DeviceClass *dc = DEVICE_CLASS(klass); 710 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 711 712 dc->desc = "ASPEED 2600 System Control Unit"; 713 dc->reset = aspeed_ast2600_scu_reset; 714 asc->resets = ast2600_a3_resets; 715 asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ 716 asc->apb_divider = 4; 717 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; 718 asc->ops = &aspeed_ast2600_scu_ops; 719 } 720 721 static const TypeInfo aspeed_2600_scu_info = { 722 .name = TYPE_ASPEED_2600_SCU, 723 .parent = TYPE_ASPEED_SCU, 724 .instance_size = sizeof(AspeedSCUState), 725 .class_init = aspeed_2600_scu_class_init, 726 }; 727 728 static void aspeed_scu_register_types(void) 729 { 730 type_register_static(&aspeed_scu_info); 731 type_register_static(&aspeed_2400_scu_info); 732 type_register_static(&aspeed_2500_scu_info); 733 type_register_static(&aspeed_2600_scu_info); 734 } 735 736 type_init(aspeed_scu_register_types); 737