1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "migration/vmstate.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "qemu/bitops.h" 19 #include "qemu/log.h" 20 #include "qemu/guest-random.h" 21 #include "qemu/module.h" 22 #include "trace.h" 23 24 #define TO_REG(offset) ((offset) >> 2) 25 26 #define PROT_KEY TO_REG(0x00) 27 #define SYS_RST_CTRL TO_REG(0x04) 28 #define CLK_SEL TO_REG(0x08) 29 #define CLK_STOP_CTRL TO_REG(0x0C) 30 #define FREQ_CNTR_CTRL TO_REG(0x10) 31 #define FREQ_CNTR_EVAL TO_REG(0x14) 32 #define IRQ_CTRL TO_REG(0x18) 33 #define D2PLL_PARAM TO_REG(0x1C) 34 #define MPLL_PARAM TO_REG(0x20) 35 #define HPLL_PARAM TO_REG(0x24) 36 #define FREQ_CNTR_RANGE TO_REG(0x28) 37 #define MISC_CTRL1 TO_REG(0x2C) 38 #define PCI_CTRL1 TO_REG(0x30) 39 #define PCI_CTRL2 TO_REG(0x34) 40 #define PCI_CTRL3 TO_REG(0x38) 41 #define SYS_RST_STATUS TO_REG(0x3C) 42 #define SOC_SCRATCH1 TO_REG(0x40) 43 #define SOC_SCRATCH2 TO_REG(0x44) 44 #define MAC_CLK_DELAY TO_REG(0x48) 45 #define MISC_CTRL2 TO_REG(0x4C) 46 #define VGA_SCRATCH1 TO_REG(0x50) 47 #define VGA_SCRATCH2 TO_REG(0x54) 48 #define VGA_SCRATCH3 TO_REG(0x58) 49 #define VGA_SCRATCH4 TO_REG(0x5C) 50 #define VGA_SCRATCH5 TO_REG(0x60) 51 #define VGA_SCRATCH6 TO_REG(0x64) 52 #define VGA_SCRATCH7 TO_REG(0x68) 53 #define VGA_SCRATCH8 TO_REG(0x6C) 54 #define HW_STRAP1 TO_REG(0x70) 55 #define RNG_CTRL TO_REG(0x74) 56 #define RNG_DATA TO_REG(0x78) 57 #define SILICON_REV TO_REG(0x7C) 58 #define PINMUX_CTRL1 TO_REG(0x80) 59 #define PINMUX_CTRL2 TO_REG(0x84) 60 #define PINMUX_CTRL3 TO_REG(0x88) 61 #define PINMUX_CTRL4 TO_REG(0x8C) 62 #define PINMUX_CTRL5 TO_REG(0x90) 63 #define PINMUX_CTRL6 TO_REG(0x94) 64 #define WDT_RST_CTRL TO_REG(0x9C) 65 #define PINMUX_CTRL7 TO_REG(0xA0) 66 #define PINMUX_CTRL8 TO_REG(0xA4) 67 #define PINMUX_CTRL9 TO_REG(0xA8) 68 #define WAKEUP_EN TO_REG(0xC0) 69 #define WAKEUP_CTRL TO_REG(0xC4) 70 #define HW_STRAP2 TO_REG(0xD0) 71 #define FREE_CNTR4 TO_REG(0xE0) 72 #define FREE_CNTR4_EXT TO_REG(0xE4) 73 #define CPU2_CTRL TO_REG(0x100) 74 #define CPU2_BASE_SEG1 TO_REG(0x104) 75 #define CPU2_BASE_SEG2 TO_REG(0x108) 76 #define CPU2_BASE_SEG3 TO_REG(0x10C) 77 #define CPU2_BASE_SEG4 TO_REG(0x110) 78 #define CPU2_BASE_SEG5 TO_REG(0x114) 79 #define CPU2_CACHE_CTRL TO_REG(0x118) 80 #define CHIP_ID0 TO_REG(0x150) 81 #define CHIP_ID1 TO_REG(0x154) 82 #define UART_HPLL_CLK TO_REG(0x160) 83 #define PCIE_CTRL TO_REG(0x180) 84 #define BMC_MMIO_CTRL TO_REG(0x184) 85 #define RELOC_DECODE_BASE1 TO_REG(0x188) 86 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 87 #define MAILBOX_DECODE_BASE TO_REG(0x190) 88 #define SRAM_DECODE_BASE1 TO_REG(0x194) 89 #define SRAM_DECODE_BASE2 TO_REG(0x198) 90 #define BMC_REV TO_REG(0x19C) 91 #define BMC_DEV_ID TO_REG(0x1A4) 92 93 #define AST2600_PROT_KEY TO_REG(0x00) 94 #define AST2600_SILICON_REV TO_REG(0x04) 95 #define AST2600_SILICON_REV2 TO_REG(0x14) 96 #define AST2600_SYS_RST_CTRL TO_REG(0x40) 97 #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) 98 #define AST2600_SYS_RST_CTRL2 TO_REG(0x50) 99 #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) 100 #define AST2600_CLK_STOP_CTRL TO_REG(0x80) 101 #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) 102 #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) 103 #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) 104 #define AST2600_DEBUG_CTRL TO_REG(0xC8) 105 #define AST2600_DEBUG_CTRL2 TO_REG(0xD8) 106 #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) 107 #define AST2600_HPLL_PARAM TO_REG(0x200) 108 #define AST2600_HPLL_EXT TO_REG(0x204) 109 #define AST2600_APLL_PARAM TO_REG(0x210) 110 #define AST2600_APLL_EXT TO_REG(0x214) 111 #define AST2600_MPLL_PARAM TO_REG(0x220) 112 #define AST2600_MPLL_EXT TO_REG(0x224) 113 #define AST2600_EPLL_PARAM TO_REG(0x240) 114 #define AST2600_EPLL_EXT TO_REG(0x244) 115 #define AST2600_DPLL_PARAM TO_REG(0x260) 116 #define AST2600_DPLL_EXT TO_REG(0x264) 117 #define AST2600_CLK_SEL TO_REG(0x300) 118 #define AST2600_CLK_SEL2 TO_REG(0x304) 119 #define AST2600_CLK_SEL3 TO_REG(0x308) 120 #define AST2600_CLK_SEL4 TO_REG(0x310) 121 #define AST2600_CLK_SEL5 TO_REG(0x314) 122 #define AST2600_UARTCLK TO_REG(0x338) 123 #define AST2600_HUARTCLK TO_REG(0x33C) 124 #define AST2600_HW_STRAP1 TO_REG(0x500) 125 #define AST2600_HW_STRAP1_CLR TO_REG(0x504) 126 #define AST2600_HW_STRAP1_PROT TO_REG(0x508) 127 #define AST2600_HW_STRAP2 TO_REG(0x510) 128 #define AST2600_HW_STRAP2_CLR TO_REG(0x514) 129 #define AST2600_HW_STRAP2_PROT TO_REG(0x518) 130 #define AST2600_RNG_CTRL TO_REG(0x524) 131 #define AST2600_RNG_DATA TO_REG(0x540) 132 #define AST2600_CHIP_ID0 TO_REG(0x5B0) 133 #define AST2600_CHIP_ID1 TO_REG(0x5B4) 134 135 #define AST2600_CLK TO_REG(0x40) 136 137 #define SCU_IO_REGION_SIZE 0x1000 138 139 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 140 [SYS_RST_CTRL] = 0xFFCFFEDCU, 141 [CLK_SEL] = 0xF3F40000U, 142 [CLK_STOP_CTRL] = 0x19FC3E8BU, 143 [D2PLL_PARAM] = 0x00026108U, 144 [MPLL_PARAM] = 0x00030291U, 145 [HPLL_PARAM] = 0x00000291U, 146 [MISC_CTRL1] = 0x00000010U, 147 [PCI_CTRL1] = 0x20001A03U, 148 [PCI_CTRL2] = 0x20001A03U, 149 [PCI_CTRL3] = 0x04000030U, 150 [SYS_RST_STATUS] = 0x00000001U, 151 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 152 [MISC_CTRL2] = 0x00000023U, 153 [RNG_CTRL] = 0x0000000EU, 154 [PINMUX_CTRL2] = 0x0000F000U, 155 [PINMUX_CTRL3] = 0x01000000U, 156 [PINMUX_CTRL4] = 0x000000FFU, 157 [PINMUX_CTRL5] = 0x0000A000U, 158 [WDT_RST_CTRL] = 0x003FFFF3U, 159 [PINMUX_CTRL8] = 0xFFFF0000U, 160 [PINMUX_CTRL9] = 0x000FFFFFU, 161 [FREE_CNTR4] = 0x000000FFU, 162 [FREE_CNTR4_EXT] = 0x000000FFU, 163 [CPU2_BASE_SEG1] = 0x80000000U, 164 [CPU2_BASE_SEG4] = 0x1E600000U, 165 [CPU2_BASE_SEG5] = 0xC0000000U, 166 [UART_HPLL_CLK] = 0x00001903U, 167 [PCIE_CTRL] = 0x0000007BU, 168 [BMC_DEV_ID] = 0x00002402U 169 }; 170 171 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 172 /* AST2500 revision A1 */ 173 174 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 175 [SYS_RST_CTRL] = 0xFFCFFEDCU, 176 [CLK_SEL] = 0xF3F40000U, 177 [CLK_STOP_CTRL] = 0x19FC3E8BU, 178 [D2PLL_PARAM] = 0x00026108U, 179 [MPLL_PARAM] = 0x00030291U, 180 [HPLL_PARAM] = 0x93000400U, 181 [MISC_CTRL1] = 0x00000010U, 182 [PCI_CTRL1] = 0x20001A03U, 183 [PCI_CTRL2] = 0x20001A03U, 184 [PCI_CTRL3] = 0x04000030U, 185 [SYS_RST_STATUS] = 0x00000001U, 186 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 187 [MISC_CTRL2] = 0x00000023U, 188 [RNG_CTRL] = 0x0000000EU, 189 [PINMUX_CTRL2] = 0x0000F000U, 190 [PINMUX_CTRL3] = 0x03000000U, 191 [PINMUX_CTRL4] = 0x00000000U, 192 [PINMUX_CTRL5] = 0x0000A000U, 193 [WDT_RST_CTRL] = 0x023FFFF3U, 194 [PINMUX_CTRL8] = 0xFFFF0000U, 195 [PINMUX_CTRL9] = 0x000FFFFFU, 196 [FREE_CNTR4] = 0x000000FFU, 197 [FREE_CNTR4_EXT] = 0x000000FFU, 198 [CPU2_BASE_SEG1] = 0x80000000U, 199 [CPU2_BASE_SEG4] = 0x1E600000U, 200 [CPU2_BASE_SEG5] = 0xC0000000U, 201 [CHIP_ID0] = 0x1234ABCDU, 202 [CHIP_ID1] = 0x88884444U, 203 [UART_HPLL_CLK] = 0x00001903U, 204 [PCIE_CTRL] = 0x0000007BU, 205 [BMC_DEV_ID] = 0x00002402U 206 }; 207 208 static uint32_t aspeed_scu_get_random(void) 209 { 210 uint32_t num; 211 qemu_guest_getrandom_nofail(&num, sizeof(num)); 212 return num; 213 } 214 215 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) 216 { 217 return ASPEED_SCU_GET_CLASS(s)->get_apb(s); 218 } 219 220 static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s) 221 { 222 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 223 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); 224 225 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) 226 / asc->apb_divider; 227 } 228 229 static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s) 230 { 231 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 232 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); 233 234 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1) 235 / asc->apb_divider; 236 } 237 238 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 239 { 240 AspeedSCUState *s = ASPEED_SCU(opaque); 241 int reg = TO_REG(offset); 242 243 if (reg >= ASPEED_SCU_NR_REGS) { 244 qemu_log_mask(LOG_GUEST_ERROR, 245 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 246 __func__, offset); 247 return 0; 248 } 249 250 switch (reg) { 251 case RNG_DATA: 252 /* On hardware, RNG_DATA works regardless of 253 * the state of the enable bit in RNG_CTRL 254 */ 255 s->regs[RNG_DATA] = aspeed_scu_get_random(); 256 break; 257 case WAKEUP_EN: 258 qemu_log_mask(LOG_GUEST_ERROR, 259 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 260 __func__, offset); 261 break; 262 } 263 264 return s->regs[reg]; 265 } 266 267 static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, 268 uint64_t data, unsigned size) 269 { 270 AspeedSCUState *s = ASPEED_SCU(opaque); 271 int reg = TO_REG(offset); 272 273 if (reg >= ASPEED_SCU_NR_REGS) { 274 qemu_log_mask(LOG_GUEST_ERROR, 275 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 276 __func__, offset); 277 return; 278 } 279 280 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 281 !s->regs[PROT_KEY]) { 282 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 283 } 284 285 trace_aspeed_scu_write(offset, size, data); 286 287 switch (reg) { 288 case PROT_KEY: 289 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 290 return; 291 case SILICON_REV: 292 case FREQ_CNTR_EVAL: 293 case VGA_SCRATCH1 ... VGA_SCRATCH8: 294 case RNG_DATA: 295 case FREE_CNTR4: 296 case FREE_CNTR4_EXT: 297 qemu_log_mask(LOG_GUEST_ERROR, 298 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 299 __func__, offset); 300 return; 301 } 302 303 s->regs[reg] = data; 304 } 305 306 static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, 307 uint64_t data, unsigned size) 308 { 309 AspeedSCUState *s = ASPEED_SCU(opaque); 310 int reg = TO_REG(offset); 311 312 if (reg >= ASPEED_SCU_NR_REGS) { 313 qemu_log_mask(LOG_GUEST_ERROR, 314 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 315 __func__, offset); 316 return; 317 } 318 319 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 320 !s->regs[PROT_KEY]) { 321 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 322 return; 323 } 324 325 trace_aspeed_scu_write(offset, size, data); 326 327 switch (reg) { 328 case PROT_KEY: 329 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 330 return; 331 case HW_STRAP1: 332 s->regs[HW_STRAP1] |= data; 333 return; 334 case SILICON_REV: 335 s->regs[HW_STRAP1] &= ~data; 336 return; 337 case FREQ_CNTR_EVAL: 338 case VGA_SCRATCH1 ... VGA_SCRATCH8: 339 case RNG_DATA: 340 case FREE_CNTR4: 341 case FREE_CNTR4_EXT: 342 case CHIP_ID0: 343 case CHIP_ID1: 344 qemu_log_mask(LOG_GUEST_ERROR, 345 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 346 __func__, offset); 347 return; 348 } 349 350 s->regs[reg] = data; 351 } 352 353 static const MemoryRegionOps aspeed_ast2400_scu_ops = { 354 .read = aspeed_scu_read, 355 .write = aspeed_ast2400_scu_write, 356 .endianness = DEVICE_LITTLE_ENDIAN, 357 .valid = { 358 .min_access_size = 1, 359 .max_access_size = 4, 360 }, 361 }; 362 363 static const MemoryRegionOps aspeed_ast2500_scu_ops = { 364 .read = aspeed_scu_read, 365 .write = aspeed_ast2500_scu_write, 366 .endianness = DEVICE_LITTLE_ENDIAN, 367 .valid.min_access_size = 4, 368 .valid.max_access_size = 4, 369 .valid.unaligned = false, 370 }; 371 372 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) 373 { 374 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN || 375 ASPEED_SCU_GET_CLASS(s)->clkin_25Mhz) { 376 return 25000000; 377 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { 378 return 48000000; 379 } else { 380 return 24000000; 381 } 382 } 383 384 /* 385 * Strapped frequencies for the AST2400 in MHz. They depend on the 386 * clkin frequency. 387 */ 388 static const uint32_t hpll_ast2400_freqs[][4] = { 389 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ 390 { 400, 375, 350, 425 }, /* 25MHz */ 391 }; 392 393 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 394 { 395 uint8_t freq_select; 396 bool clk_25m_in; 397 uint32_t clkin = aspeed_scu_get_clkin(s); 398 399 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { 400 return 0; 401 } 402 403 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { 404 uint32_t multiplier = 1; 405 406 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { 407 uint32_t n = (hpll_reg >> 5) & 0x3f; 408 uint32_t od = (hpll_reg >> 4) & 0x1; 409 uint32_t d = hpll_reg & 0xf; 410 411 multiplier = (2 - od) * ((n + 2) / (d + 1)); 412 } 413 414 return clkin * multiplier; 415 } 416 417 /* HW strapping */ 418 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); 419 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); 420 421 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; 422 } 423 424 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 425 { 426 uint32_t multiplier = 1; 427 uint32_t clkin = aspeed_scu_get_clkin(s); 428 429 if (hpll_reg & SCU_H_PLL_OFF) { 430 return 0; 431 } 432 433 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { 434 uint32_t p = (hpll_reg >> 13) & 0x3f; 435 uint32_t m = (hpll_reg >> 5) & 0xff; 436 uint32_t n = hpll_reg & 0x1f; 437 438 multiplier = ((m + 1) / (n + 1)) / (p + 1); 439 } 440 441 return clkin * multiplier; 442 } 443 444 static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 445 { 446 uint32_t multiplier = 1; 447 uint32_t clkin = aspeed_scu_get_clkin(s); 448 449 if (hpll_reg & SCU_AST2600_H_PLL_OFF) { 450 return 0; 451 } 452 453 if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) { 454 uint32_t p = (hpll_reg >> 19) & 0xf; 455 uint32_t n = (hpll_reg >> 13) & 0x3f; 456 uint32_t m = hpll_reg & 0x1fff; 457 458 multiplier = ((m + 1) / (n + 1)) / (p + 1); 459 } 460 461 return clkin * multiplier; 462 } 463 464 static void aspeed_scu_reset(DeviceState *dev) 465 { 466 AspeedSCUState *s = ASPEED_SCU(dev); 467 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 468 469 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 470 s->regs[SILICON_REV] = s->silicon_rev; 471 s->regs[HW_STRAP1] = s->hw_strap1; 472 s->regs[HW_STRAP2] = s->hw_strap2; 473 s->regs[PROT_KEY] = s->hw_prot_key; 474 } 475 476 static uint32_t aspeed_silicon_revs[] = { 477 AST2400_A0_SILICON_REV, 478 AST2400_A1_SILICON_REV, 479 AST2500_A0_SILICON_REV, 480 AST2500_A1_SILICON_REV, 481 AST2600_A0_SILICON_REV, 482 AST2600_A1_SILICON_REV, 483 AST2600_A2_SILICON_REV, 484 AST2600_A3_SILICON_REV, 485 }; 486 487 bool is_supported_silicon_rev(uint32_t silicon_rev) 488 { 489 int i; 490 491 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 492 if (silicon_rev == aspeed_silicon_revs[i]) { 493 return true; 494 } 495 } 496 497 return false; 498 } 499 500 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 501 { 502 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 503 AspeedSCUState *s = ASPEED_SCU(dev); 504 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 505 506 if (!is_supported_silicon_rev(s->silicon_rev)) { 507 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 508 s->silicon_rev); 509 return; 510 } 511 512 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, 513 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 514 515 sysbus_init_mmio(sbd, &s->iomem); 516 } 517 518 static const VMStateDescription vmstate_aspeed_scu = { 519 .name = "aspeed.scu", 520 .version_id = 2, 521 .minimum_version_id = 2, 522 .fields = (VMStateField[]) { 523 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), 524 VMSTATE_END_OF_LIST() 525 } 526 }; 527 528 static Property aspeed_scu_properties[] = { 529 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 530 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 531 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 532 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), 533 DEFINE_PROP_END_OF_LIST(), 534 }; 535 536 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 537 { 538 DeviceClass *dc = DEVICE_CLASS(klass); 539 dc->realize = aspeed_scu_realize; 540 dc->reset = aspeed_scu_reset; 541 dc->desc = "ASPEED System Control Unit"; 542 dc->vmsd = &vmstate_aspeed_scu; 543 device_class_set_props(dc, aspeed_scu_properties); 544 } 545 546 static const TypeInfo aspeed_scu_info = { 547 .name = TYPE_ASPEED_SCU, 548 .parent = TYPE_SYS_BUS_DEVICE, 549 .instance_size = sizeof(AspeedSCUState), 550 .class_init = aspeed_scu_class_init, 551 .class_size = sizeof(AspeedSCUClass), 552 .abstract = true, 553 }; 554 555 static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) 556 { 557 DeviceClass *dc = DEVICE_CLASS(klass); 558 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 559 560 dc->desc = "ASPEED 2400 System Control Unit"; 561 asc->resets = ast2400_a0_resets; 562 asc->calc_hpll = aspeed_2400_scu_calc_hpll; 563 asc->get_apb = aspeed_2400_scu_get_apb_freq; 564 asc->apb_divider = 2; 565 asc->nr_regs = ASPEED_SCU_NR_REGS; 566 asc->clkin_25Mhz = false; 567 asc->ops = &aspeed_ast2400_scu_ops; 568 } 569 570 static const TypeInfo aspeed_2400_scu_info = { 571 .name = TYPE_ASPEED_2400_SCU, 572 .parent = TYPE_ASPEED_SCU, 573 .instance_size = sizeof(AspeedSCUState), 574 .class_init = aspeed_2400_scu_class_init, 575 }; 576 577 static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) 578 { 579 DeviceClass *dc = DEVICE_CLASS(klass); 580 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 581 582 dc->desc = "ASPEED 2500 System Control Unit"; 583 asc->resets = ast2500_a1_resets; 584 asc->calc_hpll = aspeed_2500_scu_calc_hpll; 585 asc->get_apb = aspeed_2400_scu_get_apb_freq; 586 asc->apb_divider = 4; 587 asc->nr_regs = ASPEED_SCU_NR_REGS; 588 asc->clkin_25Mhz = false; 589 asc->ops = &aspeed_ast2500_scu_ops; 590 } 591 592 static const TypeInfo aspeed_2500_scu_info = { 593 .name = TYPE_ASPEED_2500_SCU, 594 .parent = TYPE_ASPEED_SCU, 595 .instance_size = sizeof(AspeedSCUState), 596 .class_init = aspeed_2500_scu_class_init, 597 }; 598 599 static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, 600 unsigned size) 601 { 602 AspeedSCUState *s = ASPEED_SCU(opaque); 603 int reg = TO_REG(offset); 604 605 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 606 qemu_log_mask(LOG_GUEST_ERROR, 607 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 608 __func__, offset); 609 return 0; 610 } 611 612 switch (reg) { 613 case AST2600_HPLL_EXT: 614 case AST2600_EPLL_EXT: 615 case AST2600_MPLL_EXT: 616 /* PLLs are always "locked" */ 617 return s->regs[reg] | BIT(31); 618 case AST2600_RNG_DATA: 619 /* 620 * On hardware, RNG_DATA works regardless of the state of the 621 * enable bit in RNG_CTRL 622 * 623 * TODO: Check this is true for ast2600 624 */ 625 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); 626 break; 627 } 628 629 return s->regs[reg]; 630 } 631 632 static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, 633 uint64_t data64, unsigned size) 634 { 635 AspeedSCUState *s = ASPEED_SCU(opaque); 636 int reg = TO_REG(offset); 637 /* Truncate here so bitwise operations below behave as expected */ 638 uint32_t data = data64; 639 640 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 641 qemu_log_mask(LOG_GUEST_ERROR, 642 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 643 __func__, offset); 644 return; 645 } 646 647 if (reg > PROT_KEY && !s->regs[PROT_KEY]) { 648 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 649 } 650 651 trace_aspeed_scu_write(offset, size, data); 652 653 switch (reg) { 654 case AST2600_PROT_KEY: 655 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 656 return; 657 case AST2600_HW_STRAP1: 658 case AST2600_HW_STRAP2: 659 if (s->regs[reg + 2]) { 660 return; 661 } 662 /* fall through */ 663 case AST2600_SYS_RST_CTRL: 664 case AST2600_SYS_RST_CTRL2: 665 case AST2600_CLK_STOP_CTRL: 666 case AST2600_CLK_STOP_CTRL2: 667 /* W1S (Write 1 to set) registers */ 668 s->regs[reg] |= data; 669 return; 670 case AST2600_SYS_RST_CTRL_CLR: 671 case AST2600_SYS_RST_CTRL2_CLR: 672 case AST2600_CLK_STOP_CTRL_CLR: 673 case AST2600_CLK_STOP_CTRL2_CLR: 674 case AST2600_HW_STRAP1_CLR: 675 case AST2600_HW_STRAP2_CLR: 676 /* 677 * W1C (Write 1 to clear) registers are offset by one address from 678 * the data register 679 */ 680 s->regs[reg - 1] &= ~data; 681 return; 682 683 case AST2600_RNG_DATA: 684 case AST2600_SILICON_REV: 685 case AST2600_SILICON_REV2: 686 case AST2600_CHIP_ID0: 687 case AST2600_CHIP_ID1: 688 /* Add read only registers here */ 689 qemu_log_mask(LOG_GUEST_ERROR, 690 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 691 __func__, offset); 692 return; 693 } 694 695 s->regs[reg] = data; 696 } 697 698 static const MemoryRegionOps aspeed_ast2600_scu_ops = { 699 .read = aspeed_ast2600_scu_read, 700 .write = aspeed_ast2600_scu_write, 701 .endianness = DEVICE_LITTLE_ENDIAN, 702 .valid.min_access_size = 4, 703 .valid.max_access_size = 4, 704 .valid.unaligned = false, 705 }; 706 707 static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { 708 [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, 709 [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, 710 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, 711 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, 712 [AST2600_DEBUG_CTRL] = 0x00000FFF, 713 [AST2600_DEBUG_CTRL2] = 0x000000FF, 714 [AST2600_SDRAM_HANDSHAKE] = 0x00000000, 715 [AST2600_HPLL_PARAM] = 0x1000408F, 716 [AST2600_APLL_PARAM] = 0x1000405F, 717 [AST2600_MPLL_PARAM] = 0x1008405F, 718 [AST2600_EPLL_PARAM] = 0x1004077F, 719 [AST2600_DPLL_PARAM] = 0x1078405F, 720 [AST2600_CLK_SEL] = 0xF3940000, 721 [AST2600_CLK_SEL2] = 0x00700000, 722 [AST2600_CLK_SEL3] = 0x00000000, 723 [AST2600_CLK_SEL4] = 0xF3F40000, 724 [AST2600_CLK_SEL5] = 0x30000000, 725 [AST2600_UARTCLK] = 0x00014506, 726 [AST2600_HUARTCLK] = 0x000145C0, 727 [AST2600_CHIP_ID0] = 0x1234ABCD, 728 [AST2600_CHIP_ID1] = 0x88884444, 729 }; 730 731 static void aspeed_ast2600_scu_reset(DeviceState *dev) 732 { 733 AspeedSCUState *s = ASPEED_SCU(dev); 734 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 735 736 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 737 738 /* 739 * A0 reports A0 in _REV, but subsequent revisions report A1 regardless 740 * of actual revision. QEMU and Linux only support A1 onwards so this is 741 * sufficient. 742 */ 743 s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; 744 s->regs[AST2600_SILICON_REV2] = s->silicon_rev; 745 s->regs[AST2600_HW_STRAP1] = s->hw_strap1; 746 s->regs[AST2600_HW_STRAP2] = s->hw_strap2; 747 s->regs[PROT_KEY] = s->hw_prot_key; 748 } 749 750 static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) 751 { 752 DeviceClass *dc = DEVICE_CLASS(klass); 753 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 754 755 dc->desc = "ASPEED 2600 System Control Unit"; 756 dc->reset = aspeed_ast2600_scu_reset; 757 asc->resets = ast2600_a3_resets; 758 asc->calc_hpll = aspeed_2600_scu_calc_hpll; 759 asc->get_apb = aspeed_2600_scu_get_apb_freq; 760 asc->apb_divider = 4; 761 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; 762 asc->clkin_25Mhz = true; 763 asc->ops = &aspeed_ast2600_scu_ops; 764 } 765 766 static const TypeInfo aspeed_2600_scu_info = { 767 .name = TYPE_ASPEED_2600_SCU, 768 .parent = TYPE_ASPEED_SCU, 769 .instance_size = sizeof(AspeedSCUState), 770 .class_init = aspeed_2600_scu_class_init, 771 }; 772 773 static void aspeed_scu_register_types(void) 774 { 775 type_register_static(&aspeed_scu_info); 776 type_register_static(&aspeed_2400_scu_info); 777 type_register_static(&aspeed_2500_scu_info); 778 type_register_static(&aspeed_2600_scu_info); 779 } 780 781 type_init(aspeed_scu_register_types); 782