1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "qapi/error.h" 16 #include "qapi/visitor.h" 17 #include "qemu/bitops.h" 18 #include "qemu/log.h" 19 #include "trace.h" 20 21 #define TO_REG(offset) ((offset) >> 2) 22 23 #define PROT_KEY TO_REG(0x00) 24 #define SYS_RST_CTRL TO_REG(0x04) 25 #define CLK_SEL TO_REG(0x08) 26 #define CLK_STOP_CTRL TO_REG(0x0C) 27 #define FREQ_CNTR_CTRL TO_REG(0x10) 28 #define FREQ_CNTR_EVAL TO_REG(0x14) 29 #define IRQ_CTRL TO_REG(0x18) 30 #define D2PLL_PARAM TO_REG(0x1C) 31 #define MPLL_PARAM TO_REG(0x20) 32 #define HPLL_PARAM TO_REG(0x24) 33 #define FREQ_CNTR_RANGE TO_REG(0x28) 34 #define MISC_CTRL1 TO_REG(0x2C) 35 #define PCI_CTRL1 TO_REG(0x30) 36 #define PCI_CTRL2 TO_REG(0x34) 37 #define PCI_CTRL3 TO_REG(0x38) 38 #define SYS_RST_STATUS TO_REG(0x3C) 39 #define SOC_SCRATCH1 TO_REG(0x40) 40 #define SOC_SCRATCH2 TO_REG(0x44) 41 #define MAC_CLK_DELAY TO_REG(0x48) 42 #define MISC_CTRL2 TO_REG(0x4C) 43 #define VGA_SCRATCH1 TO_REG(0x50) 44 #define VGA_SCRATCH2 TO_REG(0x54) 45 #define VGA_SCRATCH3 TO_REG(0x58) 46 #define VGA_SCRATCH4 TO_REG(0x5C) 47 #define VGA_SCRATCH5 TO_REG(0x60) 48 #define VGA_SCRATCH6 TO_REG(0x64) 49 #define VGA_SCRATCH7 TO_REG(0x68) 50 #define VGA_SCRATCH8 TO_REG(0x6C) 51 #define HW_STRAP1 TO_REG(0x70) 52 #define RNG_CTRL TO_REG(0x74) 53 #define RNG_DATA TO_REG(0x78) 54 #define SILICON_REV TO_REG(0x7C) 55 #define PINMUX_CTRL1 TO_REG(0x80) 56 #define PINMUX_CTRL2 TO_REG(0x84) 57 #define PINMUX_CTRL3 TO_REG(0x88) 58 #define PINMUX_CTRL4 TO_REG(0x8C) 59 #define PINMUX_CTRL5 TO_REG(0x90) 60 #define PINMUX_CTRL6 TO_REG(0x94) 61 #define WDT_RST_CTRL TO_REG(0x9C) 62 #define PINMUX_CTRL7 TO_REG(0xA0) 63 #define PINMUX_CTRL8 TO_REG(0xA4) 64 #define PINMUX_CTRL9 TO_REG(0xA8) 65 #define WAKEUP_EN TO_REG(0xC0) 66 #define WAKEUP_CTRL TO_REG(0xC4) 67 #define HW_STRAP2 TO_REG(0xD0) 68 #define FREE_CNTR4 TO_REG(0xE0) 69 #define FREE_CNTR4_EXT TO_REG(0xE4) 70 #define CPU2_CTRL TO_REG(0x100) 71 #define CPU2_BASE_SEG1 TO_REG(0x104) 72 #define CPU2_BASE_SEG2 TO_REG(0x108) 73 #define CPU2_BASE_SEG3 TO_REG(0x10C) 74 #define CPU2_BASE_SEG4 TO_REG(0x110) 75 #define CPU2_BASE_SEG5 TO_REG(0x114) 76 #define CPU2_CACHE_CTRL TO_REG(0x118) 77 #define UART_HPLL_CLK TO_REG(0x160) 78 #define PCIE_CTRL TO_REG(0x180) 79 #define BMC_MMIO_CTRL TO_REG(0x184) 80 #define RELOC_DECODE_BASE1 TO_REG(0x188) 81 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 82 #define MAILBOX_DECODE_BASE TO_REG(0x190) 83 #define SRAM_DECODE_BASE1 TO_REG(0x194) 84 #define SRAM_DECODE_BASE2 TO_REG(0x198) 85 #define BMC_REV TO_REG(0x19C) 86 #define BMC_DEV_ID TO_REG(0x1A4) 87 88 #define PROT_KEY_UNLOCK 0x1688A8A8 89 #define SCU_IO_REGION_SIZE 0x1000 90 91 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 92 [SYS_RST_CTRL] = 0xFFCFFEDCU, 93 [CLK_SEL] = 0xF3F40000U, 94 [CLK_STOP_CTRL] = 0x19FC3E8BU, 95 [D2PLL_PARAM] = 0x00026108U, 96 [MPLL_PARAM] = 0x00030291U, 97 [HPLL_PARAM] = 0x00000291U, 98 [MISC_CTRL1] = 0x00000010U, 99 [PCI_CTRL1] = 0x20001A03U, 100 [PCI_CTRL2] = 0x20001A03U, 101 [PCI_CTRL3] = 0x04000030U, 102 [SYS_RST_STATUS] = 0x00000001U, 103 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 104 [MISC_CTRL2] = 0x00000023U, 105 [RNG_CTRL] = 0x0000000EU, 106 [PINMUX_CTRL2] = 0x0000F000U, 107 [PINMUX_CTRL3] = 0x01000000U, 108 [PINMUX_CTRL4] = 0x000000FFU, 109 [PINMUX_CTRL5] = 0x0000A000U, 110 [WDT_RST_CTRL] = 0x003FFFF3U, 111 [PINMUX_CTRL8] = 0xFFFF0000U, 112 [PINMUX_CTRL9] = 0x000FFFFFU, 113 [FREE_CNTR4] = 0x000000FFU, 114 [FREE_CNTR4_EXT] = 0x000000FFU, 115 [CPU2_BASE_SEG1] = 0x80000000U, 116 [CPU2_BASE_SEG4] = 0x1E600000U, 117 [CPU2_BASE_SEG5] = 0xC0000000U, 118 [UART_HPLL_CLK] = 0x00001903U, 119 [PCIE_CTRL] = 0x0000007BU, 120 [BMC_DEV_ID] = 0x00002402U 121 }; 122 123 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 124 /* AST2500 revision A1 */ 125 126 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 127 [SYS_RST_CTRL] = 0xFFCFFEDCU, 128 [CLK_SEL] = 0xF3F40000U, 129 [CLK_STOP_CTRL] = 0x19FC3E8BU, 130 [D2PLL_PARAM] = 0x00026108U, 131 [MPLL_PARAM] = 0x00030291U, 132 [HPLL_PARAM] = 0x93000400U, 133 [MISC_CTRL1] = 0x00000010U, 134 [PCI_CTRL1] = 0x20001A03U, 135 [PCI_CTRL2] = 0x20001A03U, 136 [PCI_CTRL3] = 0x04000030U, 137 [SYS_RST_STATUS] = 0x00000001U, 138 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 139 [MISC_CTRL2] = 0x00000023U, 140 [RNG_CTRL] = 0x0000000EU, 141 [PINMUX_CTRL2] = 0x0000F000U, 142 [PINMUX_CTRL3] = 0x03000000U, 143 [PINMUX_CTRL4] = 0x00000000U, 144 [PINMUX_CTRL5] = 0x0000A000U, 145 [WDT_RST_CTRL] = 0x023FFFF3U, 146 [PINMUX_CTRL8] = 0xFFFF0000U, 147 [PINMUX_CTRL9] = 0x000FFFFFU, 148 [FREE_CNTR4] = 0x000000FFU, 149 [FREE_CNTR4_EXT] = 0x000000FFU, 150 [CPU2_BASE_SEG1] = 0x80000000U, 151 [CPU2_BASE_SEG4] = 0x1E600000U, 152 [CPU2_BASE_SEG5] = 0xC0000000U, 153 [UART_HPLL_CLK] = 0x00001903U, 154 [PCIE_CTRL] = 0x0000007BU, 155 [BMC_DEV_ID] = 0x00002402U 156 }; 157 158 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 159 { 160 AspeedSCUState *s = ASPEED_SCU(opaque); 161 int reg = TO_REG(offset); 162 163 if (reg >= ARRAY_SIZE(s->regs)) { 164 qemu_log_mask(LOG_GUEST_ERROR, 165 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 166 __func__, offset); 167 return 0; 168 } 169 170 switch (reg) { 171 case WAKEUP_EN: 172 qemu_log_mask(LOG_GUEST_ERROR, 173 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 174 __func__, offset); 175 break; 176 } 177 178 return s->regs[reg]; 179 } 180 181 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, 182 unsigned size) 183 { 184 AspeedSCUState *s = ASPEED_SCU(opaque); 185 int reg = TO_REG(offset); 186 187 if (reg >= ARRAY_SIZE(s->regs)) { 188 qemu_log_mask(LOG_GUEST_ERROR, 189 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 190 __func__, offset); 191 return; 192 } 193 194 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 195 s->regs[PROT_KEY] != PROT_KEY_UNLOCK) { 196 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 197 return; 198 } 199 200 trace_aspeed_scu_write(offset, size, data); 201 202 switch (reg) { 203 case FREQ_CNTR_EVAL: 204 case VGA_SCRATCH1 ... VGA_SCRATCH8: 205 case RNG_DATA: 206 case SILICON_REV: 207 case FREE_CNTR4: 208 case FREE_CNTR4_EXT: 209 qemu_log_mask(LOG_GUEST_ERROR, 210 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 211 __func__, offset); 212 return; 213 } 214 215 s->regs[reg] = data; 216 } 217 218 static const MemoryRegionOps aspeed_scu_ops = { 219 .read = aspeed_scu_read, 220 .write = aspeed_scu_write, 221 .endianness = DEVICE_LITTLE_ENDIAN, 222 .valid.min_access_size = 4, 223 .valid.max_access_size = 4, 224 .valid.unaligned = false, 225 }; 226 227 static void aspeed_scu_reset(DeviceState *dev) 228 { 229 AspeedSCUState *s = ASPEED_SCU(dev); 230 const uint32_t *reset; 231 232 switch (s->silicon_rev) { 233 case AST2400_A0_SILICON_REV: 234 case AST2400_A1_SILICON_REV: 235 reset = ast2400_a0_resets; 236 break; 237 case AST2500_A0_SILICON_REV: 238 case AST2500_A1_SILICON_REV: 239 reset = ast2500_a1_resets; 240 break; 241 default: 242 g_assert_not_reached(); 243 } 244 245 memcpy(s->regs, reset, sizeof(s->regs)); 246 s->regs[SILICON_REV] = s->silicon_rev; 247 s->regs[HW_STRAP1] = s->hw_strap1; 248 s->regs[HW_STRAP2] = s->hw_strap2; 249 } 250 251 static uint32_t aspeed_silicon_revs[] = { 252 AST2400_A0_SILICON_REV, 253 AST2400_A1_SILICON_REV, 254 AST2500_A0_SILICON_REV, 255 AST2500_A1_SILICON_REV, 256 }; 257 258 bool is_supported_silicon_rev(uint32_t silicon_rev) 259 { 260 int i; 261 262 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 263 if (silicon_rev == aspeed_silicon_revs[i]) { 264 return true; 265 } 266 } 267 268 return false; 269 } 270 271 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 272 { 273 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 274 AspeedSCUState *s = ASPEED_SCU(dev); 275 276 if (!is_supported_silicon_rev(s->silicon_rev)) { 277 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 278 s->silicon_rev); 279 return; 280 } 281 282 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, 283 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 284 285 sysbus_init_mmio(sbd, &s->iomem); 286 } 287 288 static const VMStateDescription vmstate_aspeed_scu = { 289 .name = "aspeed.scu", 290 .version_id = 1, 291 .minimum_version_id = 1, 292 .fields = (VMStateField[]) { 293 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), 294 VMSTATE_END_OF_LIST() 295 } 296 }; 297 298 static Property aspeed_scu_properties[] = { 299 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 300 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 301 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 302 DEFINE_PROP_END_OF_LIST(), 303 }; 304 305 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 306 { 307 DeviceClass *dc = DEVICE_CLASS(klass); 308 dc->realize = aspeed_scu_realize; 309 dc->reset = aspeed_scu_reset; 310 dc->desc = "ASPEED System Control Unit"; 311 dc->vmsd = &vmstate_aspeed_scu; 312 dc->props = aspeed_scu_properties; 313 } 314 315 static const TypeInfo aspeed_scu_info = { 316 .name = TYPE_ASPEED_SCU, 317 .parent = TYPE_SYS_BUS_DEVICE, 318 .instance_size = sizeof(AspeedSCUState), 319 .class_init = aspeed_scu_class_init, 320 }; 321 322 static void aspeed_scu_register_types(void) 323 { 324 type_register_static(&aspeed_scu_info); 325 } 326 327 type_init(aspeed_scu_register_types); 328