1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "qapi/error.h" 16 #include "qapi/visitor.h" 17 #include "qemu/bitops.h" 18 #include "qemu/log.h" 19 #include "qemu/guest-random.h" 20 #include "trace.h" 21 22 #define TO_REG(offset) ((offset) >> 2) 23 24 #define PROT_KEY TO_REG(0x00) 25 #define SYS_RST_CTRL TO_REG(0x04) 26 #define CLK_SEL TO_REG(0x08) 27 #define CLK_STOP_CTRL TO_REG(0x0C) 28 #define FREQ_CNTR_CTRL TO_REG(0x10) 29 #define FREQ_CNTR_EVAL TO_REG(0x14) 30 #define IRQ_CTRL TO_REG(0x18) 31 #define D2PLL_PARAM TO_REG(0x1C) 32 #define MPLL_PARAM TO_REG(0x20) 33 #define HPLL_PARAM TO_REG(0x24) 34 #define FREQ_CNTR_RANGE TO_REG(0x28) 35 #define MISC_CTRL1 TO_REG(0x2C) 36 #define PCI_CTRL1 TO_REG(0x30) 37 #define PCI_CTRL2 TO_REG(0x34) 38 #define PCI_CTRL3 TO_REG(0x38) 39 #define SYS_RST_STATUS TO_REG(0x3C) 40 #define SOC_SCRATCH1 TO_REG(0x40) 41 #define SOC_SCRATCH2 TO_REG(0x44) 42 #define MAC_CLK_DELAY TO_REG(0x48) 43 #define MISC_CTRL2 TO_REG(0x4C) 44 #define VGA_SCRATCH1 TO_REG(0x50) 45 #define VGA_SCRATCH2 TO_REG(0x54) 46 #define VGA_SCRATCH3 TO_REG(0x58) 47 #define VGA_SCRATCH4 TO_REG(0x5C) 48 #define VGA_SCRATCH5 TO_REG(0x60) 49 #define VGA_SCRATCH6 TO_REG(0x64) 50 #define VGA_SCRATCH7 TO_REG(0x68) 51 #define VGA_SCRATCH8 TO_REG(0x6C) 52 #define HW_STRAP1 TO_REG(0x70) 53 #define RNG_CTRL TO_REG(0x74) 54 #define RNG_DATA TO_REG(0x78) 55 #define SILICON_REV TO_REG(0x7C) 56 #define PINMUX_CTRL1 TO_REG(0x80) 57 #define PINMUX_CTRL2 TO_REG(0x84) 58 #define PINMUX_CTRL3 TO_REG(0x88) 59 #define PINMUX_CTRL4 TO_REG(0x8C) 60 #define PINMUX_CTRL5 TO_REG(0x90) 61 #define PINMUX_CTRL6 TO_REG(0x94) 62 #define WDT_RST_CTRL TO_REG(0x9C) 63 #define PINMUX_CTRL7 TO_REG(0xA0) 64 #define PINMUX_CTRL8 TO_REG(0xA4) 65 #define PINMUX_CTRL9 TO_REG(0xA8) 66 #define WAKEUP_EN TO_REG(0xC0) 67 #define WAKEUP_CTRL TO_REG(0xC4) 68 #define HW_STRAP2 TO_REG(0xD0) 69 #define FREE_CNTR4 TO_REG(0xE0) 70 #define FREE_CNTR4_EXT TO_REG(0xE4) 71 #define CPU2_CTRL TO_REG(0x100) 72 #define CPU2_BASE_SEG1 TO_REG(0x104) 73 #define CPU2_BASE_SEG2 TO_REG(0x108) 74 #define CPU2_BASE_SEG3 TO_REG(0x10C) 75 #define CPU2_BASE_SEG4 TO_REG(0x110) 76 #define CPU2_BASE_SEG5 TO_REG(0x114) 77 #define CPU2_CACHE_CTRL TO_REG(0x118) 78 #define UART_HPLL_CLK TO_REG(0x160) 79 #define PCIE_CTRL TO_REG(0x180) 80 #define BMC_MMIO_CTRL TO_REG(0x184) 81 #define RELOC_DECODE_BASE1 TO_REG(0x188) 82 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 83 #define MAILBOX_DECODE_BASE TO_REG(0x190) 84 #define SRAM_DECODE_BASE1 TO_REG(0x194) 85 #define SRAM_DECODE_BASE2 TO_REG(0x198) 86 #define BMC_REV TO_REG(0x19C) 87 #define BMC_DEV_ID TO_REG(0x1A4) 88 89 #define SCU_IO_REGION_SIZE 0x1000 90 91 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 92 [SYS_RST_CTRL] = 0xFFCFFEDCU, 93 [CLK_SEL] = 0xF3F40000U, 94 [CLK_STOP_CTRL] = 0x19FC3E8BU, 95 [D2PLL_PARAM] = 0x00026108U, 96 [MPLL_PARAM] = 0x00030291U, 97 [HPLL_PARAM] = 0x00000291U, 98 [MISC_CTRL1] = 0x00000010U, 99 [PCI_CTRL1] = 0x20001A03U, 100 [PCI_CTRL2] = 0x20001A03U, 101 [PCI_CTRL3] = 0x04000030U, 102 [SYS_RST_STATUS] = 0x00000001U, 103 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 104 [MISC_CTRL2] = 0x00000023U, 105 [RNG_CTRL] = 0x0000000EU, 106 [PINMUX_CTRL2] = 0x0000F000U, 107 [PINMUX_CTRL3] = 0x01000000U, 108 [PINMUX_CTRL4] = 0x000000FFU, 109 [PINMUX_CTRL5] = 0x0000A000U, 110 [WDT_RST_CTRL] = 0x003FFFF3U, 111 [PINMUX_CTRL8] = 0xFFFF0000U, 112 [PINMUX_CTRL9] = 0x000FFFFFU, 113 [FREE_CNTR4] = 0x000000FFU, 114 [FREE_CNTR4_EXT] = 0x000000FFU, 115 [CPU2_BASE_SEG1] = 0x80000000U, 116 [CPU2_BASE_SEG4] = 0x1E600000U, 117 [CPU2_BASE_SEG5] = 0xC0000000U, 118 [UART_HPLL_CLK] = 0x00001903U, 119 [PCIE_CTRL] = 0x0000007BU, 120 [BMC_DEV_ID] = 0x00002402U 121 }; 122 123 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 124 /* AST2500 revision A1 */ 125 126 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 127 [SYS_RST_CTRL] = 0xFFCFFEDCU, 128 [CLK_SEL] = 0xF3F40000U, 129 [CLK_STOP_CTRL] = 0x19FC3E8BU, 130 [D2PLL_PARAM] = 0x00026108U, 131 [MPLL_PARAM] = 0x00030291U, 132 [HPLL_PARAM] = 0x93000400U, 133 [MISC_CTRL1] = 0x00000010U, 134 [PCI_CTRL1] = 0x20001A03U, 135 [PCI_CTRL2] = 0x20001A03U, 136 [PCI_CTRL3] = 0x04000030U, 137 [SYS_RST_STATUS] = 0x00000001U, 138 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 139 [MISC_CTRL2] = 0x00000023U, 140 [RNG_CTRL] = 0x0000000EU, 141 [PINMUX_CTRL2] = 0x0000F000U, 142 [PINMUX_CTRL3] = 0x03000000U, 143 [PINMUX_CTRL4] = 0x00000000U, 144 [PINMUX_CTRL5] = 0x0000A000U, 145 [WDT_RST_CTRL] = 0x023FFFF3U, 146 [PINMUX_CTRL8] = 0xFFFF0000U, 147 [PINMUX_CTRL9] = 0x000FFFFFU, 148 [FREE_CNTR4] = 0x000000FFU, 149 [FREE_CNTR4_EXT] = 0x000000FFU, 150 [CPU2_BASE_SEG1] = 0x80000000U, 151 [CPU2_BASE_SEG4] = 0x1E600000U, 152 [CPU2_BASE_SEG5] = 0xC0000000U, 153 [UART_HPLL_CLK] = 0x00001903U, 154 [PCIE_CTRL] = 0x0000007BU, 155 [BMC_DEV_ID] = 0x00002402U 156 }; 157 158 static uint32_t aspeed_scu_get_random(void) 159 { 160 uint32_t num; 161 qemu_guest_getrandom_nofail(&num, sizeof(num)); 162 return num; 163 } 164 165 static void aspeed_scu_set_apb_freq(AspeedSCUState *s) 166 { 167 uint32_t apb_divider; 168 169 switch (s->silicon_rev) { 170 case AST2400_A0_SILICON_REV: 171 case AST2400_A1_SILICON_REV: 172 apb_divider = 2; 173 break; 174 case AST2500_A0_SILICON_REV: 175 case AST2500_A1_SILICON_REV: 176 apb_divider = 4; 177 break; 178 default: 179 g_assert_not_reached(); 180 } 181 182 s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) 183 / apb_divider; 184 } 185 186 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 187 { 188 AspeedSCUState *s = ASPEED_SCU(opaque); 189 int reg = TO_REG(offset); 190 191 if (reg >= ARRAY_SIZE(s->regs)) { 192 qemu_log_mask(LOG_GUEST_ERROR, 193 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 194 __func__, offset); 195 return 0; 196 } 197 198 switch (reg) { 199 case RNG_DATA: 200 /* On hardware, RNG_DATA works regardless of 201 * the state of the enable bit in RNG_CTRL 202 */ 203 s->regs[RNG_DATA] = aspeed_scu_get_random(); 204 break; 205 case WAKEUP_EN: 206 qemu_log_mask(LOG_GUEST_ERROR, 207 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 208 __func__, offset); 209 break; 210 } 211 212 return s->regs[reg]; 213 } 214 215 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, 216 unsigned size) 217 { 218 AspeedSCUState *s = ASPEED_SCU(opaque); 219 int reg = TO_REG(offset); 220 221 if (reg >= ARRAY_SIZE(s->regs)) { 222 qemu_log_mask(LOG_GUEST_ERROR, 223 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 224 __func__, offset); 225 return; 226 } 227 228 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 229 !s->regs[PROT_KEY]) { 230 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 231 return; 232 } 233 234 trace_aspeed_scu_write(offset, size, data); 235 236 switch (reg) { 237 case PROT_KEY: 238 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 239 return; 240 case CLK_SEL: 241 s->regs[reg] = data; 242 aspeed_scu_set_apb_freq(s); 243 break; 244 case HW_STRAP1: 245 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { 246 s->regs[HW_STRAP1] |= data; 247 return; 248 } 249 /* Jump to assignment below */ 250 break; 251 case SILICON_REV: 252 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { 253 s->regs[HW_STRAP1] &= ~data; 254 } else { 255 qemu_log_mask(LOG_GUEST_ERROR, 256 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 257 __func__, offset); 258 } 259 /* Avoid assignment below, we've handled everything */ 260 return; 261 case FREQ_CNTR_EVAL: 262 case VGA_SCRATCH1 ... VGA_SCRATCH8: 263 case RNG_DATA: 264 case FREE_CNTR4: 265 case FREE_CNTR4_EXT: 266 qemu_log_mask(LOG_GUEST_ERROR, 267 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 268 __func__, offset); 269 return; 270 } 271 272 s->regs[reg] = data; 273 } 274 275 static const MemoryRegionOps aspeed_scu_ops = { 276 .read = aspeed_scu_read, 277 .write = aspeed_scu_write, 278 .endianness = DEVICE_LITTLE_ENDIAN, 279 .valid.min_access_size = 4, 280 .valid.max_access_size = 4, 281 .valid.unaligned = false, 282 }; 283 284 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) 285 { 286 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) { 287 return 25000000; 288 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { 289 return 48000000; 290 } else { 291 return 24000000; 292 } 293 } 294 295 /* 296 * Strapped frequencies for the AST2400 in MHz. They depend on the 297 * clkin frequency. 298 */ 299 static const uint32_t hpll_ast2400_freqs[][4] = { 300 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ 301 { 400, 375, 350, 425 }, /* 25MHz */ 302 }; 303 304 static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s) 305 { 306 uint32_t hpll_reg = s->regs[HPLL_PARAM]; 307 uint8_t freq_select; 308 bool clk_25m_in; 309 310 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { 311 return 0; 312 } 313 314 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { 315 uint32_t multiplier = 1; 316 317 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { 318 uint32_t n = (hpll_reg >> 5) & 0x3f; 319 uint32_t od = (hpll_reg >> 4) & 0x1; 320 uint32_t d = hpll_reg & 0xf; 321 322 multiplier = (2 - od) * ((n + 2) / (d + 1)); 323 } 324 325 return s->clkin * multiplier; 326 } 327 328 /* HW strapping */ 329 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); 330 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); 331 332 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; 333 } 334 335 static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s) 336 { 337 uint32_t hpll_reg = s->regs[HPLL_PARAM]; 338 uint32_t multiplier = 1; 339 340 if (hpll_reg & SCU_H_PLL_OFF) { 341 return 0; 342 } 343 344 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { 345 uint32_t p = (hpll_reg >> 13) & 0x3f; 346 uint32_t m = (hpll_reg >> 5) & 0xff; 347 uint32_t n = hpll_reg & 0x1f; 348 349 multiplier = ((m + 1) / (n + 1)) / (p + 1); 350 } 351 352 return s->clkin * multiplier; 353 } 354 355 static void aspeed_scu_reset(DeviceState *dev) 356 { 357 AspeedSCUState *s = ASPEED_SCU(dev); 358 const uint32_t *reset; 359 uint32_t (*calc_hpll)(AspeedSCUState *s); 360 361 switch (s->silicon_rev) { 362 case AST2400_A0_SILICON_REV: 363 case AST2400_A1_SILICON_REV: 364 reset = ast2400_a0_resets; 365 calc_hpll = aspeed_scu_calc_hpll_ast2400; 366 break; 367 case AST2500_A0_SILICON_REV: 368 case AST2500_A1_SILICON_REV: 369 reset = ast2500_a1_resets; 370 calc_hpll = aspeed_scu_calc_hpll_ast2500; 371 break; 372 default: 373 g_assert_not_reached(); 374 } 375 376 memcpy(s->regs, reset, sizeof(s->regs)); 377 s->regs[SILICON_REV] = s->silicon_rev; 378 s->regs[HW_STRAP1] = s->hw_strap1; 379 s->regs[HW_STRAP2] = s->hw_strap2; 380 s->regs[PROT_KEY] = s->hw_prot_key; 381 382 /* 383 * All registers are set. Now compute the frequencies of the main clocks 384 */ 385 s->clkin = aspeed_scu_get_clkin(s); 386 s->hpll = calc_hpll(s); 387 aspeed_scu_set_apb_freq(s); 388 } 389 390 static uint32_t aspeed_silicon_revs[] = { 391 AST2400_A0_SILICON_REV, 392 AST2400_A1_SILICON_REV, 393 AST2500_A0_SILICON_REV, 394 AST2500_A1_SILICON_REV, 395 }; 396 397 bool is_supported_silicon_rev(uint32_t silicon_rev) 398 { 399 int i; 400 401 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 402 if (silicon_rev == aspeed_silicon_revs[i]) { 403 return true; 404 } 405 } 406 407 return false; 408 } 409 410 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 411 { 412 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 413 AspeedSCUState *s = ASPEED_SCU(dev); 414 415 if (!is_supported_silicon_rev(s->silicon_rev)) { 416 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 417 s->silicon_rev); 418 return; 419 } 420 421 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, 422 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 423 424 sysbus_init_mmio(sbd, &s->iomem); 425 } 426 427 static const VMStateDescription vmstate_aspeed_scu = { 428 .name = "aspeed.scu", 429 .version_id = 1, 430 .minimum_version_id = 1, 431 .fields = (VMStateField[]) { 432 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), 433 VMSTATE_END_OF_LIST() 434 } 435 }; 436 437 static Property aspeed_scu_properties[] = { 438 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 439 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 440 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 441 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), 442 DEFINE_PROP_END_OF_LIST(), 443 }; 444 445 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 446 { 447 DeviceClass *dc = DEVICE_CLASS(klass); 448 dc->realize = aspeed_scu_realize; 449 dc->reset = aspeed_scu_reset; 450 dc->desc = "ASPEED System Control Unit"; 451 dc->vmsd = &vmstate_aspeed_scu; 452 dc->props = aspeed_scu_properties; 453 } 454 455 static const TypeInfo aspeed_scu_info = { 456 .name = TYPE_ASPEED_SCU, 457 .parent = TYPE_SYS_BUS_DEVICE, 458 .instance_size = sizeof(AspeedSCUState), 459 .class_init = aspeed_scu_class_init, 460 }; 461 462 static void aspeed_scu_register_types(void) 463 { 464 type_register_static(&aspeed_scu_info); 465 } 466 467 type_init(aspeed_scu_register_types); 468