1 /* 2 * ARM SSE-200 Message Handling Unit (MHU) 3 * 4 * Copyright (c) 2019 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the Message Handling Unit (MHU) which is part of the 14 * Arm SSE-200 and documented in 15 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "trace.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "hw/registerfields.h" 27 #include "hw/irq.h" 28 #include "hw/misc/armsse-mhu.h" 29 30 REG32(CPU0INTR_STAT, 0x0) 31 REG32(CPU0INTR_SET, 0x4) 32 REG32(CPU0INTR_CLR, 0x8) 33 REG32(CPU1INTR_STAT, 0x10) 34 REG32(CPU1INTR_SET, 0x14) 35 REG32(CPU1INTR_CLR, 0x18) 36 REG32(PID4, 0xfd0) 37 REG32(PID5, 0xfd4) 38 REG32(PID6, 0xfd8) 39 REG32(PID7, 0xfdc) 40 REG32(PID0, 0xfe0) 41 REG32(PID1, 0xfe4) 42 REG32(PID2, 0xfe8) 43 REG32(PID3, 0xfec) 44 REG32(CID0, 0xff0) 45 REG32(CID1, 0xff4) 46 REG32(CID2, 0xff8) 47 REG32(CID3, 0xffc) 48 49 /* Valid bits in the interrupt registers. If any are set the IRQ is raised */ 50 #define INTR_MASK 0xf 51 52 /* PID/CID values */ 53 static const int armsse_mhu_id[] = { 54 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 55 0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 56 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 57 }; 58 59 static void armsse_mhu_update(ARMSSEMHU *s) 60 { 61 qemu_set_irq(s->cpu0irq, s->cpu0intr != 0); 62 qemu_set_irq(s->cpu1irq, s->cpu1intr != 0); 63 } 64 65 static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size) 66 { 67 ARMSSEMHU *s = ARMSSE_MHU(opaque); 68 uint64_t r; 69 70 switch (offset) { 71 case A_CPU0INTR_STAT: 72 r = s->cpu0intr; 73 break; 74 75 case A_CPU1INTR_STAT: 76 r = s->cpu1intr; 77 break; 78 79 case A_PID4 ... A_CID3: 80 r = armsse_mhu_id[(offset - A_PID4) / 4]; 81 break; 82 83 case A_CPU0INTR_SET: 84 case A_CPU0INTR_CLR: 85 case A_CPU1INTR_SET: 86 case A_CPU1INTR_CLR: 87 qemu_log_mask(LOG_GUEST_ERROR, 88 "SSE MHU: read of write-only register at offset 0x%x\n", 89 (int)offset); 90 r = 0; 91 break; 92 93 default: 94 qemu_log_mask(LOG_GUEST_ERROR, 95 "SSE MHU read: bad offset 0x%x\n", (int)offset); 96 r = 0; 97 break; 98 } 99 trace_armsse_mhu_read(offset, r, size); 100 return r; 101 } 102 103 static void armsse_mhu_write(void *opaque, hwaddr offset, 104 uint64_t value, unsigned size) 105 { 106 ARMSSEMHU *s = ARMSSE_MHU(opaque); 107 108 trace_armsse_mhu_write(offset, value, size); 109 110 switch (offset) { 111 case A_CPU0INTR_SET: 112 s->cpu0intr |= (value & INTR_MASK); 113 break; 114 case A_CPU0INTR_CLR: 115 s->cpu0intr &= ~(value & INTR_MASK); 116 break; 117 case A_CPU1INTR_SET: 118 s->cpu1intr |= (value & INTR_MASK); 119 break; 120 case A_CPU1INTR_CLR: 121 s->cpu1intr &= ~(value & INTR_MASK); 122 break; 123 124 case A_CPU0INTR_STAT: 125 case A_CPU1INTR_STAT: 126 case A_PID4 ... A_CID3: 127 qemu_log_mask(LOG_GUEST_ERROR, 128 "SSE MHU: write to read-only register at offset 0x%x\n", 129 (int)offset); 130 break; 131 132 default: 133 qemu_log_mask(LOG_GUEST_ERROR, 134 "SSE MHU write: bad offset 0x%x\n", (int)offset); 135 break; 136 } 137 138 armsse_mhu_update(s); 139 } 140 141 static const MemoryRegionOps armsse_mhu_ops = { 142 .read = armsse_mhu_read, 143 .write = armsse_mhu_write, 144 .endianness = DEVICE_LITTLE_ENDIAN, 145 .valid.min_access_size = 4, 146 .valid.max_access_size = 4, 147 }; 148 149 static void armsse_mhu_reset(DeviceState *dev) 150 { 151 ARMSSEMHU *s = ARMSSE_MHU(dev); 152 153 s->cpu0intr = 0; 154 s->cpu1intr = 0; 155 } 156 157 static const VMStateDescription armsse_mhu_vmstate = { 158 .name = "armsse-mhu", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .fields = (VMStateField[]) { 162 VMSTATE_UINT32(cpu0intr, ARMSSEMHU), 163 VMSTATE_UINT32(cpu1intr, ARMSSEMHU), 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void armsse_mhu_init(Object *obj) 169 { 170 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 171 ARMSSEMHU *s = ARMSSE_MHU(obj); 172 173 memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops, 174 s, "armsse-mhu", 0x1000); 175 sysbus_init_mmio(sbd, &s->iomem); 176 sysbus_init_irq(sbd, &s->cpu0irq); 177 sysbus_init_irq(sbd, &s->cpu1irq); 178 } 179 180 static void armsse_mhu_class_init(ObjectClass *klass, void *data) 181 { 182 DeviceClass *dc = DEVICE_CLASS(klass); 183 184 dc->reset = armsse_mhu_reset; 185 dc->vmsd = &armsse_mhu_vmstate; 186 } 187 188 static const TypeInfo armsse_mhu_info = { 189 .name = TYPE_ARMSSE_MHU, 190 .parent = TYPE_SYS_BUS_DEVICE, 191 .instance_size = sizeof(ARMSSEMHU), 192 .instance_init = armsse_mhu_init, 193 .class_init = armsse_mhu_class_init, 194 }; 195 196 static void armsse_mhu_register_types(void) 197 { 198 type_register_static(&armsse_mhu_info); 199 } 200 201 type_init(armsse_mhu_register_types); 202