xref: /openbmc/qemu/hw/misc/armsse-cpuid.c (revision 4366e1db)
1 /*
2  * ARM SSE-200 CPU_IDENTITY register block
3  *
4  * Copyright (c) 2019 Linaro Limited
5  * Written by Peter Maydell
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License version 2 or
9  *  (at your option) any later version.
10  */
11 
12 /*
13  * This is a model of the "CPU_IDENTITY" register block which is part of the
14  * Arm SSE-200 and documented in
15  * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
16  *
17  * It consists of one read-only CPUID register (set by QOM property), plus the
18  * usual ID registers.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/log.h"
23 #include "trace.h"
24 #include "qapi/error.h"
25 #include "sysemu/sysemu.h"
26 #include "hw/sysbus.h"
27 #include "hw/registerfields.h"
28 #include "hw/misc/armsse-cpuid.h"
29 
30 REG32(CPUID, 0x0)
31 REG32(PID4, 0xfd0)
32 REG32(PID5, 0xfd4)
33 REG32(PID6, 0xfd8)
34 REG32(PID7, 0xfdc)
35 REG32(PID0, 0xfe0)
36 REG32(PID1, 0xfe4)
37 REG32(PID2, 0xfe8)
38 REG32(PID3, 0xfec)
39 REG32(CID0, 0xff0)
40 REG32(CID1, 0xff4)
41 REG32(CID2, 0xff8)
42 REG32(CID3, 0xffc)
43 
44 /* PID/CID values */
45 static const int sysinfo_id[] = {
46     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
47     0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
48     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
49 };
50 
51 static uint64_t armsse_cpuid_read(void *opaque, hwaddr offset,
52                                     unsigned size)
53 {
54     ARMSSECPUID *s = ARMSSE_CPUID(opaque);
55     uint64_t r;
56 
57     switch (offset) {
58     case A_CPUID:
59         r = s->cpuid;
60         break;
61     case A_PID4 ... A_CID3:
62         r = sysinfo_id[(offset - A_PID4) / 4];
63         break;
64     default:
65         qemu_log_mask(LOG_GUEST_ERROR,
66                       "SSE CPU_IDENTITY read: bad offset 0x%x\n", (int)offset);
67         r = 0;
68         break;
69     }
70     trace_armsse_cpuid_read(offset, r, size);
71     return r;
72 }
73 
74 static void armsse_cpuid_write(void *opaque, hwaddr offset,
75                                  uint64_t value, unsigned size)
76 {
77     trace_armsse_cpuid_write(offset, value, size);
78 
79     qemu_log_mask(LOG_GUEST_ERROR,
80                   "SSE CPU_IDENTITY: write to RO offset 0x%x\n", (int)offset);
81 }
82 
83 static const MemoryRegionOps armsse_cpuid_ops = {
84     .read = armsse_cpuid_read,
85     .write = armsse_cpuid_write,
86     .endianness = DEVICE_LITTLE_ENDIAN,
87     /* byte/halfword accesses are just zero-padded on reads and writes */
88     .impl.min_access_size = 4,
89     .impl.max_access_size = 4,
90     .valid.min_access_size = 1,
91     .valid.max_access_size = 4,
92 };
93 
94 static Property armsse_cpuid_props[] = {
95     DEFINE_PROP_UINT32("CPUID", ARMSSECPUID, cpuid, 0),
96     DEFINE_PROP_END_OF_LIST()
97 };
98 
99 static void armsse_cpuid_init(Object *obj)
100 {
101     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
102     ARMSSECPUID *s = ARMSSE_CPUID(obj);
103 
104     memory_region_init_io(&s->iomem, obj, &armsse_cpuid_ops,
105                           s, "armsse-cpuid", 0x1000);
106     sysbus_init_mmio(sbd, &s->iomem);
107 }
108 
109 static void armsse_cpuid_class_init(ObjectClass *klass, void *data)
110 {
111     DeviceClass *dc = DEVICE_CLASS(klass);
112 
113     /*
114      * This device has no guest-modifiable state and so it
115      * does not need a reset function or VMState.
116      */
117 
118     dc->props = armsse_cpuid_props;
119 }
120 
121 static const TypeInfo armsse_cpuid_info = {
122     .name = TYPE_ARMSSE_CPUID,
123     .parent = TYPE_SYS_BUS_DEVICE,
124     .instance_size = sizeof(ARMSSECPUID),
125     .instance_init = armsse_cpuid_init,
126     .class_init = armsse_cpuid_class_init,
127 };
128 
129 static void armsse_cpuid_register_types(void)
130 {
131     type_register_static(&armsse_cpuid_info);
132 }
133 
134 type_init(armsse_cpuid_register_types);
135