1 /* 2 * Arm SSE CPU PWRCTRL register block 3 * 4 * Copyright (c) 2021 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "CPU<N>_PWRCTRL block" which is part of the 14 * Arm Corstone SSE-300 Example Subsystem and documented in 15 * https://developer.arm.com/documentation/101773/0000 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "trace.h" 22 #include "qapi/error.h" 23 #include "migration/vmstate.h" 24 #include "hw/sysbus.h" 25 #include "hw/registerfields.h" 26 #include "hw/misc/armsse-cpu-pwrctrl.h" 27 28 REG32(CPUPWRCFG, 0x0) 29 REG32(PID4, 0xfd0) 30 REG32(PID5, 0xfd4) 31 REG32(PID6, 0xfd8) 32 REG32(PID7, 0xfdc) 33 REG32(PID0, 0xfe0) 34 REG32(PID1, 0xfe4) 35 REG32(PID2, 0xfe8) 36 REG32(PID3, 0xfec) 37 REG32(CID0, 0xff0) 38 REG32(CID1, 0xff4) 39 REG32(CID2, 0xff8) 40 REG32(CID3, 0xffc) 41 42 /* PID/CID values */ 43 static const int cpu_pwrctrl_id[] = { 44 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 45 0x5a, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 46 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 47 }; 48 49 static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size) 50 { 51 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque); 52 uint64_t r; 53 54 switch (offset) { 55 case A_CPUPWRCFG: 56 r = s->cpupwrcfg; 57 break; 58 case A_PID4 ... A_CID3: 59 r = cpu_pwrctrl_id[(offset - A_PID4) / 4]; 60 break; 61 default: 62 qemu_log_mask(LOG_GUEST_ERROR, 63 "SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset); 64 r = 0; 65 break; 66 } 67 trace_armsse_cpu_pwrctrl_read(offset, r, size); 68 return r; 69 } 70 71 static void pwrctrl_write(void *opaque, hwaddr offset, 72 uint64_t value, unsigned size) 73 { 74 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque); 75 76 trace_armsse_cpu_pwrctrl_write(offset, value, size); 77 78 switch (offset) { 79 case A_CPUPWRCFG: 80 qemu_log_mask(LOG_UNIMP, 81 "SSE CPU_PWRCTRL: CPUPWRCFG unimplemented\n"); 82 s->cpupwrcfg = value; 83 break; 84 default: 85 qemu_log_mask(LOG_GUEST_ERROR, 86 "SSE CPU_PWRCTRL write: bad offset 0x%x\n", (int)offset); 87 break; 88 } 89 } 90 91 static const MemoryRegionOps pwrctrl_ops = { 92 .read = pwrctrl_read, 93 .write = pwrctrl_write, 94 .endianness = DEVICE_LITTLE_ENDIAN, 95 .impl.min_access_size = 4, 96 .impl.max_access_size = 4, 97 .valid.min_access_size = 4, 98 .valid.max_access_size = 4, 99 }; 100 101 static void pwrctrl_reset(DeviceState *dev) 102 { 103 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(dev); 104 105 s->cpupwrcfg = 0; 106 } 107 108 static const VMStateDescription pwrctrl_vmstate = { 109 .name = "armsse-cpu-pwrctrl", 110 .version_id = 1, 111 .minimum_version_id = 1, 112 .fields = (VMStateField[]) { 113 VMSTATE_UINT32(cpupwrcfg, ARMSSECPUPwrCtrl), 114 VMSTATE_END_OF_LIST() 115 }, 116 }; 117 118 static void pwrctrl_init(Object *obj) 119 { 120 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 121 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(obj); 122 123 memory_region_init_io(&s->iomem, obj, &pwrctrl_ops, 124 s, "armsse-cpu-pwrctrl", 0x1000); 125 sysbus_init_mmio(sbd, &s->iomem); 126 } 127 128 static void pwrctrl_class_init(ObjectClass *klass, void *data) 129 { 130 DeviceClass *dc = DEVICE_CLASS(klass); 131 132 dc->reset = pwrctrl_reset; 133 dc->vmsd = &pwrctrl_vmstate; 134 } 135 136 static const TypeInfo pwrctrl_info = { 137 .name = TYPE_ARMSSE_CPU_PWRCTRL, 138 .parent = TYPE_SYS_BUS_DEVICE, 139 .instance_size = sizeof(ARMSSECPUPwrCtrl), 140 .instance_init = pwrctrl_init, 141 .class_init = pwrctrl_class_init, 142 }; 143 144 static void pwrctrl_register_types(void) 145 { 146 type_register_static(&pwrctrl_info); 147 } 148 149 type_init(pwrctrl_register_types); 150