1 /* 2 * Status and system control registers for ARM RealView/Versatile boards. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/hw.h" 11 #include "qemu/timer.h" 12 #include "qemu/bitops.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/primecell.h" 15 #include "sysemu/sysemu.h" 16 17 #define LOCK_VALUE 0xa05f 18 19 typedef struct { 20 SysBusDevice busdev; 21 MemoryRegion iomem; 22 qemu_irq pl110_mux_ctrl; 23 24 uint32_t sys_id; 25 uint32_t leds; 26 uint16_t lockval; 27 uint32_t cfgdata1; 28 uint32_t cfgdata2; 29 uint32_t flags; 30 uint32_t nvflags; 31 uint32_t resetlevel; 32 uint32_t proc_id; 33 uint32_t sys_mci; 34 uint32_t sys_cfgdata; 35 uint32_t sys_cfgctrl; 36 uint32_t sys_cfgstat; 37 uint32_t sys_clcd; 38 uint32_t mb_clock[6]; 39 uint32_t *db_clock; 40 uint32_t db_num_vsensors; 41 uint32_t *db_voltage; 42 uint32_t db_num_clocks; 43 uint32_t *db_clock_reset; 44 } arm_sysctl_state; 45 46 static const VMStateDescription vmstate_arm_sysctl = { 47 .name = "realview_sysctl", 48 .version_id = 4, 49 .minimum_version_id = 1, 50 .fields = (VMStateField[]) { 51 VMSTATE_UINT32(leds, arm_sysctl_state), 52 VMSTATE_UINT16(lockval, arm_sysctl_state), 53 VMSTATE_UINT32(cfgdata1, arm_sysctl_state), 54 VMSTATE_UINT32(cfgdata2, arm_sysctl_state), 55 VMSTATE_UINT32(flags, arm_sysctl_state), 56 VMSTATE_UINT32(nvflags, arm_sysctl_state), 57 VMSTATE_UINT32(resetlevel, arm_sysctl_state), 58 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), 59 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), 60 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), 61 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), 62 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), 63 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), 64 VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 65 4, vmstate_info_uint32, uint32_t), 66 VMSTATE_END_OF_LIST() 67 } 68 }; 69 70 /* The PB926 actually uses a different format for 71 * its SYS_ID register. Fortunately the bits which are 72 * board type on later boards are distinct. 73 */ 74 #define BOARD_ID_PB926 0x100 75 #define BOARD_ID_EB 0x140 76 #define BOARD_ID_PBA8 0x178 77 #define BOARD_ID_PBX 0x182 78 #define BOARD_ID_VEXPRESS 0x190 79 80 static int board_id(arm_sysctl_state *s) 81 { 82 /* Extract the board ID field from the SYS_ID register value */ 83 return (s->sys_id >> 16) & 0xfff; 84 } 85 86 static void arm_sysctl_reset(DeviceState *d) 87 { 88 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d)); 89 int i; 90 91 s->leds = 0; 92 s->lockval = 0; 93 s->cfgdata1 = 0; 94 s->cfgdata2 = 0; 95 s->flags = 0; 96 s->resetlevel = 0; 97 /* Motherboard oscillators (in Hz) */ 98 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ 99 s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ 100 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ 101 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ 102 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ 103 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ 104 /* Daughterboard oscillators: reset from property values */ 105 for (i = 0; i < s->db_num_clocks; i++) { 106 s->db_clock[i] = s->db_clock_reset[i]; 107 } 108 if (board_id(s) == BOARD_ID_VEXPRESS) { 109 /* On VExpress this register will RAZ/WI */ 110 s->sys_clcd = 0; 111 } else { 112 /* All others: CLCDID 0x1f, indicating VGA */ 113 s->sys_clcd = 0x1f00; 114 } 115 } 116 117 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, 118 unsigned size) 119 { 120 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 121 122 switch (offset) { 123 case 0x00: /* ID */ 124 return s->sys_id; 125 case 0x04: /* SW */ 126 /* General purpose hardware switches. 127 We don't have a useful way of exposing these to the user. */ 128 return 0; 129 case 0x08: /* LED */ 130 return s->leds; 131 case 0x20: /* LOCK */ 132 return s->lockval; 133 case 0x0c: /* OSC0 */ 134 case 0x10: /* OSC1 */ 135 case 0x14: /* OSC2 */ 136 case 0x18: /* OSC3 */ 137 case 0x1c: /* OSC4 */ 138 case 0x24: /* 100HZ */ 139 /* ??? Implement these. */ 140 return 0; 141 case 0x28: /* CFGDATA1 */ 142 return s->cfgdata1; 143 case 0x2c: /* CFGDATA2 */ 144 return s->cfgdata2; 145 case 0x30: /* FLAGS */ 146 return s->flags; 147 case 0x38: /* NVFLAGS */ 148 return s->nvflags; 149 case 0x40: /* RESETCTL */ 150 if (board_id(s) == BOARD_ID_VEXPRESS) { 151 /* reserved: RAZ/WI */ 152 return 0; 153 } 154 return s->resetlevel; 155 case 0x44: /* PCICTL */ 156 return 1; 157 case 0x48: /* MCI */ 158 return s->sys_mci; 159 case 0x4c: /* FLASH */ 160 return 0; 161 case 0x50: /* CLCD */ 162 return s->sys_clcd; 163 case 0x54: /* CLCDSER */ 164 return 0; 165 case 0x58: /* BOOTCS */ 166 return 0; 167 case 0x5c: /* 24MHz */ 168 return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec()); 169 case 0x60: /* MISC */ 170 return 0; 171 case 0x84: /* PROCID0 */ 172 return s->proc_id; 173 case 0x88: /* PROCID1 */ 174 return 0xff000000; 175 case 0x64: /* DMAPSR0 */ 176 case 0x68: /* DMAPSR1 */ 177 case 0x6c: /* DMAPSR2 */ 178 case 0x70: /* IOSEL */ 179 case 0x74: /* PLDCTL */ 180 case 0x80: /* BUSID */ 181 case 0x8c: /* OSCRESET0 */ 182 case 0x90: /* OSCRESET1 */ 183 case 0x94: /* OSCRESET2 */ 184 case 0x98: /* OSCRESET3 */ 185 case 0x9c: /* OSCRESET4 */ 186 case 0xc0: /* SYS_TEST_OSC0 */ 187 case 0xc4: /* SYS_TEST_OSC1 */ 188 case 0xc8: /* SYS_TEST_OSC2 */ 189 case 0xcc: /* SYS_TEST_OSC3 */ 190 case 0xd0: /* SYS_TEST_OSC4 */ 191 return 0; 192 case 0xa0: /* SYS_CFGDATA */ 193 if (board_id(s) != BOARD_ID_VEXPRESS) { 194 goto bad_reg; 195 } 196 return s->sys_cfgdata; 197 case 0xa4: /* SYS_CFGCTRL */ 198 if (board_id(s) != BOARD_ID_VEXPRESS) { 199 goto bad_reg; 200 } 201 return s->sys_cfgctrl; 202 case 0xa8: /* SYS_CFGSTAT */ 203 if (board_id(s) != BOARD_ID_VEXPRESS) { 204 goto bad_reg; 205 } 206 return s->sys_cfgstat; 207 default: 208 bad_reg: 209 qemu_log_mask(LOG_GUEST_ERROR, 210 "arm_sysctl_read: Bad register offset 0x%x\n", 211 (int)offset); 212 return 0; 213 } 214 } 215 216 /* SYS_CFGCTRL functions */ 217 #define SYS_CFG_OSC 1 218 #define SYS_CFG_VOLT 2 219 #define SYS_CFG_AMP 3 220 #define SYS_CFG_TEMP 4 221 #define SYS_CFG_RESET 5 222 #define SYS_CFG_SCC 6 223 #define SYS_CFG_MUXFPGA 7 224 #define SYS_CFG_SHUTDOWN 8 225 #define SYS_CFG_REBOOT 9 226 #define SYS_CFG_DVIMODE 11 227 #define SYS_CFG_POWER 12 228 #define SYS_CFG_ENERGY 13 229 230 /* SYS_CFGCTRL site field values */ 231 #define SYS_CFG_SITE_MB 0 232 #define SYS_CFG_SITE_DB1 1 233 #define SYS_CFG_SITE_DB2 2 234 235 /** 236 * vexpress_cfgctrl_read: 237 * @s: arm_sysctl_state pointer 238 * @dcc, @function, @site, @position, @device: split out values from 239 * SYS_CFGCTRL register 240 * @val: pointer to where to put the read data on success 241 * 242 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and 243 * write the read value to *val. On failure, return false (and val may 244 * or may not be written to). 245 */ 246 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, 247 unsigned int function, unsigned int site, 248 unsigned int position, unsigned int device, 249 uint32_t *val) 250 { 251 /* We don't support anything other than DCC 0, board stack position 0 252 * or sites other than motherboard/daughterboard: 253 */ 254 if (dcc != 0 || position != 0 || 255 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 256 goto cfgctrl_unimp; 257 } 258 259 switch (function) { 260 case SYS_CFG_VOLT: 261 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) { 262 *val = s->db_voltage[device]; 263 return true; 264 } 265 if (site == SYS_CFG_SITE_MB && device == 0) { 266 /* There is only one motherboard voltage sensor: 267 * VIO : 3.3V : bus voltage between mother and daughterboard 268 */ 269 *val = 3300000; 270 return true; 271 } 272 break; 273 case SYS_CFG_OSC: 274 if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { 275 /* motherboard clock */ 276 *val = s->mb_clock[device]; 277 return true; 278 } 279 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 280 /* daughterboard clock */ 281 *val = s->db_clock[device]; 282 return true; 283 } 284 break; 285 default: 286 break; 287 } 288 289 cfgctrl_unimp: 290 qemu_log_mask(LOG_UNIMP, 291 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function " 292 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 293 function, dcc, site, position, device); 294 return false; 295 } 296 297 /** 298 * vexpress_cfgctrl_write: 299 * @s: arm_sysctl_state pointer 300 * @dcc, @function, @site, @position, @device: split out values from 301 * SYS_CFGCTRL register 302 * @val: data to write 303 * 304 * Handle a VExpress SYS_CFGCTRL register write. On success, return true. 305 * On failure, return false. 306 */ 307 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, 308 unsigned int function, unsigned int site, 309 unsigned int position, unsigned int device, 310 uint32_t val) 311 { 312 /* We don't support anything other than DCC 0, board stack position 0 313 * or sites other than motherboard/daughterboard: 314 */ 315 if (dcc != 0 || position != 0 || 316 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 317 goto cfgctrl_unimp; 318 } 319 320 switch (function) { 321 case SYS_CFG_OSC: 322 if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { 323 /* motherboard clock */ 324 s->mb_clock[device] = val; 325 return true; 326 } 327 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 328 /* daughterboard clock */ 329 s->db_clock[device] = val; 330 return true; 331 } 332 break; 333 case SYS_CFG_MUXFPGA: 334 if (site == SYS_CFG_SITE_MB && device == 0) { 335 /* Select whether video output comes from motherboard 336 * or daughterboard: log and ignore as QEMU doesn't 337 * support this. 338 */ 339 qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output " 340 "not supported, ignoring\n"); 341 return true; 342 } 343 break; 344 case SYS_CFG_SHUTDOWN: 345 if (site == SYS_CFG_SITE_MB && device == 0) { 346 qemu_system_shutdown_request(); 347 return true; 348 } 349 break; 350 case SYS_CFG_REBOOT: 351 if (site == SYS_CFG_SITE_MB && device == 0) { 352 qemu_system_reset_request(); 353 return true; 354 } 355 break; 356 case SYS_CFG_DVIMODE: 357 if (site == SYS_CFG_SITE_MB && device == 0) { 358 /* Selecting DVI mode is meaningless for QEMU: we will 359 * always display the output correctly according to the 360 * pixel height/width programmed into the CLCD controller. 361 */ 362 return true; 363 } 364 default: 365 break; 366 } 367 368 cfgctrl_unimp: 369 qemu_log_mask(LOG_UNIMP, 370 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function " 371 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 372 function, dcc, site, position, device); 373 return false; 374 } 375 376 static void arm_sysctl_write(void *opaque, hwaddr offset, 377 uint64_t val, unsigned size) 378 { 379 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 380 381 switch (offset) { 382 case 0x08: /* LED */ 383 s->leds = val; 384 break; 385 case 0x0c: /* OSC0 */ 386 case 0x10: /* OSC1 */ 387 case 0x14: /* OSC2 */ 388 case 0x18: /* OSC3 */ 389 case 0x1c: /* OSC4 */ 390 /* ??? */ 391 break; 392 case 0x20: /* LOCK */ 393 if (val == LOCK_VALUE) 394 s->lockval = val; 395 else 396 s->lockval = val & 0x7fff; 397 break; 398 case 0x28: /* CFGDATA1 */ 399 /* ??? Need to implement this. */ 400 s->cfgdata1 = val; 401 break; 402 case 0x2c: /* CFGDATA2 */ 403 /* ??? Need to implement this. */ 404 s->cfgdata2 = val; 405 break; 406 case 0x30: /* FLAGSSET */ 407 s->flags |= val; 408 break; 409 case 0x34: /* FLAGSCLR */ 410 s->flags &= ~val; 411 break; 412 case 0x38: /* NVFLAGSSET */ 413 s->nvflags |= val; 414 break; 415 case 0x3c: /* NVFLAGSCLR */ 416 s->nvflags &= ~val; 417 break; 418 case 0x40: /* RESETCTL */ 419 switch (board_id(s)) { 420 case BOARD_ID_PB926: 421 if (s->lockval == LOCK_VALUE) { 422 s->resetlevel = val; 423 if (val & 0x100) { 424 qemu_system_reset_request(); 425 } 426 } 427 break; 428 case BOARD_ID_PBX: 429 case BOARD_ID_PBA8: 430 if (s->lockval == LOCK_VALUE) { 431 s->resetlevel = val; 432 if (val & 0x04) { 433 qemu_system_reset_request(); 434 } 435 } 436 break; 437 case BOARD_ID_VEXPRESS: 438 case BOARD_ID_EB: 439 default: 440 /* reserved: RAZ/WI */ 441 break; 442 } 443 break; 444 case 0x44: /* PCICTL */ 445 /* nothing to do. */ 446 break; 447 case 0x4c: /* FLASH */ 448 break; 449 case 0x50: /* CLCD */ 450 switch (board_id(s)) { 451 case BOARD_ID_PB926: 452 /* On 926 bits 13:8 are R/O, bits 1:0 control 453 * the mux that defines how to interpret the PL110 454 * graphics format, and other bits are r/w but we 455 * don't implement them to do anything. 456 */ 457 s->sys_clcd &= 0x3f00; 458 s->sys_clcd |= val & ~0x3f00; 459 qemu_set_irq(s->pl110_mux_ctrl, val & 3); 460 break; 461 case BOARD_ID_EB: 462 /* The EB is the same except that there is no mux since 463 * the EB has a PL111. 464 */ 465 s->sys_clcd &= 0x3f00; 466 s->sys_clcd |= val & ~0x3f00; 467 break; 468 case BOARD_ID_PBA8: 469 case BOARD_ID_PBX: 470 /* On PBA8 and PBX bit 7 is r/w and all other bits 471 * are either r/o or RAZ/WI. 472 */ 473 s->sys_clcd &= (1 << 7); 474 s->sys_clcd |= val & ~(1 << 7); 475 break; 476 case BOARD_ID_VEXPRESS: 477 default: 478 /* On VExpress this register is unimplemented and will RAZ/WI */ 479 break; 480 } 481 break; 482 case 0x54: /* CLCDSER */ 483 case 0x64: /* DMAPSR0 */ 484 case 0x68: /* DMAPSR1 */ 485 case 0x6c: /* DMAPSR2 */ 486 case 0x70: /* IOSEL */ 487 case 0x74: /* PLDCTL */ 488 case 0x80: /* BUSID */ 489 case 0x84: /* PROCID0 */ 490 case 0x88: /* PROCID1 */ 491 case 0x8c: /* OSCRESET0 */ 492 case 0x90: /* OSCRESET1 */ 493 case 0x94: /* OSCRESET2 */ 494 case 0x98: /* OSCRESET3 */ 495 case 0x9c: /* OSCRESET4 */ 496 break; 497 case 0xa0: /* SYS_CFGDATA */ 498 if (board_id(s) != BOARD_ID_VEXPRESS) { 499 goto bad_reg; 500 } 501 s->sys_cfgdata = val; 502 return; 503 case 0xa4: /* SYS_CFGCTRL */ 504 if (board_id(s) != BOARD_ID_VEXPRESS) { 505 goto bad_reg; 506 } 507 /* Undefined bits [19:18] are RAZ/WI, and writing to 508 * the start bit just triggers the action; it always reads 509 * as zero. 510 */ 511 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); 512 if (val & (1 << 31)) { 513 /* Start bit set -- actually do something */ 514 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); 515 unsigned int function = extract32(s->sys_cfgctrl, 20, 6); 516 unsigned int site = extract32(s->sys_cfgctrl, 16, 2); 517 unsigned int position = extract32(s->sys_cfgctrl, 12, 4); 518 unsigned int device = extract32(s->sys_cfgctrl, 0, 12); 519 s->sys_cfgstat = 1; /* complete */ 520 if (s->sys_cfgctrl & (1 << 30)) { 521 if (!vexpress_cfgctrl_write(s, dcc, function, site, position, 522 device, s->sys_cfgdata)) { 523 s->sys_cfgstat |= 2; /* error */ 524 } 525 } else { 526 uint32_t val; 527 if (!vexpress_cfgctrl_read(s, dcc, function, site, position, 528 device, &val)) { 529 s->sys_cfgstat |= 2; /* error */ 530 } else { 531 s->sys_cfgdata = val; 532 } 533 } 534 } 535 s->sys_cfgctrl &= ~(1 << 31); 536 return; 537 case 0xa8: /* SYS_CFGSTAT */ 538 if (board_id(s) != BOARD_ID_VEXPRESS) { 539 goto bad_reg; 540 } 541 s->sys_cfgstat = val & 3; 542 return; 543 default: 544 bad_reg: 545 qemu_log_mask(LOG_GUEST_ERROR, 546 "arm_sysctl_write: Bad register offset 0x%x\n", 547 (int)offset); 548 return; 549 } 550 } 551 552 static const MemoryRegionOps arm_sysctl_ops = { 553 .read = arm_sysctl_read, 554 .write = arm_sysctl_write, 555 .endianness = DEVICE_NATIVE_ENDIAN, 556 }; 557 558 static void arm_sysctl_gpio_set(void *opaque, int line, int level) 559 { 560 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 561 switch (line) { 562 case ARM_SYSCTL_GPIO_MMC_WPROT: 563 { 564 /* For PB926 and EB write-protect is bit 2 of SYS_MCI; 565 * for all later boards it is bit 1. 566 */ 567 int bit = 2; 568 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { 569 bit = 4; 570 } 571 s->sys_mci &= ~bit; 572 if (level) { 573 s->sys_mci |= bit; 574 } 575 break; 576 } 577 case ARM_SYSCTL_GPIO_MMC_CARDIN: 578 s->sys_mci &= ~1; 579 if (level) { 580 s->sys_mci |= 1; 581 } 582 break; 583 } 584 } 585 586 static void arm_sysctl_init(Object *obj) 587 { 588 DeviceState *dev = DEVICE(obj); 589 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 590 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd); 591 592 memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000); 593 sysbus_init_mmio(sd, &s->iomem); 594 qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); 595 qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); 596 } 597 598 static void arm_sysctl_realize(DeviceState *d, Error **errp) 599 { 600 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d)); 601 s->db_clock = g_new0(uint32_t, s->db_num_clocks); 602 } 603 604 static void arm_sysctl_finalize(Object *obj) 605 { 606 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 607 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); 608 g_free(s->db_voltage); 609 g_free(s->db_clock); 610 g_free(s->db_clock_reset); 611 } 612 613 static Property arm_sysctl_properties[] = { 614 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), 615 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), 616 /* Daughterboard power supply voltages (as reported via SYS_CFG) */ 617 DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, 618 db_voltage, qdev_prop_uint32, uint32_t), 619 /* Daughterboard clock reset values (as reported via SYS_CFG) */ 620 DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, 621 db_clock_reset, qdev_prop_uint32, uint32_t), 622 DEFINE_PROP_END_OF_LIST(), 623 }; 624 625 static void arm_sysctl_class_init(ObjectClass *klass, void *data) 626 { 627 DeviceClass *dc = DEVICE_CLASS(klass); 628 629 dc->realize = arm_sysctl_realize; 630 dc->reset = arm_sysctl_reset; 631 dc->vmsd = &vmstate_arm_sysctl; 632 dc->props = arm_sysctl_properties; 633 } 634 635 static const TypeInfo arm_sysctl_info = { 636 .name = "realview_sysctl", 637 .parent = TYPE_SYS_BUS_DEVICE, 638 .instance_size = sizeof(arm_sysctl_state), 639 .instance_init = arm_sysctl_init, 640 .instance_finalize = arm_sysctl_finalize, 641 .class_init = arm_sysctl_class_init, 642 }; 643 644 static void arm_sysctl_register_types(void) 645 { 646 type_register_static(&arm_sysctl_info); 647 } 648 649 type_init(arm_sysctl_register_types) 650