1 /* 2 * Status and system control registers for ARM RealView/Versatile boards. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/hw.h" 12 #include "qemu/timer.h" 13 #include "qemu/bitops.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/primecell.h" 16 #include "sysemu/sysemu.h" 17 18 #define LOCK_VALUE 0xa05f 19 20 #define TYPE_ARM_SYSCTL "realview_sysctl" 21 #define ARM_SYSCTL(obj) \ 22 OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL) 23 24 typedef struct { 25 SysBusDevice parent_obj; 26 27 MemoryRegion iomem; 28 qemu_irq pl110_mux_ctrl; 29 30 uint32_t sys_id; 31 uint32_t leds; 32 uint16_t lockval; 33 uint32_t cfgdata1; 34 uint32_t cfgdata2; 35 uint32_t flags; 36 uint32_t nvflags; 37 uint32_t resetlevel; 38 uint32_t proc_id; 39 uint32_t sys_mci; 40 uint32_t sys_cfgdata; 41 uint32_t sys_cfgctrl; 42 uint32_t sys_cfgstat; 43 uint32_t sys_clcd; 44 uint32_t mb_clock[6]; 45 uint32_t *db_clock; 46 uint32_t db_num_vsensors; 47 uint32_t *db_voltage; 48 uint32_t db_num_clocks; 49 uint32_t *db_clock_reset; 50 } arm_sysctl_state; 51 52 static const VMStateDescription vmstate_arm_sysctl = { 53 .name = "realview_sysctl", 54 .version_id = 4, 55 .minimum_version_id = 1, 56 .fields = (VMStateField[]) { 57 VMSTATE_UINT32(leds, arm_sysctl_state), 58 VMSTATE_UINT16(lockval, arm_sysctl_state), 59 VMSTATE_UINT32(cfgdata1, arm_sysctl_state), 60 VMSTATE_UINT32(cfgdata2, arm_sysctl_state), 61 VMSTATE_UINT32(flags, arm_sysctl_state), 62 VMSTATE_UINT32(nvflags, arm_sysctl_state), 63 VMSTATE_UINT32(resetlevel, arm_sysctl_state), 64 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), 65 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), 66 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), 67 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), 68 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), 69 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), 70 VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 71 4, vmstate_info_uint32, uint32_t), 72 VMSTATE_END_OF_LIST() 73 } 74 }; 75 76 /* The PB926 actually uses a different format for 77 * its SYS_ID register. Fortunately the bits which are 78 * board type on later boards are distinct. 79 */ 80 #define BOARD_ID_PB926 0x100 81 #define BOARD_ID_EB 0x140 82 #define BOARD_ID_PBA8 0x178 83 #define BOARD_ID_PBX 0x182 84 #define BOARD_ID_VEXPRESS 0x190 85 86 static int board_id(arm_sysctl_state *s) 87 { 88 /* Extract the board ID field from the SYS_ID register value */ 89 return (s->sys_id >> 16) & 0xfff; 90 } 91 92 static void arm_sysctl_reset(DeviceState *d) 93 { 94 arm_sysctl_state *s = ARM_SYSCTL(d); 95 int i; 96 97 s->leds = 0; 98 s->lockval = 0; 99 s->cfgdata1 = 0; 100 s->cfgdata2 = 0; 101 s->flags = 0; 102 s->resetlevel = 0; 103 /* Motherboard oscillators (in Hz) */ 104 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ 105 s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ 106 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ 107 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ 108 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ 109 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ 110 /* Daughterboard oscillators: reset from property values */ 111 for (i = 0; i < s->db_num_clocks; i++) { 112 s->db_clock[i] = s->db_clock_reset[i]; 113 } 114 if (board_id(s) == BOARD_ID_VEXPRESS) { 115 /* On VExpress this register will RAZ/WI */ 116 s->sys_clcd = 0; 117 } else { 118 /* All others: CLCDID 0x1f, indicating VGA */ 119 s->sys_clcd = 0x1f00; 120 } 121 } 122 123 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, 124 unsigned size) 125 { 126 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 127 128 switch (offset) { 129 case 0x00: /* ID */ 130 return s->sys_id; 131 case 0x04: /* SW */ 132 /* General purpose hardware switches. 133 We don't have a useful way of exposing these to the user. */ 134 return 0; 135 case 0x08: /* LED */ 136 return s->leds; 137 case 0x20: /* LOCK */ 138 return s->lockval; 139 case 0x0c: /* OSC0 */ 140 case 0x10: /* OSC1 */ 141 case 0x14: /* OSC2 */ 142 case 0x18: /* OSC3 */ 143 case 0x1c: /* OSC4 */ 144 case 0x24: /* 100HZ */ 145 /* ??? Implement these. */ 146 return 0; 147 case 0x28: /* CFGDATA1 */ 148 return s->cfgdata1; 149 case 0x2c: /* CFGDATA2 */ 150 return s->cfgdata2; 151 case 0x30: /* FLAGS */ 152 return s->flags; 153 case 0x38: /* NVFLAGS */ 154 return s->nvflags; 155 case 0x40: /* RESETCTL */ 156 if (board_id(s) == BOARD_ID_VEXPRESS) { 157 /* reserved: RAZ/WI */ 158 return 0; 159 } 160 return s->resetlevel; 161 case 0x44: /* PCICTL */ 162 return 1; 163 case 0x48: /* MCI */ 164 return s->sys_mci; 165 case 0x4c: /* FLASH */ 166 return 0; 167 case 0x50: /* CLCD */ 168 return s->sys_clcd; 169 case 0x54: /* CLCDSER */ 170 return 0; 171 case 0x58: /* BOOTCS */ 172 return 0; 173 case 0x5c: /* 24MHz */ 174 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, 175 NANOSECONDS_PER_SECOND); 176 case 0x60: /* MISC */ 177 return 0; 178 case 0x84: /* PROCID0 */ 179 return s->proc_id; 180 case 0x88: /* PROCID1 */ 181 return 0xff000000; 182 case 0x64: /* DMAPSR0 */ 183 case 0x68: /* DMAPSR1 */ 184 case 0x6c: /* DMAPSR2 */ 185 case 0x70: /* IOSEL */ 186 case 0x74: /* PLDCTL */ 187 case 0x80: /* BUSID */ 188 case 0x8c: /* OSCRESET0 */ 189 case 0x90: /* OSCRESET1 */ 190 case 0x94: /* OSCRESET2 */ 191 case 0x98: /* OSCRESET3 */ 192 case 0x9c: /* OSCRESET4 */ 193 case 0xc0: /* SYS_TEST_OSC0 */ 194 case 0xc4: /* SYS_TEST_OSC1 */ 195 case 0xc8: /* SYS_TEST_OSC2 */ 196 case 0xcc: /* SYS_TEST_OSC3 */ 197 case 0xd0: /* SYS_TEST_OSC4 */ 198 return 0; 199 case 0xa0: /* SYS_CFGDATA */ 200 if (board_id(s) != BOARD_ID_VEXPRESS) { 201 goto bad_reg; 202 } 203 return s->sys_cfgdata; 204 case 0xa4: /* SYS_CFGCTRL */ 205 if (board_id(s) != BOARD_ID_VEXPRESS) { 206 goto bad_reg; 207 } 208 return s->sys_cfgctrl; 209 case 0xa8: /* SYS_CFGSTAT */ 210 if (board_id(s) != BOARD_ID_VEXPRESS) { 211 goto bad_reg; 212 } 213 return s->sys_cfgstat; 214 default: 215 bad_reg: 216 qemu_log_mask(LOG_GUEST_ERROR, 217 "arm_sysctl_read: Bad register offset 0x%x\n", 218 (int)offset); 219 return 0; 220 } 221 } 222 223 /* SYS_CFGCTRL functions */ 224 #define SYS_CFG_OSC 1 225 #define SYS_CFG_VOLT 2 226 #define SYS_CFG_AMP 3 227 #define SYS_CFG_TEMP 4 228 #define SYS_CFG_RESET 5 229 #define SYS_CFG_SCC 6 230 #define SYS_CFG_MUXFPGA 7 231 #define SYS_CFG_SHUTDOWN 8 232 #define SYS_CFG_REBOOT 9 233 #define SYS_CFG_DVIMODE 11 234 #define SYS_CFG_POWER 12 235 #define SYS_CFG_ENERGY 13 236 237 /* SYS_CFGCTRL site field values */ 238 #define SYS_CFG_SITE_MB 0 239 #define SYS_CFG_SITE_DB1 1 240 #define SYS_CFG_SITE_DB2 2 241 242 /** 243 * vexpress_cfgctrl_read: 244 * @s: arm_sysctl_state pointer 245 * @dcc, @function, @site, @position, @device: split out values from 246 * SYS_CFGCTRL register 247 * @val: pointer to where to put the read data on success 248 * 249 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and 250 * write the read value to *val. On failure, return false (and val may 251 * or may not be written to). 252 */ 253 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, 254 unsigned int function, unsigned int site, 255 unsigned int position, unsigned int device, 256 uint32_t *val) 257 { 258 /* We don't support anything other than DCC 0, board stack position 0 259 * or sites other than motherboard/daughterboard: 260 */ 261 if (dcc != 0 || position != 0 || 262 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 263 goto cfgctrl_unimp; 264 } 265 266 switch (function) { 267 case SYS_CFG_VOLT: 268 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) { 269 *val = s->db_voltage[device]; 270 return true; 271 } 272 if (site == SYS_CFG_SITE_MB && device == 0) { 273 /* There is only one motherboard voltage sensor: 274 * VIO : 3.3V : bus voltage between mother and daughterboard 275 */ 276 *val = 3300000; 277 return true; 278 } 279 break; 280 case SYS_CFG_OSC: 281 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 282 /* motherboard clock */ 283 *val = s->mb_clock[device]; 284 return true; 285 } 286 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 287 /* daughterboard clock */ 288 *val = s->db_clock[device]; 289 return true; 290 } 291 break; 292 default: 293 break; 294 } 295 296 cfgctrl_unimp: 297 qemu_log_mask(LOG_UNIMP, 298 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function " 299 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 300 function, dcc, site, position, device); 301 return false; 302 } 303 304 /** 305 * vexpress_cfgctrl_write: 306 * @s: arm_sysctl_state pointer 307 * @dcc, @function, @site, @position, @device: split out values from 308 * SYS_CFGCTRL register 309 * @val: data to write 310 * 311 * Handle a VExpress SYS_CFGCTRL register write. On success, return true. 312 * On failure, return false. 313 */ 314 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, 315 unsigned int function, unsigned int site, 316 unsigned int position, unsigned int device, 317 uint32_t val) 318 { 319 /* We don't support anything other than DCC 0, board stack position 0 320 * or sites other than motherboard/daughterboard: 321 */ 322 if (dcc != 0 || position != 0 || 323 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 324 goto cfgctrl_unimp; 325 } 326 327 switch (function) { 328 case SYS_CFG_OSC: 329 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 330 /* motherboard clock */ 331 s->mb_clock[device] = val; 332 return true; 333 } 334 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 335 /* daughterboard clock */ 336 s->db_clock[device] = val; 337 return true; 338 } 339 break; 340 case SYS_CFG_MUXFPGA: 341 if (site == SYS_CFG_SITE_MB && device == 0) { 342 /* Select whether video output comes from motherboard 343 * or daughterboard: log and ignore as QEMU doesn't 344 * support this. 345 */ 346 qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output " 347 "not supported, ignoring\n"); 348 return true; 349 } 350 break; 351 case SYS_CFG_SHUTDOWN: 352 if (site == SYS_CFG_SITE_MB && device == 0) { 353 qemu_system_shutdown_request(); 354 return true; 355 } 356 break; 357 case SYS_CFG_REBOOT: 358 if (site == SYS_CFG_SITE_MB && device == 0) { 359 qemu_system_reset_request(); 360 return true; 361 } 362 break; 363 case SYS_CFG_DVIMODE: 364 if (site == SYS_CFG_SITE_MB && device == 0) { 365 /* Selecting DVI mode is meaningless for QEMU: we will 366 * always display the output correctly according to the 367 * pixel height/width programmed into the CLCD controller. 368 */ 369 return true; 370 } 371 default: 372 break; 373 } 374 375 cfgctrl_unimp: 376 qemu_log_mask(LOG_UNIMP, 377 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function " 378 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 379 function, dcc, site, position, device); 380 return false; 381 } 382 383 static void arm_sysctl_write(void *opaque, hwaddr offset, 384 uint64_t val, unsigned size) 385 { 386 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 387 388 switch (offset) { 389 case 0x08: /* LED */ 390 s->leds = val; 391 break; 392 case 0x0c: /* OSC0 */ 393 case 0x10: /* OSC1 */ 394 case 0x14: /* OSC2 */ 395 case 0x18: /* OSC3 */ 396 case 0x1c: /* OSC4 */ 397 /* ??? */ 398 break; 399 case 0x20: /* LOCK */ 400 if (val == LOCK_VALUE) 401 s->lockval = val; 402 else 403 s->lockval = val & 0x7fff; 404 break; 405 case 0x28: /* CFGDATA1 */ 406 /* ??? Need to implement this. */ 407 s->cfgdata1 = val; 408 break; 409 case 0x2c: /* CFGDATA2 */ 410 /* ??? Need to implement this. */ 411 s->cfgdata2 = val; 412 break; 413 case 0x30: /* FLAGSSET */ 414 s->flags |= val; 415 break; 416 case 0x34: /* FLAGSCLR */ 417 s->flags &= ~val; 418 break; 419 case 0x38: /* NVFLAGSSET */ 420 s->nvflags |= val; 421 break; 422 case 0x3c: /* NVFLAGSCLR */ 423 s->nvflags &= ~val; 424 break; 425 case 0x40: /* RESETCTL */ 426 switch (board_id(s)) { 427 case BOARD_ID_PB926: 428 if (s->lockval == LOCK_VALUE) { 429 s->resetlevel = val; 430 if (val & 0x100) { 431 qemu_system_reset_request(); 432 } 433 } 434 break; 435 case BOARD_ID_PBX: 436 case BOARD_ID_PBA8: 437 if (s->lockval == LOCK_VALUE) { 438 s->resetlevel = val; 439 if (val & 0x04) { 440 qemu_system_reset_request(); 441 } 442 } 443 break; 444 case BOARD_ID_VEXPRESS: 445 case BOARD_ID_EB: 446 default: 447 /* reserved: RAZ/WI */ 448 break; 449 } 450 break; 451 case 0x44: /* PCICTL */ 452 /* nothing to do. */ 453 break; 454 case 0x4c: /* FLASH */ 455 break; 456 case 0x50: /* CLCD */ 457 switch (board_id(s)) { 458 case BOARD_ID_PB926: 459 /* On 926 bits 13:8 are R/O, bits 1:0 control 460 * the mux that defines how to interpret the PL110 461 * graphics format, and other bits are r/w but we 462 * don't implement them to do anything. 463 */ 464 s->sys_clcd &= 0x3f00; 465 s->sys_clcd |= val & ~0x3f00; 466 qemu_set_irq(s->pl110_mux_ctrl, val & 3); 467 break; 468 case BOARD_ID_EB: 469 /* The EB is the same except that there is no mux since 470 * the EB has a PL111. 471 */ 472 s->sys_clcd &= 0x3f00; 473 s->sys_clcd |= val & ~0x3f00; 474 break; 475 case BOARD_ID_PBA8: 476 case BOARD_ID_PBX: 477 /* On PBA8 and PBX bit 7 is r/w and all other bits 478 * are either r/o or RAZ/WI. 479 */ 480 s->sys_clcd &= (1 << 7); 481 s->sys_clcd |= val & ~(1 << 7); 482 break; 483 case BOARD_ID_VEXPRESS: 484 default: 485 /* On VExpress this register is unimplemented and will RAZ/WI */ 486 break; 487 } 488 break; 489 case 0x54: /* CLCDSER */ 490 case 0x64: /* DMAPSR0 */ 491 case 0x68: /* DMAPSR1 */ 492 case 0x6c: /* DMAPSR2 */ 493 case 0x70: /* IOSEL */ 494 case 0x74: /* PLDCTL */ 495 case 0x80: /* BUSID */ 496 case 0x84: /* PROCID0 */ 497 case 0x88: /* PROCID1 */ 498 case 0x8c: /* OSCRESET0 */ 499 case 0x90: /* OSCRESET1 */ 500 case 0x94: /* OSCRESET2 */ 501 case 0x98: /* OSCRESET3 */ 502 case 0x9c: /* OSCRESET4 */ 503 break; 504 case 0xa0: /* SYS_CFGDATA */ 505 if (board_id(s) != BOARD_ID_VEXPRESS) { 506 goto bad_reg; 507 } 508 s->sys_cfgdata = val; 509 return; 510 case 0xa4: /* SYS_CFGCTRL */ 511 if (board_id(s) != BOARD_ID_VEXPRESS) { 512 goto bad_reg; 513 } 514 /* Undefined bits [19:18] are RAZ/WI, and writing to 515 * the start bit just triggers the action; it always reads 516 * as zero. 517 */ 518 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); 519 if (val & (1 << 31)) { 520 /* Start bit set -- actually do something */ 521 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); 522 unsigned int function = extract32(s->sys_cfgctrl, 20, 6); 523 unsigned int site = extract32(s->sys_cfgctrl, 16, 2); 524 unsigned int position = extract32(s->sys_cfgctrl, 12, 4); 525 unsigned int device = extract32(s->sys_cfgctrl, 0, 12); 526 s->sys_cfgstat = 1; /* complete */ 527 if (s->sys_cfgctrl & (1 << 30)) { 528 if (!vexpress_cfgctrl_write(s, dcc, function, site, position, 529 device, s->sys_cfgdata)) { 530 s->sys_cfgstat |= 2; /* error */ 531 } 532 } else { 533 uint32_t val; 534 if (!vexpress_cfgctrl_read(s, dcc, function, site, position, 535 device, &val)) { 536 s->sys_cfgstat |= 2; /* error */ 537 } else { 538 s->sys_cfgdata = val; 539 } 540 } 541 } 542 s->sys_cfgctrl &= ~(1 << 31); 543 return; 544 case 0xa8: /* SYS_CFGSTAT */ 545 if (board_id(s) != BOARD_ID_VEXPRESS) { 546 goto bad_reg; 547 } 548 s->sys_cfgstat = val & 3; 549 return; 550 default: 551 bad_reg: 552 qemu_log_mask(LOG_GUEST_ERROR, 553 "arm_sysctl_write: Bad register offset 0x%x\n", 554 (int)offset); 555 return; 556 } 557 } 558 559 static const MemoryRegionOps arm_sysctl_ops = { 560 .read = arm_sysctl_read, 561 .write = arm_sysctl_write, 562 .endianness = DEVICE_NATIVE_ENDIAN, 563 }; 564 565 static void arm_sysctl_gpio_set(void *opaque, int line, int level) 566 { 567 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 568 switch (line) { 569 case ARM_SYSCTL_GPIO_MMC_WPROT: 570 { 571 /* For PB926 and EB write-protect is bit 2 of SYS_MCI; 572 * for all later boards it is bit 1. 573 */ 574 int bit = 2; 575 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { 576 bit = 4; 577 } 578 s->sys_mci &= ~bit; 579 if (level) { 580 s->sys_mci |= bit; 581 } 582 break; 583 } 584 case ARM_SYSCTL_GPIO_MMC_CARDIN: 585 s->sys_mci &= ~1; 586 if (level) { 587 s->sys_mci |= 1; 588 } 589 break; 590 } 591 } 592 593 static void arm_sysctl_init(Object *obj) 594 { 595 DeviceState *dev = DEVICE(obj); 596 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 597 arm_sysctl_state *s = ARM_SYSCTL(obj); 598 599 memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s, 600 "arm-sysctl", 0x1000); 601 sysbus_init_mmio(sd, &s->iomem); 602 qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); 603 qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); 604 } 605 606 static void arm_sysctl_realize(DeviceState *d, Error **errp) 607 { 608 arm_sysctl_state *s = ARM_SYSCTL(d); 609 610 s->db_clock = g_new0(uint32_t, s->db_num_clocks); 611 } 612 613 static void arm_sysctl_finalize(Object *obj) 614 { 615 arm_sysctl_state *s = ARM_SYSCTL(obj); 616 617 g_free(s->db_voltage); 618 g_free(s->db_clock); 619 g_free(s->db_clock_reset); 620 } 621 622 static Property arm_sysctl_properties[] = { 623 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), 624 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), 625 /* Daughterboard power supply voltages (as reported via SYS_CFG) */ 626 DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, 627 db_voltage, qdev_prop_uint32, uint32_t), 628 /* Daughterboard clock reset values (as reported via SYS_CFG) */ 629 DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, 630 db_clock_reset, qdev_prop_uint32, uint32_t), 631 DEFINE_PROP_END_OF_LIST(), 632 }; 633 634 static void arm_sysctl_class_init(ObjectClass *klass, void *data) 635 { 636 DeviceClass *dc = DEVICE_CLASS(klass); 637 638 dc->realize = arm_sysctl_realize; 639 dc->reset = arm_sysctl_reset; 640 dc->vmsd = &vmstate_arm_sysctl; 641 dc->props = arm_sysctl_properties; 642 } 643 644 static const TypeInfo arm_sysctl_info = { 645 .name = TYPE_ARM_SYSCTL, 646 .parent = TYPE_SYS_BUS_DEVICE, 647 .instance_size = sizeof(arm_sysctl_state), 648 .instance_init = arm_sysctl_init, 649 .instance_finalize = arm_sysctl_finalize, 650 .class_init = arm_sysctl_class_init, 651 }; 652 653 static void arm_sysctl_register_types(void) 654 { 655 type_register_static(&arm_sysctl_info); 656 } 657 658 type_init(arm_sysctl_register_types) 659