1 /* 2 * Status and system control registers for ARM RealView/Versatile boards. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/hw.h" 12 #include "qemu/timer.h" 13 #include "qemu/bitops.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/primecell.h" 16 #include "sysemu/sysemu.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 20 #define LOCK_VALUE 0xa05f 21 22 #define TYPE_ARM_SYSCTL "realview_sysctl" 23 #define ARM_SYSCTL(obj) \ 24 OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL) 25 26 typedef struct { 27 SysBusDevice parent_obj; 28 29 MemoryRegion iomem; 30 qemu_irq pl110_mux_ctrl; 31 32 uint32_t sys_id; 33 uint32_t leds; 34 uint16_t lockval; 35 uint32_t cfgdata1; 36 uint32_t cfgdata2; 37 uint32_t flags; 38 uint32_t nvflags; 39 uint32_t resetlevel; 40 uint32_t proc_id; 41 uint32_t sys_mci; 42 uint32_t sys_cfgdata; 43 uint32_t sys_cfgctrl; 44 uint32_t sys_cfgstat; 45 uint32_t sys_clcd; 46 uint32_t mb_clock[6]; 47 uint32_t *db_clock; 48 uint32_t db_num_vsensors; 49 uint32_t *db_voltage; 50 uint32_t db_num_clocks; 51 uint32_t *db_clock_reset; 52 } arm_sysctl_state; 53 54 static const VMStateDescription vmstate_arm_sysctl = { 55 .name = "realview_sysctl", 56 .version_id = 4, 57 .minimum_version_id = 1, 58 .fields = (VMStateField[]) { 59 VMSTATE_UINT32(leds, arm_sysctl_state), 60 VMSTATE_UINT16(lockval, arm_sysctl_state), 61 VMSTATE_UINT32(cfgdata1, arm_sysctl_state), 62 VMSTATE_UINT32(cfgdata2, arm_sysctl_state), 63 VMSTATE_UINT32(flags, arm_sysctl_state), 64 VMSTATE_UINT32(nvflags, arm_sysctl_state), 65 VMSTATE_UINT32(resetlevel, arm_sysctl_state), 66 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), 67 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), 68 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), 69 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), 70 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), 71 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), 72 VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 73 4, vmstate_info_uint32, uint32_t), 74 VMSTATE_END_OF_LIST() 75 } 76 }; 77 78 /* The PB926 actually uses a different format for 79 * its SYS_ID register. Fortunately the bits which are 80 * board type on later boards are distinct. 81 */ 82 #define BOARD_ID_PB926 0x100 83 #define BOARD_ID_EB 0x140 84 #define BOARD_ID_PBA8 0x178 85 #define BOARD_ID_PBX 0x182 86 #define BOARD_ID_VEXPRESS 0x190 87 88 static int board_id(arm_sysctl_state *s) 89 { 90 /* Extract the board ID field from the SYS_ID register value */ 91 return (s->sys_id >> 16) & 0xfff; 92 } 93 94 static void arm_sysctl_reset(DeviceState *d) 95 { 96 arm_sysctl_state *s = ARM_SYSCTL(d); 97 int i; 98 99 s->leds = 0; 100 s->lockval = 0; 101 s->cfgdata1 = 0; 102 s->cfgdata2 = 0; 103 s->flags = 0; 104 s->resetlevel = 0; 105 /* Motherboard oscillators (in Hz) */ 106 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ 107 s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ 108 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ 109 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ 110 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ 111 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ 112 /* Daughterboard oscillators: reset from property values */ 113 for (i = 0; i < s->db_num_clocks; i++) { 114 s->db_clock[i] = s->db_clock_reset[i]; 115 } 116 if (board_id(s) == BOARD_ID_VEXPRESS) { 117 /* On VExpress this register will RAZ/WI */ 118 s->sys_clcd = 0; 119 } else { 120 /* All others: CLCDID 0x1f, indicating VGA */ 121 s->sys_clcd = 0x1f00; 122 } 123 } 124 125 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, 126 unsigned size) 127 { 128 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 129 130 switch (offset) { 131 case 0x00: /* ID */ 132 return s->sys_id; 133 case 0x04: /* SW */ 134 /* General purpose hardware switches. 135 We don't have a useful way of exposing these to the user. */ 136 return 0; 137 case 0x08: /* LED */ 138 return s->leds; 139 case 0x20: /* LOCK */ 140 return s->lockval; 141 case 0x0c: /* OSC0 */ 142 case 0x10: /* OSC1 */ 143 case 0x14: /* OSC2 */ 144 case 0x18: /* OSC3 */ 145 case 0x1c: /* OSC4 */ 146 case 0x24: /* 100HZ */ 147 /* ??? Implement these. */ 148 return 0; 149 case 0x28: /* CFGDATA1 */ 150 return s->cfgdata1; 151 case 0x2c: /* CFGDATA2 */ 152 return s->cfgdata2; 153 case 0x30: /* FLAGS */ 154 return s->flags; 155 case 0x38: /* NVFLAGS */ 156 return s->nvflags; 157 case 0x40: /* RESETCTL */ 158 if (board_id(s) == BOARD_ID_VEXPRESS) { 159 /* reserved: RAZ/WI */ 160 return 0; 161 } 162 return s->resetlevel; 163 case 0x44: /* PCICTL */ 164 return 1; 165 case 0x48: /* MCI */ 166 return s->sys_mci; 167 case 0x4c: /* FLASH */ 168 return 0; 169 case 0x50: /* CLCD */ 170 return s->sys_clcd; 171 case 0x54: /* CLCDSER */ 172 return 0; 173 case 0x58: /* BOOTCS */ 174 return 0; 175 case 0x5c: /* 24MHz */ 176 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, 177 NANOSECONDS_PER_SECOND); 178 case 0x60: /* MISC */ 179 return 0; 180 case 0x84: /* PROCID0 */ 181 return s->proc_id; 182 case 0x88: /* PROCID1 */ 183 return 0xff000000; 184 case 0x64: /* DMAPSR0 */ 185 case 0x68: /* DMAPSR1 */ 186 case 0x6c: /* DMAPSR2 */ 187 case 0x70: /* IOSEL */ 188 case 0x74: /* PLDCTL */ 189 case 0x80: /* BUSID */ 190 case 0x8c: /* OSCRESET0 */ 191 case 0x90: /* OSCRESET1 */ 192 case 0x94: /* OSCRESET2 */ 193 case 0x98: /* OSCRESET3 */ 194 case 0x9c: /* OSCRESET4 */ 195 case 0xc0: /* SYS_TEST_OSC0 */ 196 case 0xc4: /* SYS_TEST_OSC1 */ 197 case 0xc8: /* SYS_TEST_OSC2 */ 198 case 0xcc: /* SYS_TEST_OSC3 */ 199 case 0xd0: /* SYS_TEST_OSC4 */ 200 return 0; 201 case 0xa0: /* SYS_CFGDATA */ 202 if (board_id(s) != BOARD_ID_VEXPRESS) { 203 goto bad_reg; 204 } 205 return s->sys_cfgdata; 206 case 0xa4: /* SYS_CFGCTRL */ 207 if (board_id(s) != BOARD_ID_VEXPRESS) { 208 goto bad_reg; 209 } 210 return s->sys_cfgctrl; 211 case 0xa8: /* SYS_CFGSTAT */ 212 if (board_id(s) != BOARD_ID_VEXPRESS) { 213 goto bad_reg; 214 } 215 return s->sys_cfgstat; 216 default: 217 bad_reg: 218 qemu_log_mask(LOG_GUEST_ERROR, 219 "arm_sysctl_read: Bad register offset 0x%x\n", 220 (int)offset); 221 return 0; 222 } 223 } 224 225 /* SYS_CFGCTRL functions */ 226 #define SYS_CFG_OSC 1 227 #define SYS_CFG_VOLT 2 228 #define SYS_CFG_AMP 3 229 #define SYS_CFG_TEMP 4 230 #define SYS_CFG_RESET 5 231 #define SYS_CFG_SCC 6 232 #define SYS_CFG_MUXFPGA 7 233 #define SYS_CFG_SHUTDOWN 8 234 #define SYS_CFG_REBOOT 9 235 #define SYS_CFG_DVIMODE 11 236 #define SYS_CFG_POWER 12 237 #define SYS_CFG_ENERGY 13 238 239 /* SYS_CFGCTRL site field values */ 240 #define SYS_CFG_SITE_MB 0 241 #define SYS_CFG_SITE_DB1 1 242 #define SYS_CFG_SITE_DB2 2 243 244 /** 245 * vexpress_cfgctrl_read: 246 * @s: arm_sysctl_state pointer 247 * @dcc, @function, @site, @position, @device: split out values from 248 * SYS_CFGCTRL register 249 * @val: pointer to where to put the read data on success 250 * 251 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and 252 * write the read value to *val. On failure, return false (and val may 253 * or may not be written to). 254 */ 255 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, 256 unsigned int function, unsigned int site, 257 unsigned int position, unsigned int device, 258 uint32_t *val) 259 { 260 /* We don't support anything other than DCC 0, board stack position 0 261 * or sites other than motherboard/daughterboard: 262 */ 263 if (dcc != 0 || position != 0 || 264 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 265 goto cfgctrl_unimp; 266 } 267 268 switch (function) { 269 case SYS_CFG_VOLT: 270 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) { 271 *val = s->db_voltage[device]; 272 return true; 273 } 274 if (site == SYS_CFG_SITE_MB && device == 0) { 275 /* There is only one motherboard voltage sensor: 276 * VIO : 3.3V : bus voltage between mother and daughterboard 277 */ 278 *val = 3300000; 279 return true; 280 } 281 break; 282 case SYS_CFG_OSC: 283 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 284 /* motherboard clock */ 285 *val = s->mb_clock[device]; 286 return true; 287 } 288 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 289 /* daughterboard clock */ 290 *val = s->db_clock[device]; 291 return true; 292 } 293 break; 294 default: 295 break; 296 } 297 298 cfgctrl_unimp: 299 qemu_log_mask(LOG_UNIMP, 300 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function " 301 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 302 function, dcc, site, position, device); 303 return false; 304 } 305 306 /** 307 * vexpress_cfgctrl_write: 308 * @s: arm_sysctl_state pointer 309 * @dcc, @function, @site, @position, @device: split out values from 310 * SYS_CFGCTRL register 311 * @val: data to write 312 * 313 * Handle a VExpress SYS_CFGCTRL register write. On success, return true. 314 * On failure, return false. 315 */ 316 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, 317 unsigned int function, unsigned int site, 318 unsigned int position, unsigned int device, 319 uint32_t val) 320 { 321 /* We don't support anything other than DCC 0, board stack position 0 322 * or sites other than motherboard/daughterboard: 323 */ 324 if (dcc != 0 || position != 0 || 325 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 326 goto cfgctrl_unimp; 327 } 328 329 switch (function) { 330 case SYS_CFG_OSC: 331 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 332 /* motherboard clock */ 333 s->mb_clock[device] = val; 334 return true; 335 } 336 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 337 /* daughterboard clock */ 338 s->db_clock[device] = val; 339 return true; 340 } 341 break; 342 case SYS_CFG_MUXFPGA: 343 if (site == SYS_CFG_SITE_MB && device == 0) { 344 /* Select whether video output comes from motherboard 345 * or daughterboard: log and ignore as QEMU doesn't 346 * support this. 347 */ 348 qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output " 349 "not supported, ignoring\n"); 350 return true; 351 } 352 break; 353 case SYS_CFG_SHUTDOWN: 354 if (site == SYS_CFG_SITE_MB && device == 0) { 355 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 356 return true; 357 } 358 break; 359 case SYS_CFG_REBOOT: 360 if (site == SYS_CFG_SITE_MB && device == 0) { 361 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 362 return true; 363 } 364 break; 365 case SYS_CFG_DVIMODE: 366 if (site == SYS_CFG_SITE_MB && device == 0) { 367 /* Selecting DVI mode is meaningless for QEMU: we will 368 * always display the output correctly according to the 369 * pixel height/width programmed into the CLCD controller. 370 */ 371 return true; 372 } 373 default: 374 break; 375 } 376 377 cfgctrl_unimp: 378 qemu_log_mask(LOG_UNIMP, 379 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function " 380 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 381 function, dcc, site, position, device); 382 return false; 383 } 384 385 static void arm_sysctl_write(void *opaque, hwaddr offset, 386 uint64_t val, unsigned size) 387 { 388 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 389 390 switch (offset) { 391 case 0x08: /* LED */ 392 s->leds = val; 393 break; 394 case 0x0c: /* OSC0 */ 395 case 0x10: /* OSC1 */ 396 case 0x14: /* OSC2 */ 397 case 0x18: /* OSC3 */ 398 case 0x1c: /* OSC4 */ 399 /* ??? */ 400 break; 401 case 0x20: /* LOCK */ 402 if (val == LOCK_VALUE) 403 s->lockval = val; 404 else 405 s->lockval = val & 0x7fff; 406 break; 407 case 0x28: /* CFGDATA1 */ 408 /* ??? Need to implement this. */ 409 s->cfgdata1 = val; 410 break; 411 case 0x2c: /* CFGDATA2 */ 412 /* ??? Need to implement this. */ 413 s->cfgdata2 = val; 414 break; 415 case 0x30: /* FLAGSSET */ 416 s->flags |= val; 417 break; 418 case 0x34: /* FLAGSCLR */ 419 s->flags &= ~val; 420 break; 421 case 0x38: /* NVFLAGSSET */ 422 s->nvflags |= val; 423 break; 424 case 0x3c: /* NVFLAGSCLR */ 425 s->nvflags &= ~val; 426 break; 427 case 0x40: /* RESETCTL */ 428 switch (board_id(s)) { 429 case BOARD_ID_PB926: 430 if (s->lockval == LOCK_VALUE) { 431 s->resetlevel = val; 432 if (val & 0x100) { 433 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 434 } 435 } 436 break; 437 case BOARD_ID_PBX: 438 case BOARD_ID_PBA8: 439 if (s->lockval == LOCK_VALUE) { 440 s->resetlevel = val; 441 if (val & 0x04) { 442 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 443 } 444 } 445 break; 446 case BOARD_ID_VEXPRESS: 447 case BOARD_ID_EB: 448 default: 449 /* reserved: RAZ/WI */ 450 break; 451 } 452 break; 453 case 0x44: /* PCICTL */ 454 /* nothing to do. */ 455 break; 456 case 0x4c: /* FLASH */ 457 break; 458 case 0x50: /* CLCD */ 459 switch (board_id(s)) { 460 case BOARD_ID_PB926: 461 /* On 926 bits 13:8 are R/O, bits 1:0 control 462 * the mux that defines how to interpret the PL110 463 * graphics format, and other bits are r/w but we 464 * don't implement them to do anything. 465 */ 466 s->sys_clcd &= 0x3f00; 467 s->sys_clcd |= val & ~0x3f00; 468 qemu_set_irq(s->pl110_mux_ctrl, val & 3); 469 break; 470 case BOARD_ID_EB: 471 /* The EB is the same except that there is no mux since 472 * the EB has a PL111. 473 */ 474 s->sys_clcd &= 0x3f00; 475 s->sys_clcd |= val & ~0x3f00; 476 break; 477 case BOARD_ID_PBA8: 478 case BOARD_ID_PBX: 479 /* On PBA8 and PBX bit 7 is r/w and all other bits 480 * are either r/o or RAZ/WI. 481 */ 482 s->sys_clcd &= (1 << 7); 483 s->sys_clcd |= val & ~(1 << 7); 484 break; 485 case BOARD_ID_VEXPRESS: 486 default: 487 /* On VExpress this register is unimplemented and will RAZ/WI */ 488 break; 489 } 490 break; 491 case 0x54: /* CLCDSER */ 492 case 0x64: /* DMAPSR0 */ 493 case 0x68: /* DMAPSR1 */ 494 case 0x6c: /* DMAPSR2 */ 495 case 0x70: /* IOSEL */ 496 case 0x74: /* PLDCTL */ 497 case 0x80: /* BUSID */ 498 case 0x84: /* PROCID0 */ 499 case 0x88: /* PROCID1 */ 500 case 0x8c: /* OSCRESET0 */ 501 case 0x90: /* OSCRESET1 */ 502 case 0x94: /* OSCRESET2 */ 503 case 0x98: /* OSCRESET3 */ 504 case 0x9c: /* OSCRESET4 */ 505 break; 506 case 0xa0: /* SYS_CFGDATA */ 507 if (board_id(s) != BOARD_ID_VEXPRESS) { 508 goto bad_reg; 509 } 510 s->sys_cfgdata = val; 511 return; 512 case 0xa4: /* SYS_CFGCTRL */ 513 if (board_id(s) != BOARD_ID_VEXPRESS) { 514 goto bad_reg; 515 } 516 /* Undefined bits [19:18] are RAZ/WI, and writing to 517 * the start bit just triggers the action; it always reads 518 * as zero. 519 */ 520 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); 521 if (val & (1 << 31)) { 522 /* Start bit set -- actually do something */ 523 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); 524 unsigned int function = extract32(s->sys_cfgctrl, 20, 6); 525 unsigned int site = extract32(s->sys_cfgctrl, 16, 2); 526 unsigned int position = extract32(s->sys_cfgctrl, 12, 4); 527 unsigned int device = extract32(s->sys_cfgctrl, 0, 12); 528 s->sys_cfgstat = 1; /* complete */ 529 if (s->sys_cfgctrl & (1 << 30)) { 530 if (!vexpress_cfgctrl_write(s, dcc, function, site, position, 531 device, s->sys_cfgdata)) { 532 s->sys_cfgstat |= 2; /* error */ 533 } 534 } else { 535 uint32_t val; 536 if (!vexpress_cfgctrl_read(s, dcc, function, site, position, 537 device, &val)) { 538 s->sys_cfgstat |= 2; /* error */ 539 } else { 540 s->sys_cfgdata = val; 541 } 542 } 543 } 544 s->sys_cfgctrl &= ~(1 << 31); 545 return; 546 case 0xa8: /* SYS_CFGSTAT */ 547 if (board_id(s) != BOARD_ID_VEXPRESS) { 548 goto bad_reg; 549 } 550 s->sys_cfgstat = val & 3; 551 return; 552 default: 553 bad_reg: 554 qemu_log_mask(LOG_GUEST_ERROR, 555 "arm_sysctl_write: Bad register offset 0x%x\n", 556 (int)offset); 557 return; 558 } 559 } 560 561 static const MemoryRegionOps arm_sysctl_ops = { 562 .read = arm_sysctl_read, 563 .write = arm_sysctl_write, 564 .endianness = DEVICE_NATIVE_ENDIAN, 565 }; 566 567 static void arm_sysctl_gpio_set(void *opaque, int line, int level) 568 { 569 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 570 switch (line) { 571 case ARM_SYSCTL_GPIO_MMC_WPROT: 572 { 573 /* For PB926 and EB write-protect is bit 2 of SYS_MCI; 574 * for all later boards it is bit 1. 575 */ 576 int bit = 2; 577 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { 578 bit = 4; 579 } 580 s->sys_mci &= ~bit; 581 if (level) { 582 s->sys_mci |= bit; 583 } 584 break; 585 } 586 case ARM_SYSCTL_GPIO_MMC_CARDIN: 587 s->sys_mci &= ~1; 588 if (level) { 589 s->sys_mci |= 1; 590 } 591 break; 592 } 593 } 594 595 static void arm_sysctl_init(Object *obj) 596 { 597 DeviceState *dev = DEVICE(obj); 598 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 599 arm_sysctl_state *s = ARM_SYSCTL(obj); 600 601 memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s, 602 "arm-sysctl", 0x1000); 603 sysbus_init_mmio(sd, &s->iomem); 604 qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); 605 qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); 606 } 607 608 static void arm_sysctl_realize(DeviceState *d, Error **errp) 609 { 610 arm_sysctl_state *s = ARM_SYSCTL(d); 611 612 s->db_clock = g_new0(uint32_t, s->db_num_clocks); 613 } 614 615 static void arm_sysctl_finalize(Object *obj) 616 { 617 arm_sysctl_state *s = ARM_SYSCTL(obj); 618 619 g_free(s->db_voltage); 620 g_free(s->db_clock); 621 g_free(s->db_clock_reset); 622 } 623 624 static Property arm_sysctl_properties[] = { 625 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), 626 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), 627 /* Daughterboard power supply voltages (as reported via SYS_CFG) */ 628 DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, 629 db_voltage, qdev_prop_uint32, uint32_t), 630 /* Daughterboard clock reset values (as reported via SYS_CFG) */ 631 DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, 632 db_clock_reset, qdev_prop_uint32, uint32_t), 633 DEFINE_PROP_END_OF_LIST(), 634 }; 635 636 static void arm_sysctl_class_init(ObjectClass *klass, void *data) 637 { 638 DeviceClass *dc = DEVICE_CLASS(klass); 639 640 dc->realize = arm_sysctl_realize; 641 dc->reset = arm_sysctl_reset; 642 dc->vmsd = &vmstate_arm_sysctl; 643 dc->props = arm_sysctl_properties; 644 } 645 646 static const TypeInfo arm_sysctl_info = { 647 .name = TYPE_ARM_SYSCTL, 648 .parent = TYPE_SYS_BUS_DEVICE, 649 .instance_size = sizeof(arm_sysctl_state), 650 .instance_init = arm_sysctl_init, 651 .instance_finalize = arm_sysctl_finalize, 652 .class_init = arm_sysctl_class_init, 653 }; 654 655 static void arm_sysctl_register_types(void) 656 { 657 type_register_static(&arm_sysctl_info); 658 } 659 660 type_init(arm_sysctl_register_types) 661