1 /* 2 * Status and system control registers for ARM RealView/Versatile boards. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/hw.h" 11 #include "qemu/timer.h" 12 #include "qemu/bitops.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/primecell.h" 15 #include "sysemu/sysemu.h" 16 17 #define LOCK_VALUE 0xa05f 18 19 #define TYPE_ARM_SYSCTL "realview_sysctl" 20 #define ARM_SYSCTL(obj) \ 21 OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL) 22 23 typedef struct { 24 SysBusDevice parent_obj; 25 26 MemoryRegion iomem; 27 qemu_irq pl110_mux_ctrl; 28 29 uint32_t sys_id; 30 uint32_t leds; 31 uint16_t lockval; 32 uint32_t cfgdata1; 33 uint32_t cfgdata2; 34 uint32_t flags; 35 uint32_t nvflags; 36 uint32_t resetlevel; 37 uint32_t proc_id; 38 uint32_t sys_mci; 39 uint32_t sys_cfgdata; 40 uint32_t sys_cfgctrl; 41 uint32_t sys_cfgstat; 42 uint32_t sys_clcd; 43 uint32_t mb_clock[6]; 44 uint32_t *db_clock; 45 uint32_t db_num_vsensors; 46 uint32_t *db_voltage; 47 uint32_t db_num_clocks; 48 uint32_t *db_clock_reset; 49 } arm_sysctl_state; 50 51 static const VMStateDescription vmstate_arm_sysctl = { 52 .name = "realview_sysctl", 53 .version_id = 4, 54 .minimum_version_id = 1, 55 .fields = (VMStateField[]) { 56 VMSTATE_UINT32(leds, arm_sysctl_state), 57 VMSTATE_UINT16(lockval, arm_sysctl_state), 58 VMSTATE_UINT32(cfgdata1, arm_sysctl_state), 59 VMSTATE_UINT32(cfgdata2, arm_sysctl_state), 60 VMSTATE_UINT32(flags, arm_sysctl_state), 61 VMSTATE_UINT32(nvflags, arm_sysctl_state), 62 VMSTATE_UINT32(resetlevel, arm_sysctl_state), 63 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), 64 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), 65 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), 66 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), 67 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), 68 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), 69 VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 70 4, vmstate_info_uint32, uint32_t), 71 VMSTATE_END_OF_LIST() 72 } 73 }; 74 75 /* The PB926 actually uses a different format for 76 * its SYS_ID register. Fortunately the bits which are 77 * board type on later boards are distinct. 78 */ 79 #define BOARD_ID_PB926 0x100 80 #define BOARD_ID_EB 0x140 81 #define BOARD_ID_PBA8 0x178 82 #define BOARD_ID_PBX 0x182 83 #define BOARD_ID_VEXPRESS 0x190 84 85 static int board_id(arm_sysctl_state *s) 86 { 87 /* Extract the board ID field from the SYS_ID register value */ 88 return (s->sys_id >> 16) & 0xfff; 89 } 90 91 static void arm_sysctl_reset(DeviceState *d) 92 { 93 arm_sysctl_state *s = ARM_SYSCTL(d); 94 int i; 95 96 s->leds = 0; 97 s->lockval = 0; 98 s->cfgdata1 = 0; 99 s->cfgdata2 = 0; 100 s->flags = 0; 101 s->resetlevel = 0; 102 /* Motherboard oscillators (in Hz) */ 103 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ 104 s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ 105 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ 106 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ 107 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ 108 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ 109 /* Daughterboard oscillators: reset from property values */ 110 for (i = 0; i < s->db_num_clocks; i++) { 111 s->db_clock[i] = s->db_clock_reset[i]; 112 } 113 if (board_id(s) == BOARD_ID_VEXPRESS) { 114 /* On VExpress this register will RAZ/WI */ 115 s->sys_clcd = 0; 116 } else { 117 /* All others: CLCDID 0x1f, indicating VGA */ 118 s->sys_clcd = 0x1f00; 119 } 120 } 121 122 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, 123 unsigned size) 124 { 125 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 126 127 switch (offset) { 128 case 0x00: /* ID */ 129 return s->sys_id; 130 case 0x04: /* SW */ 131 /* General purpose hardware switches. 132 We don't have a useful way of exposing these to the user. */ 133 return 0; 134 case 0x08: /* LED */ 135 return s->leds; 136 case 0x20: /* LOCK */ 137 return s->lockval; 138 case 0x0c: /* OSC0 */ 139 case 0x10: /* OSC1 */ 140 case 0x14: /* OSC2 */ 141 case 0x18: /* OSC3 */ 142 case 0x1c: /* OSC4 */ 143 case 0x24: /* 100HZ */ 144 /* ??? Implement these. */ 145 return 0; 146 case 0x28: /* CFGDATA1 */ 147 return s->cfgdata1; 148 case 0x2c: /* CFGDATA2 */ 149 return s->cfgdata2; 150 case 0x30: /* FLAGS */ 151 return s->flags; 152 case 0x38: /* NVFLAGS */ 153 return s->nvflags; 154 case 0x40: /* RESETCTL */ 155 if (board_id(s) == BOARD_ID_VEXPRESS) { 156 /* reserved: RAZ/WI */ 157 return 0; 158 } 159 return s->resetlevel; 160 case 0x44: /* PCICTL */ 161 return 1; 162 case 0x48: /* MCI */ 163 return s->sys_mci; 164 case 0x4c: /* FLASH */ 165 return 0; 166 case 0x50: /* CLCD */ 167 return s->sys_clcd; 168 case 0x54: /* CLCDSER */ 169 return 0; 170 case 0x58: /* BOOTCS */ 171 return 0; 172 case 0x5c: /* 24MHz */ 173 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, get_ticks_per_sec()); 174 case 0x60: /* MISC */ 175 return 0; 176 case 0x84: /* PROCID0 */ 177 return s->proc_id; 178 case 0x88: /* PROCID1 */ 179 return 0xff000000; 180 case 0x64: /* DMAPSR0 */ 181 case 0x68: /* DMAPSR1 */ 182 case 0x6c: /* DMAPSR2 */ 183 case 0x70: /* IOSEL */ 184 case 0x74: /* PLDCTL */ 185 case 0x80: /* BUSID */ 186 case 0x8c: /* OSCRESET0 */ 187 case 0x90: /* OSCRESET1 */ 188 case 0x94: /* OSCRESET2 */ 189 case 0x98: /* OSCRESET3 */ 190 case 0x9c: /* OSCRESET4 */ 191 case 0xc0: /* SYS_TEST_OSC0 */ 192 case 0xc4: /* SYS_TEST_OSC1 */ 193 case 0xc8: /* SYS_TEST_OSC2 */ 194 case 0xcc: /* SYS_TEST_OSC3 */ 195 case 0xd0: /* SYS_TEST_OSC4 */ 196 return 0; 197 case 0xa0: /* SYS_CFGDATA */ 198 if (board_id(s) != BOARD_ID_VEXPRESS) { 199 goto bad_reg; 200 } 201 return s->sys_cfgdata; 202 case 0xa4: /* SYS_CFGCTRL */ 203 if (board_id(s) != BOARD_ID_VEXPRESS) { 204 goto bad_reg; 205 } 206 return s->sys_cfgctrl; 207 case 0xa8: /* SYS_CFGSTAT */ 208 if (board_id(s) != BOARD_ID_VEXPRESS) { 209 goto bad_reg; 210 } 211 return s->sys_cfgstat; 212 default: 213 bad_reg: 214 qemu_log_mask(LOG_GUEST_ERROR, 215 "arm_sysctl_read: Bad register offset 0x%x\n", 216 (int)offset); 217 return 0; 218 } 219 } 220 221 /* SYS_CFGCTRL functions */ 222 #define SYS_CFG_OSC 1 223 #define SYS_CFG_VOLT 2 224 #define SYS_CFG_AMP 3 225 #define SYS_CFG_TEMP 4 226 #define SYS_CFG_RESET 5 227 #define SYS_CFG_SCC 6 228 #define SYS_CFG_MUXFPGA 7 229 #define SYS_CFG_SHUTDOWN 8 230 #define SYS_CFG_REBOOT 9 231 #define SYS_CFG_DVIMODE 11 232 #define SYS_CFG_POWER 12 233 #define SYS_CFG_ENERGY 13 234 235 /* SYS_CFGCTRL site field values */ 236 #define SYS_CFG_SITE_MB 0 237 #define SYS_CFG_SITE_DB1 1 238 #define SYS_CFG_SITE_DB2 2 239 240 /** 241 * vexpress_cfgctrl_read: 242 * @s: arm_sysctl_state pointer 243 * @dcc, @function, @site, @position, @device: split out values from 244 * SYS_CFGCTRL register 245 * @val: pointer to where to put the read data on success 246 * 247 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and 248 * write the read value to *val. On failure, return false (and val may 249 * or may not be written to). 250 */ 251 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, 252 unsigned int function, unsigned int site, 253 unsigned int position, unsigned int device, 254 uint32_t *val) 255 { 256 /* We don't support anything other than DCC 0, board stack position 0 257 * or sites other than motherboard/daughterboard: 258 */ 259 if (dcc != 0 || position != 0 || 260 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 261 goto cfgctrl_unimp; 262 } 263 264 switch (function) { 265 case SYS_CFG_VOLT: 266 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) { 267 *val = s->db_voltage[device]; 268 return true; 269 } 270 if (site == SYS_CFG_SITE_MB && device == 0) { 271 /* There is only one motherboard voltage sensor: 272 * VIO : 3.3V : bus voltage between mother and daughterboard 273 */ 274 *val = 3300000; 275 return true; 276 } 277 break; 278 case SYS_CFG_OSC: 279 if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { 280 /* motherboard clock */ 281 *val = s->mb_clock[device]; 282 return true; 283 } 284 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 285 /* daughterboard clock */ 286 *val = s->db_clock[device]; 287 return true; 288 } 289 break; 290 default: 291 break; 292 } 293 294 cfgctrl_unimp: 295 qemu_log_mask(LOG_UNIMP, 296 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function " 297 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 298 function, dcc, site, position, device); 299 return false; 300 } 301 302 /** 303 * vexpress_cfgctrl_write: 304 * @s: arm_sysctl_state pointer 305 * @dcc, @function, @site, @position, @device: split out values from 306 * SYS_CFGCTRL register 307 * @val: data to write 308 * 309 * Handle a VExpress SYS_CFGCTRL register write. On success, return true. 310 * On failure, return false. 311 */ 312 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, 313 unsigned int function, unsigned int site, 314 unsigned int position, unsigned int device, 315 uint32_t val) 316 { 317 /* We don't support anything other than DCC 0, board stack position 0 318 * or sites other than motherboard/daughterboard: 319 */ 320 if (dcc != 0 || position != 0 || 321 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 322 goto cfgctrl_unimp; 323 } 324 325 switch (function) { 326 case SYS_CFG_OSC: 327 if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) { 328 /* motherboard clock */ 329 s->mb_clock[device] = val; 330 return true; 331 } 332 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 333 /* daughterboard clock */ 334 s->db_clock[device] = val; 335 return true; 336 } 337 break; 338 case SYS_CFG_MUXFPGA: 339 if (site == SYS_CFG_SITE_MB && device == 0) { 340 /* Select whether video output comes from motherboard 341 * or daughterboard: log and ignore as QEMU doesn't 342 * support this. 343 */ 344 qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output " 345 "not supported, ignoring\n"); 346 return true; 347 } 348 break; 349 case SYS_CFG_SHUTDOWN: 350 if (site == SYS_CFG_SITE_MB && device == 0) { 351 qemu_system_shutdown_request(); 352 return true; 353 } 354 break; 355 case SYS_CFG_REBOOT: 356 if (site == SYS_CFG_SITE_MB && device == 0) { 357 qemu_system_reset_request(); 358 return true; 359 } 360 break; 361 case SYS_CFG_DVIMODE: 362 if (site == SYS_CFG_SITE_MB && device == 0) { 363 /* Selecting DVI mode is meaningless for QEMU: we will 364 * always display the output correctly according to the 365 * pixel height/width programmed into the CLCD controller. 366 */ 367 return true; 368 } 369 default: 370 break; 371 } 372 373 cfgctrl_unimp: 374 qemu_log_mask(LOG_UNIMP, 375 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function " 376 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 377 function, dcc, site, position, device); 378 return false; 379 } 380 381 static void arm_sysctl_write(void *opaque, hwaddr offset, 382 uint64_t val, unsigned size) 383 { 384 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 385 386 switch (offset) { 387 case 0x08: /* LED */ 388 s->leds = val; 389 break; 390 case 0x0c: /* OSC0 */ 391 case 0x10: /* OSC1 */ 392 case 0x14: /* OSC2 */ 393 case 0x18: /* OSC3 */ 394 case 0x1c: /* OSC4 */ 395 /* ??? */ 396 break; 397 case 0x20: /* LOCK */ 398 if (val == LOCK_VALUE) 399 s->lockval = val; 400 else 401 s->lockval = val & 0x7fff; 402 break; 403 case 0x28: /* CFGDATA1 */ 404 /* ??? Need to implement this. */ 405 s->cfgdata1 = val; 406 break; 407 case 0x2c: /* CFGDATA2 */ 408 /* ??? Need to implement this. */ 409 s->cfgdata2 = val; 410 break; 411 case 0x30: /* FLAGSSET */ 412 s->flags |= val; 413 break; 414 case 0x34: /* FLAGSCLR */ 415 s->flags &= ~val; 416 break; 417 case 0x38: /* NVFLAGSSET */ 418 s->nvflags |= val; 419 break; 420 case 0x3c: /* NVFLAGSCLR */ 421 s->nvflags &= ~val; 422 break; 423 case 0x40: /* RESETCTL */ 424 switch (board_id(s)) { 425 case BOARD_ID_PB926: 426 if (s->lockval == LOCK_VALUE) { 427 s->resetlevel = val; 428 if (val & 0x100) { 429 qemu_system_reset_request(); 430 } 431 } 432 break; 433 case BOARD_ID_PBX: 434 case BOARD_ID_PBA8: 435 if (s->lockval == LOCK_VALUE) { 436 s->resetlevel = val; 437 if (val & 0x04) { 438 qemu_system_reset_request(); 439 } 440 } 441 break; 442 case BOARD_ID_VEXPRESS: 443 case BOARD_ID_EB: 444 default: 445 /* reserved: RAZ/WI */ 446 break; 447 } 448 break; 449 case 0x44: /* PCICTL */ 450 /* nothing to do. */ 451 break; 452 case 0x4c: /* FLASH */ 453 break; 454 case 0x50: /* CLCD */ 455 switch (board_id(s)) { 456 case BOARD_ID_PB926: 457 /* On 926 bits 13:8 are R/O, bits 1:0 control 458 * the mux that defines how to interpret the PL110 459 * graphics format, and other bits are r/w but we 460 * don't implement them to do anything. 461 */ 462 s->sys_clcd &= 0x3f00; 463 s->sys_clcd |= val & ~0x3f00; 464 qemu_set_irq(s->pl110_mux_ctrl, val & 3); 465 break; 466 case BOARD_ID_EB: 467 /* The EB is the same except that there is no mux since 468 * the EB has a PL111. 469 */ 470 s->sys_clcd &= 0x3f00; 471 s->sys_clcd |= val & ~0x3f00; 472 break; 473 case BOARD_ID_PBA8: 474 case BOARD_ID_PBX: 475 /* On PBA8 and PBX bit 7 is r/w and all other bits 476 * are either r/o or RAZ/WI. 477 */ 478 s->sys_clcd &= (1 << 7); 479 s->sys_clcd |= val & ~(1 << 7); 480 break; 481 case BOARD_ID_VEXPRESS: 482 default: 483 /* On VExpress this register is unimplemented and will RAZ/WI */ 484 break; 485 } 486 break; 487 case 0x54: /* CLCDSER */ 488 case 0x64: /* DMAPSR0 */ 489 case 0x68: /* DMAPSR1 */ 490 case 0x6c: /* DMAPSR2 */ 491 case 0x70: /* IOSEL */ 492 case 0x74: /* PLDCTL */ 493 case 0x80: /* BUSID */ 494 case 0x84: /* PROCID0 */ 495 case 0x88: /* PROCID1 */ 496 case 0x8c: /* OSCRESET0 */ 497 case 0x90: /* OSCRESET1 */ 498 case 0x94: /* OSCRESET2 */ 499 case 0x98: /* OSCRESET3 */ 500 case 0x9c: /* OSCRESET4 */ 501 break; 502 case 0xa0: /* SYS_CFGDATA */ 503 if (board_id(s) != BOARD_ID_VEXPRESS) { 504 goto bad_reg; 505 } 506 s->sys_cfgdata = val; 507 return; 508 case 0xa4: /* SYS_CFGCTRL */ 509 if (board_id(s) != BOARD_ID_VEXPRESS) { 510 goto bad_reg; 511 } 512 /* Undefined bits [19:18] are RAZ/WI, and writing to 513 * the start bit just triggers the action; it always reads 514 * as zero. 515 */ 516 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); 517 if (val & (1 << 31)) { 518 /* Start bit set -- actually do something */ 519 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); 520 unsigned int function = extract32(s->sys_cfgctrl, 20, 6); 521 unsigned int site = extract32(s->sys_cfgctrl, 16, 2); 522 unsigned int position = extract32(s->sys_cfgctrl, 12, 4); 523 unsigned int device = extract32(s->sys_cfgctrl, 0, 12); 524 s->sys_cfgstat = 1; /* complete */ 525 if (s->sys_cfgctrl & (1 << 30)) { 526 if (!vexpress_cfgctrl_write(s, dcc, function, site, position, 527 device, s->sys_cfgdata)) { 528 s->sys_cfgstat |= 2; /* error */ 529 } 530 } else { 531 uint32_t val; 532 if (!vexpress_cfgctrl_read(s, dcc, function, site, position, 533 device, &val)) { 534 s->sys_cfgstat |= 2; /* error */ 535 } else { 536 s->sys_cfgdata = val; 537 } 538 } 539 } 540 s->sys_cfgctrl &= ~(1 << 31); 541 return; 542 case 0xa8: /* SYS_CFGSTAT */ 543 if (board_id(s) != BOARD_ID_VEXPRESS) { 544 goto bad_reg; 545 } 546 s->sys_cfgstat = val & 3; 547 return; 548 default: 549 bad_reg: 550 qemu_log_mask(LOG_GUEST_ERROR, 551 "arm_sysctl_write: Bad register offset 0x%x\n", 552 (int)offset); 553 return; 554 } 555 } 556 557 static const MemoryRegionOps arm_sysctl_ops = { 558 .read = arm_sysctl_read, 559 .write = arm_sysctl_write, 560 .endianness = DEVICE_NATIVE_ENDIAN, 561 }; 562 563 static void arm_sysctl_gpio_set(void *opaque, int line, int level) 564 { 565 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 566 switch (line) { 567 case ARM_SYSCTL_GPIO_MMC_WPROT: 568 { 569 /* For PB926 and EB write-protect is bit 2 of SYS_MCI; 570 * for all later boards it is bit 1. 571 */ 572 int bit = 2; 573 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { 574 bit = 4; 575 } 576 s->sys_mci &= ~bit; 577 if (level) { 578 s->sys_mci |= bit; 579 } 580 break; 581 } 582 case ARM_SYSCTL_GPIO_MMC_CARDIN: 583 s->sys_mci &= ~1; 584 if (level) { 585 s->sys_mci |= 1; 586 } 587 break; 588 } 589 } 590 591 static void arm_sysctl_init(Object *obj) 592 { 593 DeviceState *dev = DEVICE(obj); 594 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 595 arm_sysctl_state *s = ARM_SYSCTL(obj); 596 597 memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s, 598 "arm-sysctl", 0x1000); 599 sysbus_init_mmio(sd, &s->iomem); 600 qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); 601 qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); 602 } 603 604 static void arm_sysctl_realize(DeviceState *d, Error **errp) 605 { 606 arm_sysctl_state *s = ARM_SYSCTL(d); 607 608 s->db_clock = g_new0(uint32_t, s->db_num_clocks); 609 } 610 611 static void arm_sysctl_finalize(Object *obj) 612 { 613 arm_sysctl_state *s = ARM_SYSCTL(obj); 614 615 g_free(s->db_voltage); 616 g_free(s->db_clock); 617 g_free(s->db_clock_reset); 618 } 619 620 static Property arm_sysctl_properties[] = { 621 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), 622 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), 623 /* Daughterboard power supply voltages (as reported via SYS_CFG) */ 624 DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, 625 db_voltage, qdev_prop_uint32, uint32_t), 626 /* Daughterboard clock reset values (as reported via SYS_CFG) */ 627 DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, 628 db_clock_reset, qdev_prop_uint32, uint32_t), 629 DEFINE_PROP_END_OF_LIST(), 630 }; 631 632 static void arm_sysctl_class_init(ObjectClass *klass, void *data) 633 { 634 DeviceClass *dc = DEVICE_CLASS(klass); 635 636 dc->realize = arm_sysctl_realize; 637 dc->reset = arm_sysctl_reset; 638 dc->vmsd = &vmstate_arm_sysctl; 639 dc->props = arm_sysctl_properties; 640 } 641 642 static const TypeInfo arm_sysctl_info = { 643 .name = TYPE_ARM_SYSCTL, 644 .parent = TYPE_SYS_BUS_DEVICE, 645 .instance_size = sizeof(arm_sysctl_state), 646 .instance_init = arm_sysctl_init, 647 .instance_finalize = arm_sysctl_finalize, 648 .class_init = arm_sysctl_class_init, 649 }; 650 651 static void arm_sysctl_register_types(void) 652 { 653 type_register_static(&arm_sysctl_info); 654 } 655 656 type_init(arm_sysctl_register_types) 657