1 /* 2 * ARM dummy L210, L220, PL310 cache controller. 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or any later version, as published by the Free Software 9 * Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 27 /* L2C-310 r3p2 */ 28 #define CACHE_ID 0x410000c8 29 30 #define TYPE_ARM_L2X0 "l2x0" 31 #define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0) 32 33 typedef struct L2x0State { 34 SysBusDevice parent_obj; 35 36 MemoryRegion iomem; 37 uint32_t cache_type; 38 uint32_t ctrl; 39 uint32_t aux_ctrl; 40 uint32_t data_ctrl; 41 uint32_t tag_ctrl; 42 uint32_t filter_start; 43 uint32_t filter_end; 44 } L2x0State; 45 46 static const VMStateDescription vmstate_l2x0 = { 47 .name = "l2x0", 48 .version_id = 1, 49 .minimum_version_id = 1, 50 .fields = (VMStateField[]) { 51 VMSTATE_UINT32(ctrl, L2x0State), 52 VMSTATE_UINT32(aux_ctrl, L2x0State), 53 VMSTATE_UINT32(data_ctrl, L2x0State), 54 VMSTATE_UINT32(tag_ctrl, L2x0State), 55 VMSTATE_UINT32(filter_start, L2x0State), 56 VMSTATE_UINT32(filter_end, L2x0State), 57 VMSTATE_END_OF_LIST() 58 } 59 }; 60 61 62 static uint64_t l2x0_priv_read(void *opaque, hwaddr offset, 63 unsigned size) 64 { 65 uint32_t cache_data; 66 L2x0State *s = (L2x0State *)opaque; 67 offset &= 0xfff; 68 if (offset >= 0x730 && offset < 0x800) { 69 return 0; /* cache ops complete */ 70 } 71 switch (offset) { 72 case 0: 73 return CACHE_ID; 74 case 0x4: 75 /* aux_ctrl values affect cache_type values */ 76 cache_data = (s->aux_ctrl & (7 << 17)) >> 15; 77 cache_data |= (s->aux_ctrl & (1 << 16)) >> 16; 78 return s->cache_type |= (cache_data << 18) | (cache_data << 6); 79 case 0x100: 80 return s->ctrl; 81 case 0x104: 82 return s->aux_ctrl; 83 case 0x108: 84 return s->tag_ctrl; 85 case 0x10C: 86 return s->data_ctrl; 87 case 0xC00: 88 return s->filter_start; 89 case 0xC04: 90 return s->filter_end; 91 case 0xF40: 92 return 0; 93 case 0xF60: 94 return 0; 95 case 0xF80: 96 return 0; 97 default: 98 qemu_log_mask(LOG_GUEST_ERROR, 99 "l2x0_priv_read: Bad offset %x\n", (int)offset); 100 break; 101 } 102 return 0; 103 } 104 105 static void l2x0_priv_write(void *opaque, hwaddr offset, 106 uint64_t value, unsigned size) 107 { 108 L2x0State *s = (L2x0State *)opaque; 109 offset &= 0xfff; 110 if (offset >= 0x730 && offset < 0x800) { 111 /* ignore */ 112 return; 113 } 114 switch (offset) { 115 case 0x100: 116 s->ctrl = value & 1; 117 break; 118 case 0x104: 119 s->aux_ctrl = value; 120 break; 121 case 0x108: 122 s->tag_ctrl = value; 123 break; 124 case 0x10C: 125 s->data_ctrl = value; 126 break; 127 case 0xC00: 128 s->filter_start = value; 129 break; 130 case 0xC04: 131 s->filter_end = value; 132 break; 133 case 0xF40: 134 return; 135 case 0xF60: 136 return; 137 case 0xF80: 138 return; 139 default: 140 qemu_log_mask(LOG_GUEST_ERROR, 141 "l2x0_priv_write: Bad offset %x\n", (int)offset); 142 break; 143 } 144 } 145 146 static void l2x0_priv_reset(DeviceState *dev) 147 { 148 L2x0State *s = ARM_L2X0(dev); 149 150 s->ctrl = 0; 151 s->aux_ctrl = 0x02020000; 152 s->tag_ctrl = 0; 153 s->data_ctrl = 0; 154 s->filter_start = 0; 155 s->filter_end = 0; 156 } 157 158 static const MemoryRegionOps l2x0_mem_ops = { 159 .read = l2x0_priv_read, 160 .write = l2x0_priv_write, 161 .endianness = DEVICE_NATIVE_ENDIAN, 162 }; 163 164 static void l2x0_priv_init(Object *obj) 165 { 166 L2x0State *s = ARM_L2X0(obj); 167 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 168 169 memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s, 170 "l2x0_cc", 0x1000); 171 sysbus_init_mmio(dev, &s->iomem); 172 } 173 174 static Property l2x0_properties[] = { 175 DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100), 176 DEFINE_PROP_END_OF_LIST(), 177 }; 178 179 static void l2x0_class_init(ObjectClass *klass, void *data) 180 { 181 DeviceClass *dc = DEVICE_CLASS(klass); 182 183 dc->vmsd = &vmstate_l2x0; 184 dc->props = l2x0_properties; 185 dc->reset = l2x0_priv_reset; 186 } 187 188 static const TypeInfo l2x0_info = { 189 .name = TYPE_ARM_L2X0, 190 .parent = TYPE_SYS_BUS_DEVICE, 191 .instance_size = sizeof(L2x0State), 192 .instance_init = l2x0_priv_init, 193 .class_init = l2x0_class_init, 194 }; 195 196 static void l2x0_register_types(void) 197 { 198 type_register_static(&l2x0_info); 199 } 200 201 type_init(l2x0_register_types) 202