xref: /openbmc/qemu/hw/misc/arm_integrator_debug.c (revision d6032e06)
1 /*
2  * LED, Switch and Debug control registers for ARM Integrator Boards
3  *
4  * This is currently a stub for this functionality but at least
5  * ensures something other than unassigned_mem_read() handles access
6  * to this area.
7  *
8  * The real h/w is described at:
9  *  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
10  *
11  * Copyright (c) 2013 Alex Bennée <alex@bennee.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2 or later.
14  * See the COPYING file in the top-level directory.
15  */
16 
17 #include "hw/hw.h"
18 #include "hw/sysbus.h"
19 #include "exec/address-spaces.h"
20 #include "hw/misc/arm_integrator_debug.h"
21 
22 #define INTEGRATOR_DEBUG(obj) \
23     OBJECT_CHECK(IntegratorDebugState, (obj), TYPE_INTEGRATOR_DEBUG)
24 
25 typedef struct {
26     SysBusDevice parent_obj;
27 
28     MemoryRegion iomem;
29 } IntegratorDebugState;
30 
31 static uint64_t intdbg_control_read(void *opaque, hwaddr offset,
32                                     unsigned size)
33 {
34     switch (offset >> 2) {
35     case 0: /* ALPHA */
36     case 1: /* LEDS */
37     case 2: /* SWITCHES */
38         qemu_log_mask(LOG_UNIMP,
39                       "%s: returning zero from %" HWADDR_PRIx ":%u\n",
40                       __func__, offset, size);
41         return 0;
42     default:
43         qemu_log_mask(LOG_GUEST_ERROR,
44                       "%s: Bad offset %" HWADDR_PRIx,
45                       __func__, offset);
46         return 0;
47     }
48 }
49 
50 static void intdbg_control_write(void *opaque, hwaddr offset,
51                                  uint64_t value, unsigned size)
52 {
53     switch (offset >> 2) {
54     case 1: /* ALPHA */
55     case 2: /* LEDS */
56     case 3: /* SWITCHES */
57         /* Nothing interesting implemented yet.  */
58         qemu_log_mask(LOG_UNIMP,
59                       "%s: ignoring write of %" PRIu64
60                       " to %" HWADDR_PRIx ":%u\n",
61                       __func__, value, offset, size);
62         break;
63     default:
64         qemu_log_mask(LOG_GUEST_ERROR,
65                       "%s: write of %" PRIu64
66                       " to bad offset %" HWADDR_PRIx "\n",
67                       __func__, value, offset);
68     }
69 }
70 
71 static const MemoryRegionOps intdbg_control_ops = {
72     .read = intdbg_control_read,
73     .write = intdbg_control_write,
74     .endianness = DEVICE_NATIVE_ENDIAN,
75 };
76 
77 static void intdbg_control_init(Object *obj)
78 {
79     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
80     IntegratorDebugState *s = INTEGRATOR_DEBUG(obj);
81 
82     memory_region_init_io(&s->iomem, NULL, &intdbg_control_ops,
83                           NULL, "dbg-leds", 0x1000000);
84     sysbus_init_mmio(sd, &s->iomem);
85 }
86 
87 static const TypeInfo intdbg_info = {
88     .name          = TYPE_INTEGRATOR_DEBUG,
89     .parent        = TYPE_SYS_BUS_DEVICE,
90     .instance_size = sizeof(IntegratorDebugState),
91     .instance_init = intdbg_control_init,
92 };
93 
94 static void intdbg_register_types(void)
95 {
96     type_register_static(&intdbg_info);
97 }
98 
99 type_init(intdbg_register_types)
100