xref: /openbmc/qemu/hw/misc/arm_integrator_debug.c (revision a68694cd)
1 /*
2  * LED, Switch and Debug control registers for ARM Integrator Boards
3  *
4  * This is currently a stub for this functionality but at least
5  * ensures something other than unassigned_mem_read() handles access
6  * to this area.
7  *
8  * The real h/w is described at:
9  *  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
10  *
11  * Copyright (c) 2013 Alex Bennée <alex@bennee.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2 or later.
14  * See the COPYING file in the top-level directory.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "hw/sysbus.h"
19 #include "hw/misc/arm_integrator_debug.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qom/object.h"
23 
24 typedef struct IntegratorDebugState IntegratorDebugState;
25 DECLARE_INSTANCE_CHECKER(IntegratorDebugState, INTEGRATOR_DEBUG,
26                          TYPE_INTEGRATOR_DEBUG)
27 
28 struct IntegratorDebugState {
29     SysBusDevice parent_obj;
30 
31     MemoryRegion iomem;
32 };
33 
34 static uint64_t intdbg_control_read(void *opaque, hwaddr offset,
35                                     unsigned size)
36 {
37     switch (offset >> 2) {
38     case 0: /* ALPHA */
39     case 1: /* LEDS */
40     case 2: /* SWITCHES */
41         qemu_log_mask(LOG_UNIMP,
42                       "%s: returning zero from %" HWADDR_PRIx ":%u\n",
43                       __func__, offset, size);
44         return 0;
45     default:
46         qemu_log_mask(LOG_GUEST_ERROR,
47                       "%s: Bad offset %" HWADDR_PRIx,
48                       __func__, offset);
49         return 0;
50     }
51 }
52 
53 static void intdbg_control_write(void *opaque, hwaddr offset,
54                                  uint64_t value, unsigned size)
55 {
56     switch (offset >> 2) {
57     case 1: /* ALPHA */
58     case 2: /* LEDS */
59     case 3: /* SWITCHES */
60         /* Nothing interesting implemented yet.  */
61         qemu_log_mask(LOG_UNIMP,
62                       "%s: ignoring write of %" PRIu64
63                       " to %" HWADDR_PRIx ":%u\n",
64                       __func__, value, offset, size);
65         break;
66     default:
67         qemu_log_mask(LOG_GUEST_ERROR,
68                       "%s: write of %" PRIu64
69                       " to bad offset %" HWADDR_PRIx "\n",
70                       __func__, value, offset);
71     }
72 }
73 
74 static const MemoryRegionOps intdbg_control_ops = {
75     .read = intdbg_control_read,
76     .write = intdbg_control_write,
77     .endianness = DEVICE_NATIVE_ENDIAN,
78 };
79 
80 static void intdbg_control_init(Object *obj)
81 {
82     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
83     IntegratorDebugState *s = INTEGRATOR_DEBUG(obj);
84 
85     memory_region_init_io(&s->iomem, obj, &intdbg_control_ops,
86                           NULL, "dbg-leds", 0x1000000);
87     sysbus_init_mmio(sd, &s->iomem);
88 }
89 
90 static const TypeInfo intdbg_info = {
91     .name          = TYPE_INTEGRATOR_DEBUG,
92     .parent        = TYPE_SYS_BUS_DEVICE,
93     .instance_size = sizeof(IntegratorDebugState),
94     .instance_init = intdbg_control_init,
95 };
96 
97 static void intdbg_register_types(void)
98 {
99     type_register_static(&intdbg_info);
100 }
101 
102 type_init(intdbg_register_types)
103