xref: /openbmc/qemu/hw/mips/mipssim.c (revision 05caa062)
1 /*
2  * QEMU/mipssim emulation
3  *
4  * Emulates a very simple machine model similar to the one used by the
5  * proprietary MIPS emulator.
6  *
7  * Copyright (c) 2007 Thiemo Seufer
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a copy
10  * of this software and associated documentation files (the "Software"), to deal
11  * in the Software without restriction, including without limitation the rights
12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13  * copies of the Software, and to permit persons to whom the Software is
14  * furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included in
17  * all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25  * THE SOFTWARE.
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu/datadir.h"
31 #include "exec/address-spaces.h"
32 #include "hw/clock.h"
33 #include "hw/mips/mips.h"
34 #include "hw/char/serial.h"
35 #include "net/net.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/boards.h"
38 #include "hw/loader.h"
39 #include "elf.h"
40 #include "hw/sysbus.h"
41 #include "hw/qdev-properties.h"
42 #include "qemu/error-report.h"
43 #include "sysemu/qtest.h"
44 #include "sysemu/reset.h"
45 #include "cpu.h"
46 
47 #define BIOS_SIZE (4 * MiB)
48 
49 #if TARGET_BIG_ENDIAN
50 #define BIOS_FILENAME "mips_bios.bin"
51 #else
52 #define BIOS_FILENAME "mipsel_bios.bin"
53 #endif
54 
55 static struct _loaderparams {
56     int ram_size;
57     const char *kernel_filename;
58     const char *kernel_cmdline;
59     const char *initrd_filename;
60 } loaderparams;
61 
62 typedef struct ResetData {
63     MIPSCPU *cpu;
64     uint64_t vector;
65 } ResetData;
66 
67 static uint64_t load_kernel(void)
68 {
69     uint64_t entry, kernel_high, initrd_size;
70     long kernel_size;
71     ram_addr_t initrd_offset;
72 
73     kernel_size = load_elf(loaderparams.kernel_filename, NULL,
74                            cpu_mips_kseg0_to_phys, NULL,
75                            &entry, NULL,
76                            &kernel_high, NULL, TARGET_BIG_ENDIAN,
77                            EM_MIPS, 1, 0);
78     if (kernel_size < 0) {
79         error_report("could not load kernel '%s': %s",
80                      loaderparams.kernel_filename,
81                      load_elf_strerror(kernel_size));
82         exit(1);
83     }
84 
85     /* load initrd */
86     initrd_size = 0;
87     initrd_offset = 0;
88     if (loaderparams.initrd_filename) {
89         initrd_size = get_image_size(loaderparams.initrd_filename);
90         if (initrd_size > 0) {
91             initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE);
92             if (initrd_offset + initrd_size > loaderparams.ram_size) {
93                 error_report("memory too small for initial ram disk '%s'",
94                              loaderparams.initrd_filename);
95                 exit(1);
96             }
97             initrd_size = load_image_targphys(loaderparams.initrd_filename,
98                 initrd_offset, loaderparams.ram_size - initrd_offset);
99         }
100         if (initrd_size == (target_ulong) -1) {
101             error_report("could not load initial ram disk '%s'",
102                          loaderparams.initrd_filename);
103             exit(1);
104         }
105     }
106     return entry;
107 }
108 
109 static void main_cpu_reset(void *opaque)
110 {
111     ResetData *s = (ResetData *)opaque;
112     CPUMIPSState *env = &s->cpu->env;
113 
114     cpu_reset(CPU(s->cpu));
115     env->active_tc.PC = s->vector & ~(target_ulong)1;
116     if (s->vector & 1) {
117         env->hflags |= MIPS_HFLAG_M16;
118     }
119 }
120 
121 static void mipsnet_init(int base, qemu_irq irq)
122 {
123     DeviceState *dev;
124     SysBusDevice *s;
125 
126     dev = qemu_create_nic_device("mipsnet", true, NULL);
127     if (!dev) {
128         return;
129     }
130 
131     s = SYS_BUS_DEVICE(dev);
132     sysbus_realize_and_unref(s, &error_fatal);
133     sysbus_connect_irq(s, 0, irq);
134     memory_region_add_subregion(get_system_io(),
135                                 base,
136                                 sysbus_mmio_get_region(s, 0));
137 }
138 
139 static void
140 mips_mipssim_init(MachineState *machine)
141 {
142     const char *kernel_filename = machine->kernel_filename;
143     const char *kernel_cmdline = machine->kernel_cmdline;
144     const char *initrd_filename = machine->initrd_filename;
145     char *filename;
146     MemoryRegion *address_space_mem = get_system_memory();
147     MemoryRegion *isa = g_new(MemoryRegion, 1);
148     MemoryRegion *bios = g_new(MemoryRegion, 1);
149     Clock *cpuclk;
150     MIPSCPU *cpu;
151     CPUMIPSState *env;
152     ResetData *reset_info;
153     int bios_size;
154 
155     cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
156 #ifdef TARGET_MIPS64
157     clock_set_hz(cpuclk, 6000000); /* 6 MHz */
158 #else
159     clock_set_hz(cpuclk, 12000000); /* 12 MHz */
160 #endif
161 
162     /* Init CPUs. */
163     cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
164     env = &cpu->env;
165 
166     reset_info = g_new0(ResetData, 1);
167     reset_info->cpu = cpu;
168     reset_info->vector = env->active_tc.PC;
169     qemu_register_reset(main_cpu_reset, reset_info);
170 
171     /* Allocate RAM. */
172     memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE,
173                            &error_fatal);
174 
175     memory_region_add_subregion(address_space_mem, 0, machine->ram);
176 
177     /* Map the BIOS / boot exception handler. */
178     memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
179     /* Load a BIOS / boot exception handler image. */
180     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
181     if (filename) {
182         bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
183         g_free(filename);
184     } else {
185         bios_size = -1;
186     }
187     if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
188         machine->firmware && !qtest_enabled()) {
189         /* Bail out if we have neither a kernel image nor boot vector code. */
190         error_report("Could not load MIPS bios '%s'", machine->firmware);
191         exit(1);
192     } else {
193         /* We have a boot vector start address. */
194         env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
195     }
196 
197     if (kernel_filename) {
198         loaderparams.ram_size = machine->ram_size;
199         loaderparams.kernel_filename = kernel_filename;
200         loaderparams.kernel_cmdline = kernel_cmdline;
201         loaderparams.initrd_filename = initrd_filename;
202         reset_info->vector = load_kernel();
203     }
204 
205     /* Init CPU internal devices. */
206     cpu_mips_irq_init_cpu(cpu);
207     cpu_mips_clock_init(cpu);
208 
209     /*
210      * Register 64 KB of ISA IO space at 0x1fd00000.  But without interrupts
211      * (except for the hardcoded serial port interrupt) -device cannot work,
212      * so do not expose the ISA bus to the user.
213      */
214     memory_region_init_alias(isa, NULL, "isa_mmio",
215                              get_system_io(), 0, 0x00010000);
216     memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
217 
218     /*
219      * A single 16450 sits at offset 0x3f8. It is attached to
220      * MIPS CPU INT2, which is interrupt 4.
221      */
222     if (serial_hd(0)) {
223         DeviceState *dev = qdev_new(TYPE_SERIAL_MM);
224 
225         qdev_prop_set_chr(dev, "chardev", serial_hd(0));
226         qdev_prop_set_uint8(dev, "regshift", 0);
227         qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
228         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
229         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
230         memory_region_add_subregion(get_system_io(), 0x3f8,
231                       sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
232     }
233 
234     /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
235     mipsnet_init(0x4200, env->irq[2]);
236 }
237 
238 static void mips_mipssim_machine_init(MachineClass *mc)
239 {
240     mc->desc = "MIPS MIPSsim platform";
241     mc->init = mips_mipssim_init;
242 #ifdef TARGET_MIPS64
243     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf");
244 #else
245     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
246 #endif
247     mc->default_ram_id = "mips_mipssim.ram";
248 }
249 
250 DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)
251