xref: /openbmc/qemu/hw/mips/mips_int.c (revision 327d4b7f)
1 /*
2  * QEMU MIPS interrupt support
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22 
23 #include "qemu/osdep.h"
24 #include "qemu/main-loop.h"
25 #include "hw/irq.h"
26 #include "hw/mips/cpudevs.h"
27 #include "sysemu/kvm.h"
28 #include "kvm_mips.h"
29 
30 static void cpu_mips_irq_request(void *opaque, int irq, int level)
31 {
32     MIPSCPU *cpu = opaque;
33     CPUMIPSState *env = &cpu->env;
34     CPUState *cs = CPU(cpu);
35     bool locked = false;
36 
37     if (irq < 0 || irq > 7) {
38         return;
39     }
40 
41     /* Make sure locking works even if BQL is already held by the caller */
42     if (!qemu_mutex_iothread_locked()) {
43         locked = true;
44         qemu_mutex_lock_iothread();
45     }
46 
47     if (level) {
48         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
49     } else {
50         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
51     }
52 
53     if (kvm_enabled() && (irq == 2 || irq == 3)) {
54         kvm_mips_set_interrupt(cpu, irq, level);
55     }
56 
57     if (env->CP0_Cause & CP0Ca_IP_mask) {
58         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
59     } else {
60         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
61     }
62 
63     if (locked) {
64         qemu_mutex_unlock_iothread();
65     }
66 }
67 
68 void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
69 {
70     CPUMIPSState *env = &cpu->env;
71     qemu_irq *qi;
72     int i;
73 
74     qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8);
75     for (i = 0; i < 8; i++) {
76         env->irq[i] = qi[i];
77     }
78     g_free(qi);
79 }
80 
81 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
82 {
83     if (irq < 0 || irq > 2) {
84         return;
85     }
86 
87     qemu_set_irq(env->irq[irq], level);
88 }
89