1 /* 2 * QEMU Malta board support 3 * 4 * Copyright (c) 2006 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu-common.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/clock.h" 31 #include "hw/southbridge/piix.h" 32 #include "hw/isa/superio.h" 33 #include "hw/char/serial.h" 34 #include "net/net.h" 35 #include "hw/boards.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/block/flash.h" 38 #include "hw/mips/mips.h" 39 #include "hw/mips/cpudevs.h" 40 #include "hw/pci/pci.h" 41 #include "sysemu/sysemu.h" 42 #include "sysemu/arch_init.h" 43 #include "qemu/log.h" 44 #include "hw/mips/bios.h" 45 #include "hw/ide.h" 46 #include "hw/irq.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "exec/address-spaces.h" 50 #include "qom/object.h" 51 #include "hw/sysbus.h" /* SysBusDevice */ 52 #include "qemu/host-utils.h" 53 #include "sysemu/qtest.h" 54 #include "sysemu/reset.h" 55 #include "sysemu/runstate.h" 56 #include "qapi/error.h" 57 #include "qemu/error-report.h" 58 #include "hw/misc/empty_slot.h" 59 #include "sysemu/kvm.h" 60 #include "hw/semihosting/semihost.h" 61 #include "hw/mips/cps.h" 62 #include "hw/qdev-clock.h" 63 64 #define ENVP_ADDR 0x80002000l 65 #define ENVP_NB_ENTRIES 16 66 #define ENVP_ENTRY_SIZE 256 67 68 /* Hardware addresses */ 69 #define FLASH_ADDRESS 0x1e000000ULL 70 #define FPGA_ADDRESS 0x1f000000ULL 71 #define RESET_ADDRESS 0x1fc00000ULL 72 73 #define FLASH_SIZE 0x400000 74 75 #define MAX_IDE_BUS 2 76 77 typedef struct { 78 MemoryRegion iomem; 79 MemoryRegion iomem_lo; /* 0 - 0x900 */ 80 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ 81 uint32_t leds; 82 uint32_t brk; 83 uint32_t gpout; 84 uint32_t i2cin; 85 uint32_t i2coe; 86 uint32_t i2cout; 87 uint32_t i2csel; 88 CharBackend display; 89 char display_text[9]; 90 SerialMM *uart; 91 bool display_inited; 92 } MaltaFPGAState; 93 94 #define TYPE_MIPS_MALTA "mips-malta" 95 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) 96 97 struct MaltaState { 98 SysBusDevice parent_obj; 99 100 Clock *cpuclk; 101 MIPSCPSState cps; 102 qemu_irq i8259[ISA_NUM_IRQS]; 103 }; 104 105 static struct _loaderparams { 106 int ram_size, ram_low_size; 107 const char *kernel_filename; 108 const char *kernel_cmdline; 109 const char *initrd_filename; 110 } loaderparams; 111 112 /* Malta FPGA */ 113 static void malta_fpga_update_display(void *opaque) 114 { 115 char leds_text[9]; 116 int i; 117 MaltaFPGAState *s = opaque; 118 119 for (i = 7 ; i >= 0 ; i--) { 120 if (s->leds & (1 << i)) { 121 leds_text[i] = '#'; 122 } else { 123 leds_text[i] = ' '; 124 } 125 } 126 leds_text[8] = '\0'; 127 128 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", 129 leds_text); 130 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", 131 s->display_text); 132 } 133 134 /* 135 * EEPROM 24C01 / 24C02 emulation. 136 * 137 * Emulation for serial EEPROMs: 138 * 24C01 - 1024 bit (128 x 8) 139 * 24C02 - 2048 bit (256 x 8) 140 * 141 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. 142 */ 143 144 #if defined(DEBUG) 145 # define logout(fmt, ...) \ 146 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) 147 #else 148 # define logout(fmt, ...) ((void)0) 149 #endif 150 151 struct _eeprom24c0x_t { 152 uint8_t tick; 153 uint8_t address; 154 uint8_t command; 155 uint8_t ack; 156 uint8_t scl; 157 uint8_t sda; 158 uint8_t data; 159 /* uint16_t size; */ 160 uint8_t contents[256]; 161 }; 162 163 typedef struct _eeprom24c0x_t eeprom24c0x_t; 164 165 static eeprom24c0x_t spd_eeprom = { 166 .contents = { 167 /* 00000000: */ 168 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 169 /* 00000008: */ 170 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 171 /* 00000010: */ 172 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 173 /* 00000018: */ 174 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 175 /* 00000020: */ 176 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 177 /* 00000028: */ 178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 179 /* 00000030: */ 180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 181 /* 00000038: */ 182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 183 /* 00000040: */ 184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 185 /* 00000048: */ 186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 /* 00000050: */ 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 189 /* 00000058: */ 190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 191 /* 00000060: */ 192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 193 /* 00000068: */ 194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 195 /* 00000070: */ 196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 197 /* 00000078: */ 198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 199 }, 200 }; 201 202 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 203 { 204 enum { SDR = 0x4, DDR2 = 0x8 } type; 205 uint8_t *spd = spd_eeprom.contents; 206 uint8_t nbanks = 0; 207 uint16_t density = 0; 208 int i; 209 210 /* work in terms of MB */ 211 ram_size /= MiB; 212 213 while ((ram_size >= 4) && (nbanks <= 2)) { 214 int sz_log2 = MIN(31 - clz32(ram_size), 14); 215 nbanks++; 216 density |= 1 << (sz_log2 - 2); 217 ram_size -= 1 << sz_log2; 218 } 219 220 /* split to 2 banks if possible */ 221 if ((nbanks == 1) && (density > 1)) { 222 nbanks++; 223 density >>= 1; 224 } 225 226 if (density & 0xff00) { 227 density = (density & 0xe0) | ((density >> 8) & 0x1f); 228 type = DDR2; 229 } else if (!(density & 0x1f)) { 230 type = DDR2; 231 } else { 232 type = SDR; 233 } 234 235 if (ram_size) { 236 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 237 " of SDRAM", ram_size); 238 } 239 240 /* fill in SPD memory information */ 241 spd[2] = type; 242 spd[5] = nbanks; 243 spd[31] = density; 244 245 /* checksum */ 246 spd[63] = 0; 247 for (i = 0; i < 63; i++) { 248 spd[63] += spd[i]; 249 } 250 251 /* copy for SMBUS */ 252 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 253 } 254 255 static void generate_eeprom_serial(uint8_t *eeprom) 256 { 257 int i, pos = 0; 258 uint8_t mac[6] = { 0x00 }; 259 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 260 261 /* version */ 262 eeprom[pos++] = 0x01; 263 264 /* count */ 265 eeprom[pos++] = 0x02; 266 267 /* MAC address */ 268 eeprom[pos++] = 0x01; /* MAC */ 269 eeprom[pos++] = 0x06; /* length */ 270 memcpy(&eeprom[pos], mac, sizeof(mac)); 271 pos += sizeof(mac); 272 273 /* serial number */ 274 eeprom[pos++] = 0x02; /* serial */ 275 eeprom[pos++] = 0x05; /* length */ 276 memcpy(&eeprom[pos], sn, sizeof(sn)); 277 pos += sizeof(sn); 278 279 /* checksum */ 280 eeprom[pos] = 0; 281 for (i = 0; i < pos; i++) { 282 eeprom[pos] += eeprom[i]; 283 } 284 } 285 286 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) 287 { 288 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", 289 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); 290 return eeprom->sda; 291 } 292 293 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) 294 { 295 if (eeprom->scl && scl && (eeprom->sda != sda)) { 296 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", 297 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, 298 sda ? "stop" : "start"); 299 if (!sda) { 300 eeprom->tick = 1; 301 eeprom->command = 0; 302 } 303 } else if (eeprom->tick == 0 && !eeprom->ack) { 304 /* Waiting for start. */ 305 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", 306 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 307 } else if (!eeprom->scl && scl) { 308 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", 309 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 310 if (eeprom->ack) { 311 logout("\ti2c ack bit = 0\n"); 312 sda = 0; 313 eeprom->ack = 0; 314 } else if (eeprom->sda == sda) { 315 uint8_t bit = (sda != 0); 316 logout("\ti2c bit = %d\n", bit); 317 if (eeprom->tick < 9) { 318 eeprom->command <<= 1; 319 eeprom->command += bit; 320 eeprom->tick++; 321 if (eeprom->tick == 9) { 322 logout("\tcommand 0x%04x, %s\n", eeprom->command, 323 bit ? "read" : "write"); 324 eeprom->ack = 1; 325 } 326 } else if (eeprom->tick < 17) { 327 if (eeprom->command & 1) { 328 sda = ((eeprom->data & 0x80) != 0); 329 } 330 eeprom->address <<= 1; 331 eeprom->address += bit; 332 eeprom->tick++; 333 eeprom->data <<= 1; 334 if (eeprom->tick == 17) { 335 eeprom->data = eeprom->contents[eeprom->address]; 336 logout("\taddress 0x%04x, data 0x%02x\n", 337 eeprom->address, eeprom->data); 338 eeprom->ack = 1; 339 eeprom->tick = 0; 340 } 341 } else if (eeprom->tick >= 17) { 342 sda = 0; 343 } 344 } else { 345 logout("\tsda changed with raising scl\n"); 346 } 347 } else { 348 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, 349 scl, eeprom->sda, sda); 350 } 351 eeprom->scl = scl; 352 eeprom->sda = sda; 353 } 354 355 static uint64_t malta_fpga_read(void *opaque, hwaddr addr, 356 unsigned size) 357 { 358 MaltaFPGAState *s = opaque; 359 uint32_t val = 0; 360 uint32_t saddr; 361 362 saddr = (addr & 0xfffff); 363 364 switch (saddr) { 365 366 /* SWITCH Register */ 367 case 0x00200: 368 val = 0x00000000; 369 break; 370 371 /* STATUS Register */ 372 case 0x00208: 373 #ifdef TARGET_WORDS_BIGENDIAN 374 val = 0x00000012; 375 #else 376 val = 0x00000010; 377 #endif 378 break; 379 380 /* JMPRS Register */ 381 case 0x00210: 382 val = 0x00; 383 break; 384 385 /* LEDBAR Register */ 386 case 0x00408: 387 val = s->leds; 388 break; 389 390 /* BRKRES Register */ 391 case 0x00508: 392 val = s->brk; 393 break; 394 395 /* UART Registers are handled directly by the serial device */ 396 397 /* GPOUT Register */ 398 case 0x00a00: 399 val = s->gpout; 400 break; 401 402 /* XXX: implement a real I2C controller */ 403 404 /* GPINP Register */ 405 case 0x00a08: 406 /* IN = OUT until a real I2C control is implemented */ 407 if (s->i2csel) { 408 val = s->i2cout; 409 } else { 410 val = 0x00; 411 } 412 break; 413 414 /* I2CINP Register */ 415 case 0x00b00: 416 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); 417 break; 418 419 /* I2COE Register */ 420 case 0x00b08: 421 val = s->i2coe; 422 break; 423 424 /* I2COUT Register */ 425 case 0x00b10: 426 val = s->i2cout; 427 break; 428 429 /* I2CSEL Register */ 430 case 0x00b18: 431 val = s->i2csel; 432 break; 433 434 default: 435 qemu_log_mask(LOG_GUEST_ERROR, 436 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", 437 addr); 438 break; 439 } 440 return val; 441 } 442 443 static void malta_fpga_write(void *opaque, hwaddr addr, 444 uint64_t val, unsigned size) 445 { 446 MaltaFPGAState *s = opaque; 447 uint32_t saddr; 448 449 saddr = (addr & 0xfffff); 450 451 switch (saddr) { 452 453 /* SWITCH Register */ 454 case 0x00200: 455 break; 456 457 /* JMPRS Register */ 458 case 0x00210: 459 break; 460 461 /* LEDBAR Register */ 462 case 0x00408: 463 s->leds = val & 0xff; 464 malta_fpga_update_display(s); 465 break; 466 467 /* ASCIIWORD Register */ 468 case 0x00410: 469 snprintf(s->display_text, 9, "%08X", (uint32_t)val); 470 malta_fpga_update_display(s); 471 break; 472 473 /* ASCIIPOS0 to ASCIIPOS7 Registers */ 474 case 0x00418: 475 case 0x00420: 476 case 0x00428: 477 case 0x00430: 478 case 0x00438: 479 case 0x00440: 480 case 0x00448: 481 case 0x00450: 482 s->display_text[(saddr - 0x00418) >> 3] = (char) val; 483 malta_fpga_update_display(s); 484 break; 485 486 /* SOFTRES Register */ 487 case 0x00500: 488 if (val == 0x42) { 489 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 490 } 491 break; 492 493 /* BRKRES Register */ 494 case 0x00508: 495 s->brk = val & 0xff; 496 break; 497 498 /* UART Registers are handled directly by the serial device */ 499 500 /* GPOUT Register */ 501 case 0x00a00: 502 s->gpout = val & 0xff; 503 break; 504 505 /* I2COE Register */ 506 case 0x00b08: 507 s->i2coe = val & 0x03; 508 break; 509 510 /* I2COUT Register */ 511 case 0x00b10: 512 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); 513 s->i2cout = val; 514 break; 515 516 /* I2CSEL Register */ 517 case 0x00b18: 518 s->i2csel = val & 0x01; 519 break; 520 521 default: 522 qemu_log_mask(LOG_GUEST_ERROR, 523 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", 524 addr); 525 break; 526 } 527 } 528 529 static const MemoryRegionOps malta_fpga_ops = { 530 .read = malta_fpga_read, 531 .write = malta_fpga_write, 532 .endianness = DEVICE_NATIVE_ENDIAN, 533 }; 534 535 static void malta_fpga_reset(void *opaque) 536 { 537 MaltaFPGAState *s = opaque; 538 539 s->leds = 0x00; 540 s->brk = 0x0a; 541 s->gpout = 0x00; 542 s->i2cin = 0x3; 543 s->i2coe = 0x0; 544 s->i2cout = 0x3; 545 s->i2csel = 0x1; 546 547 s->display_text[8] = '\0'; 548 snprintf(s->display_text, 9, " "); 549 } 550 551 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) 552 { 553 MaltaFPGAState *s = opaque; 554 555 if (event == CHR_EVENT_OPENED && !s->display_inited) { 556 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); 557 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 558 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 559 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 560 qemu_chr_fe_printf(&s->display, "\n"); 561 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); 562 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 563 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 564 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 565 s->display_inited = true; 566 } 567 } 568 569 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, 570 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) 571 { 572 MaltaFPGAState *s; 573 Chardev *chr; 574 575 s = g_new0(MaltaFPGAState, 1); 576 577 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, 578 "malta-fpga", 0x100000); 579 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", 580 &s->iomem, 0, 0x900); 581 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", 582 &s->iomem, 0xa00, 0x100000 - 0xa00); 583 584 memory_region_add_subregion(address_space, base, &s->iomem_lo); 585 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); 586 587 chr = qemu_chr_new("fpga", "vc:320x200", NULL); 588 qemu_chr_fe_init(&s->display, chr, NULL); 589 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, 590 malta_fgpa_display_event, NULL, s, NULL, true); 591 592 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, 593 230400, uart_chr, DEVICE_NATIVE_ENDIAN); 594 595 malta_fpga_reset(s); 596 qemu_register_reset(malta_fpga_reset, s); 597 598 return s; 599 } 600 601 /* Network support */ 602 static void network_init(PCIBus *pci_bus) 603 { 604 int i; 605 606 for (i = 0; i < nb_nics; i++) { 607 NICInfo *nd = &nd_table[i]; 608 const char *default_devaddr = NULL; 609 610 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) 611 /* The malta board has a PCNet card using PCI SLOT 11 */ 612 default_devaddr = "0b"; 613 614 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); 615 } 616 } 617 618 static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, 619 int64_t kernel_entry) 620 { 621 uint16_t *p; 622 623 /* Small bootloader */ 624 p = (uint16_t *)base; 625 626 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) 627 #define NM_HI2(VAL) \ 628 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) 629 #define NM_LO(VAL) ((VAL) & 0xfff) 630 631 stw_p(p++, 0x2800); stw_p(p++, 0x001c); 632 /* bc to_here */ 633 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 634 /* nop */ 635 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 636 /* nop */ 637 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 638 /* nop */ 639 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 640 /* nop */ 641 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 642 /* nop */ 643 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 644 /* nop */ 645 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 646 /* nop */ 647 648 /* to_here: */ 649 if (semihosting_get_argc()) { 650 /* Preserve a0 content as arguments have been passed */ 651 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 652 /* nop */ 653 } else { 654 stw_p(p++, 0x0080); stw_p(p++, 0x0002); 655 /* li a0,2 */ 656 } 657 658 stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); 659 660 stw_p(p++, NM_HI2(ENVP_ADDR - 64)); 661 /* lui sp,%hi(ENVP_ADDR - 64) */ 662 663 stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); 664 /* ori sp,sp,%lo(ENVP_ADDR - 64) */ 665 666 stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); 667 668 stw_p(p++, NM_HI2(ENVP_ADDR)); 669 /* lui a1,%hi(ENVP_ADDR) */ 670 671 stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); 672 /* ori a1,a1,%lo(ENVP_ADDR) */ 673 674 stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); 675 676 stw_p(p++, NM_HI2(ENVP_ADDR + 8)); 677 /* lui a2,%hi(ENVP_ADDR + 8) */ 678 679 stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); 680 /* ori a2,a2,%lo(ENVP_ADDR + 8) */ 681 682 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); 683 684 stw_p(p++, NM_HI2(loaderparams.ram_low_size)); 685 /* lui a3,%hi(loaderparams.ram_low_size) */ 686 687 stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); 688 /* ori a3,a3,%lo(loaderparams.ram_low_size) */ 689 690 /* 691 * Load BAR registers as done by YAMON: 692 * 693 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 694 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000 695 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000 696 * 697 */ 698 stw_p(p++, 0xe040); stw_p(p++, 0x0681); 699 /* lui t1, %hi(0xb4000000) */ 700 701 #ifdef TARGET_WORDS_BIGENDIAN 702 703 stw_p(p++, 0xe020); stw_p(p++, 0x0be1); 704 /* lui t0, %hi(0xdf000000) */ 705 706 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */ 707 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 708 /* sw t0, 0x68(t1) */ 709 710 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 711 /* lui t1, %hi(0xbbe00000) */ 712 713 stw_p(p++, 0xe020); stw_p(p++, 0x0801); 714 /* lui t0, %hi(0xc0000000) */ 715 716 /* 0x48 corresponds to GT_PCI0IOLD */ 717 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 718 /* sw t0, 0x48(t1) */ 719 720 stw_p(p++, 0xe020); stw_p(p++, 0x0800); 721 /* lui t0, %hi(0x40000000) */ 722 723 /* 0x50 corresponds to GT_PCI0IOHD */ 724 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 725 /* sw t0, 0x50(t1) */ 726 727 stw_p(p++, 0xe020); stw_p(p++, 0x0001); 728 /* lui t0, %hi(0x80000000) */ 729 730 /* 0x58 corresponds to GT_PCI0M0LD */ 731 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 732 /* sw t0, 0x58(t1) */ 733 734 stw_p(p++, 0xe020); stw_p(p++, 0x07e0); 735 /* lui t0, %hi(0x3f000000) */ 736 737 /* 0x60 corresponds to GT_PCI0M0HD */ 738 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 739 /* sw t0, 0x60(t1) */ 740 741 stw_p(p++, 0xe020); stw_p(p++, 0x0821); 742 /* lui t0, %hi(0xc1000000) */ 743 744 /* 0x80 corresponds to GT_PCI0M1LD */ 745 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 746 /* sw t0, 0x80(t1) */ 747 748 stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); 749 /* lui t0, %hi(0x5e000000) */ 750 751 #else 752 753 stw_p(p++, 0x0020); stw_p(p++, 0x00df); 754 /* addiu[32] t0, $0, 0xdf */ 755 756 /* 0x68 corresponds to GT_ISD */ 757 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 758 /* sw t0, 0x68(t1) */ 759 760 /* Use kseg2 remapped address 0x1be00000 */ 761 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 762 /* lui t1, %hi(0xbbe00000) */ 763 764 stw_p(p++, 0x0020); stw_p(p++, 0x00c0); 765 /* addiu[32] t0, $0, 0xc0 */ 766 767 /* 0x48 corresponds to GT_PCI0IOLD */ 768 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 769 /* sw t0, 0x48(t1) */ 770 771 stw_p(p++, 0x0020); stw_p(p++, 0x0040); 772 /* addiu[32] t0, $0, 0x40 */ 773 774 /* 0x50 corresponds to GT_PCI0IOHD */ 775 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 776 /* sw t0, 0x50(t1) */ 777 778 stw_p(p++, 0x0020); stw_p(p++, 0x0080); 779 /* addiu[32] t0, $0, 0x80 */ 780 781 /* 0x58 corresponds to GT_PCI0M0LD */ 782 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 783 /* sw t0, 0x58(t1) */ 784 785 stw_p(p++, 0x0020); stw_p(p++, 0x003f); 786 /* addiu[32] t0, $0, 0x3f */ 787 788 /* 0x60 corresponds to GT_PCI0M0HD */ 789 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 790 /* sw t0, 0x60(t1) */ 791 792 stw_p(p++, 0x0020); stw_p(p++, 0x00c1); 793 /* addiu[32] t0, $0, 0xc1 */ 794 795 /* 0x80 corresponds to GT_PCI0M1LD */ 796 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 797 /* sw t0, 0x80(t1) */ 798 799 stw_p(p++, 0x0020); stw_p(p++, 0x005e); 800 /* addiu[32] t0, $0, 0x5e */ 801 802 #endif 803 804 /* 0x88 corresponds to GT_PCI0M1HD */ 805 stw_p(p++, 0x8422); stw_p(p++, 0x9088); 806 /* sw t0, 0x88(t1) */ 807 808 stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); 809 810 stw_p(p++, NM_HI2(kernel_entry)); 811 /* lui t9,%hi(kernel_entry) */ 812 813 stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); 814 /* ori t9,t9,%lo(kernel_entry) */ 815 816 stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); 817 /* jalrc t8 */ 818 } 819 820 /* 821 * ROM and pseudo bootloader 822 * 823 * The following code implements a very very simple bootloader. It first 824 * loads the registers a0 to a3 to the values expected by the OS, and 825 * then jump at the kernel address. 826 * 827 * The bootloader should pass the locations of the kernel arguments and 828 * environment variables tables. Those tables contain the 32-bit address 829 * of NULL terminated strings. The environment variables table should be 830 * terminated by a NULL address. 831 * 832 * For a simpler implementation, the number of kernel arguments is fixed 833 * to two (the name of the kernel and the command line), and the two 834 * tables are actually the same one. 835 * 836 * The registers a0 to a3 should contain the following values: 837 * a0 - number of kernel arguments 838 * a1 - 32-bit address of the kernel arguments table 839 * a2 - 32-bit address of the environment variables table 840 * a3 - RAM size in bytes 841 */ 842 static void write_bootloader(uint8_t *base, int64_t run_addr, 843 int64_t kernel_entry) 844 { 845 uint32_t *p; 846 847 /* Small bootloader */ 848 p = (uint32_t *)base; 849 850 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ 851 ((run_addr + 0x580) & 0x0fffffff) >> 2); 852 stl_p(p++, 0x00000000); /* nop */ 853 854 /* YAMON service vector */ 855 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ 856 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ 857 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ 858 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ 859 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ 860 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ 861 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ 862 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ 863 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ 864 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ 865 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ 866 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ 867 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ 868 869 870 /* Second part of the bootloader */ 871 p = (uint32_t *) (base + 0x580); 872 873 if (semihosting_get_argc()) { 874 /* Preserve a0 content as arguments have been passed */ 875 stl_p(p++, 0x00000000); /* nop */ 876 } else { 877 stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ 878 } 879 880 /* lui sp, high(ENVP_ADDR) */ 881 stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); 882 /* ori sp, sp, low(ENVP_ADDR) */ 883 stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); 884 /* lui a1, high(ENVP_ADDR) */ 885 stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); 886 /* ori a1, a1, low(ENVP_ADDR) */ 887 stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); 888 /* lui a2, high(ENVP_ADDR + 8) */ 889 stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); 890 /* ori a2, a2, low(ENVP_ADDR + 8) */ 891 stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); 892 /* lui a3, high(ram_low_size) */ 893 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); 894 /* ori a3, a3, low(ram_low_size) */ 895 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); 896 897 /* Load BAR registers as done by YAMON */ 898 stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ 899 900 #ifdef TARGET_WORDS_BIGENDIAN 901 stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ 902 #else 903 stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ 904 #endif 905 stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ 906 907 stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ 908 909 #ifdef TARGET_WORDS_BIGENDIAN 910 stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ 911 #else 912 stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ 913 #endif 914 stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ 915 #ifdef TARGET_WORDS_BIGENDIAN 916 stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ 917 #else 918 stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ 919 #endif 920 stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ 921 922 #ifdef TARGET_WORDS_BIGENDIAN 923 stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ 924 #else 925 stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ 926 #endif 927 stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ 928 #ifdef TARGET_WORDS_BIGENDIAN 929 stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ 930 #else 931 stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ 932 #endif 933 stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ 934 935 #ifdef TARGET_WORDS_BIGENDIAN 936 stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ 937 #else 938 stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ 939 #endif 940 stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ 941 #ifdef TARGET_WORDS_BIGENDIAN 942 stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ 943 #else 944 stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ 945 #endif 946 stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ 947 948 /* Jump to kernel code */ 949 stl_p(p++, 0x3c1f0000 | 950 ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ 951 stl_p(p++, 0x37ff0000 | 952 (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ 953 stl_p(p++, 0x03e00009); /* jalr ra */ 954 stl_p(p++, 0x00000000); /* nop */ 955 956 /* YAMON subroutines */ 957 p = (uint32_t *) (base + 0x800); 958 stl_p(p++, 0x03e00009); /* jalr ra */ 959 stl_p(p++, 0x24020000); /* li v0,0 */ 960 /* 808 YAMON print */ 961 stl_p(p++, 0x03e06821); /* move t5,ra */ 962 stl_p(p++, 0x00805821); /* move t3,a0 */ 963 stl_p(p++, 0x00a05021); /* move t2,a1 */ 964 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 965 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 966 stl_p(p++, 0x10800005); /* beqz a0,834 */ 967 stl_p(p++, 0x00000000); /* nop */ 968 stl_p(p++, 0x0ff0021c); /* jal 870 */ 969 stl_p(p++, 0x00000000); /* nop */ 970 stl_p(p++, 0x1000fff9); /* b 814 */ 971 stl_p(p++, 0x00000000); /* nop */ 972 stl_p(p++, 0x01a00009); /* jalr t5 */ 973 stl_p(p++, 0x01602021); /* move a0,t3 */ 974 /* 0x83c YAMON print_count */ 975 stl_p(p++, 0x03e06821); /* move t5,ra */ 976 stl_p(p++, 0x00805821); /* move t3,a0 */ 977 stl_p(p++, 0x00a05021); /* move t2,a1 */ 978 stl_p(p++, 0x00c06021); /* move t4,a2 */ 979 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 980 stl_p(p++, 0x0ff0021c); /* jal 870 */ 981 stl_p(p++, 0x00000000); /* nop */ 982 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 983 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ 984 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ 985 stl_p(p++, 0x00000000); /* nop */ 986 stl_p(p++, 0x01a00009); /* jalr t5 */ 987 stl_p(p++, 0x01602021); /* move a0,t3 */ 988 /* 0x870 */ 989 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ 990 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ 991 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ 992 stl_p(p++, 0x00000000); /* nop */ 993 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ 994 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ 995 stl_p(p++, 0x00000000); /* nop */ 996 stl_p(p++, 0x03e00009); /* jalr ra */ 997 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ 998 999 } 1000 1001 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, 1002 const char *string, ...) 1003 { 1004 va_list ap; 1005 int32_t table_addr; 1006 1007 if (index >= ENVP_NB_ENTRIES) { 1008 return; 1009 } 1010 1011 if (string == NULL) { 1012 prom_buf[index] = 0; 1013 return; 1014 } 1015 1016 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 1017 prom_buf[index] = tswap32(ENVP_ADDR + table_addr); 1018 1019 va_start(ap, string); 1020 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 1021 va_end(ap); 1022 } 1023 1024 /* Kernel */ 1025 static int64_t load_kernel(void) 1026 { 1027 int64_t kernel_entry, kernel_high, initrd_size; 1028 long kernel_size; 1029 ram_addr_t initrd_offset; 1030 int big_endian; 1031 uint32_t *prom_buf; 1032 long prom_size; 1033 int prom_index = 0; 1034 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); 1035 1036 #ifdef TARGET_WORDS_BIGENDIAN 1037 big_endian = 1; 1038 #else 1039 big_endian = 0; 1040 #endif 1041 1042 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 1043 cpu_mips_kseg0_to_phys, NULL, 1044 (uint64_t *)&kernel_entry, NULL, 1045 (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS, 1046 1, 0); 1047 if (kernel_size < 0) { 1048 error_report("could not load kernel '%s': %s", 1049 loaderparams.kernel_filename, 1050 load_elf_strerror(kernel_size)); 1051 exit(1); 1052 } 1053 1054 /* Check where the kernel has been linked */ 1055 if (kernel_entry & 0x80000000ll) { 1056 if (kvm_enabled()) { 1057 error_report("KVM guest kernels must be linked in useg. " 1058 "Did you forget to enable CONFIG_KVM_GUEST?"); 1059 exit(1); 1060 } 1061 1062 xlate_to_kseg0 = cpu_mips_phys_to_kseg0; 1063 } else { 1064 /* if kernel entry is in useg it is probably a KVM T&E kernel */ 1065 mips_um_ksegs_enable(); 1066 1067 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; 1068 } 1069 1070 /* load initrd */ 1071 initrd_size = 0; 1072 initrd_offset = 0; 1073 if (loaderparams.initrd_filename) { 1074 initrd_size = get_image_size(loaderparams.initrd_filename); 1075 if (initrd_size > 0) { 1076 /* 1077 * The kernel allocates the bootmap memory in the low memory after 1078 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB 1079 * pages. 1080 */ 1081 initrd_offset = ROUND_UP(loaderparams.ram_low_size 1082 - (initrd_size + 128 * KiB), 1083 INITRD_PAGE_SIZE); 1084 if (kernel_high >= initrd_offset) { 1085 error_report("memory too small for initial ram disk '%s'", 1086 loaderparams.initrd_filename); 1087 exit(1); 1088 } 1089 initrd_size = load_image_targphys(loaderparams.initrd_filename, 1090 initrd_offset, 1091 loaderparams.ram_size - initrd_offset); 1092 } 1093 if (initrd_size == (target_ulong) -1) { 1094 error_report("could not load initial ram disk '%s'", 1095 loaderparams.initrd_filename); 1096 exit(1); 1097 } 1098 } 1099 1100 /* Setup prom parameters. */ 1101 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 1102 prom_buf = g_malloc(prom_size); 1103 1104 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); 1105 if (initrd_size > 0) { 1106 prom_set(prom_buf, prom_index++, 1107 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 1108 xlate_to_kseg0(NULL, initrd_offset), 1109 initrd_size, loaderparams.kernel_cmdline); 1110 } else { 1111 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); 1112 } 1113 1114 prom_set(prom_buf, prom_index++, "memsize"); 1115 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); 1116 1117 prom_set(prom_buf, prom_index++, "ememsize"); 1118 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); 1119 1120 prom_set(prom_buf, prom_index++, "modetty0"); 1121 prom_set(prom_buf, prom_index++, "38400n8r"); 1122 prom_set(prom_buf, prom_index++, NULL); 1123 1124 rom_add_blob_fixed("prom", prom_buf, prom_size, 1125 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); 1126 1127 g_free(prom_buf); 1128 return kernel_entry; 1129 } 1130 1131 static void malta_mips_config(MIPSCPU *cpu) 1132 { 1133 MachineState *ms = MACHINE(qdev_get_machine()); 1134 unsigned int smp_cpus = ms->smp.cpus; 1135 CPUMIPSState *env = &cpu->env; 1136 CPUState *cs = CPU(cpu); 1137 1138 env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | 1139 ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); 1140 } 1141 1142 static void main_cpu_reset(void *opaque) 1143 { 1144 MIPSCPU *cpu = opaque; 1145 CPUMIPSState *env = &cpu->env; 1146 1147 cpu_reset(CPU(cpu)); 1148 1149 /* 1150 * The bootloader does not need to be rewritten as it is located in a 1151 * read only location. The kernel location and the arguments table 1152 * location does not change. 1153 */ 1154 if (loaderparams.kernel_filename) { 1155 env->CP0_Status &= ~(1 << CP0St_ERL); 1156 } 1157 1158 malta_mips_config(cpu); 1159 1160 if (kvm_enabled()) { 1161 /* Start running from the bootloader we wrote to end of RAM */ 1162 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; 1163 } 1164 } 1165 1166 static void create_cpu_without_cps(MachineState *ms, MaltaState *s, 1167 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1168 { 1169 CPUMIPSState *env; 1170 MIPSCPU *cpu; 1171 int i; 1172 1173 for (i = 0; i < ms->smp.cpus; i++) { 1174 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); 1175 1176 /* Init internal devices */ 1177 cpu_mips_irq_init_cpu(cpu); 1178 cpu_mips_clock_init(cpu); 1179 qemu_register_reset(main_cpu_reset, cpu); 1180 } 1181 1182 cpu = MIPS_CPU(first_cpu); 1183 env = &cpu->env; 1184 *i8259_irq = env->irq[2]; 1185 *cbus_irq = env->irq[4]; 1186 } 1187 1188 static void create_cps(MachineState *ms, MaltaState *s, 1189 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1190 { 1191 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1192 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1193 &error_fatal); 1194 object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1195 &error_fatal); 1196 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); 1197 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1198 1199 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1200 1201 *i8259_irq = get_cps_irq(&s->cps, 3); 1202 *cbus_irq = NULL; 1203 } 1204 1205 static void mips_create_cpu(MachineState *ms, MaltaState *s, 1206 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1207 { 1208 if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { 1209 create_cps(ms, s, cbus_irq, i8259_irq); 1210 } else { 1211 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); 1212 } 1213 } 1214 1215 static 1216 void mips_malta_init(MachineState *machine) 1217 { 1218 ram_addr_t ram_size = machine->ram_size; 1219 ram_addr_t ram_low_size; 1220 const char *kernel_filename = machine->kernel_filename; 1221 const char *kernel_cmdline = machine->kernel_cmdline; 1222 const char *initrd_filename = machine->initrd_filename; 1223 char *filename; 1224 PFlashCFI01 *fl; 1225 MemoryRegion *system_memory = get_system_memory(); 1226 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1227 MemoryRegion *ram_low_postio; 1228 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); 1229 const size_t smbus_eeprom_size = 8 * 256; 1230 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 1231 int64_t kernel_entry, bootloader_run_addr; 1232 PCIBus *pci_bus; 1233 ISABus *isa_bus; 1234 qemu_irq cbus_irq, i8259_irq; 1235 I2CBus *smbus; 1236 DriveInfo *dinfo; 1237 int fl_idx = 0; 1238 int be; 1239 MaltaState *s; 1240 DeviceState *dev; 1241 1242 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); 1243 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 1244 1245 /* create CPU */ 1246 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); 1247 1248 /* allocate RAM */ 1249 if (ram_size > 2 * GiB) { 1250 error_report("Too much memory for this machine: %" PRId64 "MB," 1251 " maximum 2048MB", ram_size / MiB); 1252 exit(1); 1253 } 1254 1255 /* register RAM at high address where it is undisturbed by IO */ 1256 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1257 1258 /* alias for pre IO hole access */ 1259 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1260 machine->ram, 0, MIN(ram_size, 256 * MiB)); 1261 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1262 1263 /* alias for post IO hole access, if there is enough RAM */ 1264 if (ram_size > 512 * MiB) { 1265 ram_low_postio = g_new(MemoryRegion, 1); 1266 memory_region_init_alias(ram_low_postio, NULL, 1267 "mips_malta_low_postio.ram", 1268 machine->ram, 512 * MiB, 1269 ram_size - 512 * MiB); 1270 memory_region_add_subregion(system_memory, 512 * MiB, 1271 ram_low_postio); 1272 } 1273 1274 #ifdef TARGET_WORDS_BIGENDIAN 1275 be = 1; 1276 #else 1277 be = 0; 1278 #endif 1279 1280 /* FPGA */ 1281 1282 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ 1283 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); 1284 1285 /* Load firmware in flash / BIOS. */ 1286 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 1287 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", 1288 FLASH_SIZE, 1289 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 1290 65536, 1291 4, 0x0000, 0x0000, 0x0000, 0x0000, be); 1292 bios = pflash_cfi01_get_memory(fl); 1293 fl_idx++; 1294 if (kernel_filename) { 1295 ram_low_size = MIN(ram_size, 256 * MiB); 1296 /* For KVM we reserve 1MB of RAM for running bootloader */ 1297 if (kvm_enabled()) { 1298 ram_low_size -= 0x100000; 1299 bootloader_run_addr = 0x40000000 + ram_low_size; 1300 } else { 1301 bootloader_run_addr = 0xbfc00000; 1302 } 1303 1304 /* Write a small bootloader to the flash location. */ 1305 loaderparams.ram_size = ram_size; 1306 loaderparams.ram_low_size = ram_low_size; 1307 loaderparams.kernel_filename = kernel_filename; 1308 loaderparams.kernel_cmdline = kernel_cmdline; 1309 loaderparams.initrd_filename = initrd_filename; 1310 kernel_entry = load_kernel(); 1311 1312 if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { 1313 write_bootloader(memory_region_get_ram_ptr(bios), 1314 bootloader_run_addr, kernel_entry); 1315 } else { 1316 write_bootloader_nanomips(memory_region_get_ram_ptr(bios), 1317 bootloader_run_addr, kernel_entry); 1318 } 1319 if (kvm_enabled()) { 1320 /* Write the bootloader code @ the end of RAM, 1MB reserved */ 1321 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + 1322 ram_low_size, 1323 bootloader_run_addr, kernel_entry); 1324 } 1325 } else { 1326 target_long bios_size = FLASH_SIZE; 1327 /* The flash region isn't executable from a KVM guest */ 1328 if (kvm_enabled()) { 1329 error_report("KVM enabled but no -kernel argument was specified. " 1330 "Booting from flash is not supported with KVM."); 1331 exit(1); 1332 } 1333 /* Load firmware from flash. */ 1334 if (!dinfo) { 1335 /* Load a BIOS image. */ 1336 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 1337 machine->firmware ?: BIOS_FILENAME); 1338 if (filename) { 1339 bios_size = load_image_targphys(filename, FLASH_ADDRESS, 1340 BIOS_SIZE); 1341 g_free(filename); 1342 } else { 1343 bios_size = -1; 1344 } 1345 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 1346 machine->firmware && !qtest_enabled()) { 1347 error_report("Could not load MIPS bios '%s'", machine->firmware); 1348 exit(1); 1349 } 1350 } 1351 /* 1352 * In little endian mode the 32bit words in the bios are swapped, 1353 * a neat trick which allows bi-endian firmware. 1354 */ 1355 #ifndef TARGET_WORDS_BIGENDIAN 1356 { 1357 uint32_t *end, *addr; 1358 const size_t swapsize = MIN(bios_size, 0x3e0000); 1359 addr = rom_ptr(FLASH_ADDRESS, swapsize); 1360 if (!addr) { 1361 addr = memory_region_get_ram_ptr(bios); 1362 } 1363 end = (void *)addr + swapsize; 1364 while (addr < end) { 1365 bswap32s(addr); 1366 addr++; 1367 } 1368 } 1369 #endif 1370 } 1371 1372 /* 1373 * Map the BIOS at a 2nd physical location, as on the real board. 1374 * Copy it so that we can patch in the MIPS revision, which cannot be 1375 * handled by an overlapping region as the resulting ROM code subpage 1376 * regions are not executable. 1377 */ 1378 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, 1379 &error_fatal); 1380 if (!rom_copy(memory_region_get_ram_ptr(bios_copy), 1381 FLASH_ADDRESS, BIOS_SIZE)) { 1382 memcpy(memory_region_get_ram_ptr(bios_copy), 1383 memory_region_get_ram_ptr(bios), BIOS_SIZE); 1384 } 1385 memory_region_set_readonly(bios_copy, true); 1386 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); 1387 1388 /* Board ID = 0x420 (Malta Board with CoreLV) */ 1389 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); 1390 1391 /* Northbridge */ 1392 pci_bus = gt64120_register(s->i8259); 1393 /* 1394 * The whole address space decoded by the GT-64120A doesn't generate 1395 * exception when accessing invalid memory. Create an empty slot to 1396 * emulate this feature. 1397 */ 1398 empty_slot_init("GT64120", 0, 0x20000000); 1399 1400 /* Southbridge */ 1401 dev = piix4_create(pci_bus, &isa_bus, &smbus); 1402 1403 /* Interrupt controller */ 1404 qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); 1405 for (int i = 0; i < ISA_NUM_IRQS; i++) { 1406 s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); 1407 } 1408 1409 /* generate SPD EEPROM data */ 1410 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); 1411 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 1412 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); 1413 g_free(smbus_eeprom_buf); 1414 1415 /* Super I/O: SMS FDC37M817 */ 1416 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); 1417 1418 /* Network card */ 1419 network_init(pci_bus); 1420 1421 /* Optional PCI video card */ 1422 pci_vga_init(pci_bus); 1423 } 1424 1425 static void mips_malta_instance_init(Object *obj) 1426 { 1427 MaltaState *s = MIPS_MALTA(obj); 1428 1429 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 1430 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ 1431 } 1432 1433 static const TypeInfo mips_malta_device = { 1434 .name = TYPE_MIPS_MALTA, 1435 .parent = TYPE_SYS_BUS_DEVICE, 1436 .instance_size = sizeof(MaltaState), 1437 .instance_init = mips_malta_instance_init, 1438 }; 1439 1440 static void mips_malta_machine_init(MachineClass *mc) 1441 { 1442 mc->desc = "MIPS Malta Core LV"; 1443 mc->init = mips_malta_init; 1444 mc->block_default_type = IF_IDE; 1445 mc->max_cpus = 16; 1446 mc->is_default = true; 1447 #ifdef TARGET_MIPS64 1448 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1449 #else 1450 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1451 #endif 1452 mc->default_ram_id = "mips_malta.ram"; 1453 } 1454 1455 DEFINE_MACHINE("malta", mips_malta_machine_init) 1456 1457 static void mips_malta_register_types(void) 1458 { 1459 type_register_static(&mips_malta_device); 1460 } 1461 1462 type_init(mips_malta_register_types) 1463