1 /* 2 * QEMU Malta board support 3 * 4 * Copyright (c) 2006 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/bitops.h" 28 #include "qemu/datadir.h" 29 #include "qemu/guest-random.h" 30 #include "hw/clock.h" 31 #include "hw/southbridge/piix.h" 32 #include "hw/isa/superio.h" 33 #include "hw/char/serial.h" 34 #include "net/net.h" 35 #include "hw/boards.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/block/flash.h" 38 #include "hw/mips/mips.h" 39 #include "hw/mips/bootloader.h" 40 #include "hw/pci/pci.h" 41 #include "hw/pci/pci_bus.h" 42 #include "qemu/log.h" 43 #include "hw/mips/bios.h" 44 #include "hw/ide/pci.h" 45 #include "hw/irq.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "qom/object.h" 49 #include "hw/sysbus.h" /* SysBusDevice */ 50 #include "qemu/host-utils.h" 51 #include "sysemu/qtest.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/runstate.h" 54 #include "qapi/error.h" 55 #include "qemu/error-report.h" 56 #include "sysemu/kvm.h" 57 #include "semihosting/semihost.h" 58 #include "hw/mips/cps.h" 59 #include "hw/qdev-clock.h" 60 #include "target/mips/internal.h" 61 #include "trace.h" 62 63 #define ENVP_PADDR 0x2000 64 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) 65 #define ENVP_NB_ENTRIES 16 66 #define ENVP_ENTRY_SIZE 256 67 68 /* Hardware addresses */ 69 #define FLASH_ADDRESS 0x1e000000ULL 70 #define FPGA_ADDRESS 0x1f000000ULL 71 #define RESET_ADDRESS 0x1fc00000ULL 72 73 #define FLASH_SIZE 0x400000 74 75 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) 76 77 typedef struct { 78 MemoryRegion iomem; 79 MemoryRegion iomem_lo; /* 0 - 0x900 */ 80 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ 81 uint32_t leds; 82 uint32_t brk; 83 uint32_t gpout; 84 uint32_t i2cin; 85 uint32_t i2coe; 86 uint32_t i2cout; 87 uint32_t i2csel; 88 CharBackend display; 89 char display_text[9]; 90 SerialMM *uart; 91 bool display_inited; 92 } MaltaFPGAState; 93 94 #define TYPE_MIPS_MALTA "mips-malta" 95 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) 96 97 struct MaltaState { 98 SysBusDevice parent_obj; 99 100 Clock *cpuclk; 101 MIPSCPSState cps; 102 }; 103 104 static struct _loaderparams { 105 int ram_size, ram_low_size; 106 const char *kernel_filename; 107 const char *kernel_cmdline; 108 const char *initrd_filename; 109 } loaderparams; 110 111 /* Malta FPGA */ 112 static void malta_fpga_update_display_leds(MaltaFPGAState *s) 113 { 114 char leds_text[9]; 115 int i; 116 117 for (i = 7 ; i >= 0 ; i--) { 118 if (s->leds & (1 << i)) { 119 leds_text[i] = '#'; 120 } else { 121 leds_text[i] = ' '; 122 } 123 } 124 leds_text[8] = '\0'; 125 126 trace_malta_fpga_leds(leds_text); 127 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", 128 leds_text); 129 } 130 131 static void malta_fpga_update_display_ascii(MaltaFPGAState *s) 132 { 133 trace_malta_fpga_display(s->display_text); 134 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", 135 s->display_text); 136 } 137 138 /* 139 * EEPROM 24C01 / 24C02 emulation. 140 * 141 * Emulation for serial EEPROMs: 142 * 24C01 - 1024 bit (128 x 8) 143 * 24C02 - 2048 bit (256 x 8) 144 * 145 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. 146 */ 147 148 #if defined(DEBUG) 149 # define logout(fmt, ...) \ 150 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) 151 #else 152 # define logout(fmt, ...) ((void)0) 153 #endif 154 155 struct _eeprom24c0x_t { 156 uint8_t tick; 157 uint8_t address; 158 uint8_t command; 159 uint8_t ack; 160 uint8_t scl; 161 uint8_t sda; 162 uint8_t data; 163 /* uint16_t size; */ 164 uint8_t contents[256]; 165 }; 166 167 typedef struct _eeprom24c0x_t eeprom24c0x_t; 168 169 static eeprom24c0x_t spd_eeprom = { 170 .contents = { 171 /* 00000000: */ 172 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 173 /* 00000008: */ 174 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 175 /* 00000010: */ 176 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 177 /* 00000018: */ 178 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 179 /* 00000020: */ 180 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 181 /* 00000028: */ 182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 183 /* 00000030: */ 184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 185 /* 00000038: */ 186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 187 /* 00000040: */ 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 189 /* 00000048: */ 190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 191 /* 00000050: */ 192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 193 /* 00000058: */ 194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 195 /* 00000060: */ 196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 197 /* 00000068: */ 198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 199 /* 00000070: */ 200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 201 /* 00000078: */ 202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 203 }, 204 }; 205 206 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 207 { 208 enum sdram_type type; 209 uint8_t *spd = spd_eeprom.contents; 210 uint8_t nbanks = 0; 211 uint16_t density = 0; 212 int i; 213 214 /* work in terms of MB */ 215 ram_size /= MiB; 216 217 while ((ram_size >= 4) && (nbanks <= 2)) { 218 int sz_log2 = MIN(31 - clz32(ram_size), 14); 219 nbanks++; 220 density |= 1 << (sz_log2 - 2); 221 ram_size -= 1 << sz_log2; 222 } 223 224 /* split to 2 banks if possible */ 225 if ((nbanks == 1) && (density > 1)) { 226 nbanks++; 227 density >>= 1; 228 } 229 230 if (density & 0xff00) { 231 density = (density & 0xe0) | ((density >> 8) & 0x1f); 232 type = DDR2; 233 } else if (!(density & 0x1f)) { 234 type = DDR2; 235 } else { 236 type = SDR; 237 } 238 239 if (ram_size) { 240 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 241 " of SDRAM", ram_size); 242 } 243 244 /* fill in SPD memory information */ 245 spd[2] = type; 246 spd[5] = nbanks; 247 spd[31] = density; 248 249 /* checksum */ 250 spd[63] = 0; 251 for (i = 0; i < 63; i++) { 252 spd[63] += spd[i]; 253 } 254 255 /* copy for SMBUS */ 256 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 257 } 258 259 static void generate_eeprom_serial(uint8_t *eeprom) 260 { 261 int i, pos = 0; 262 uint8_t mac[6] = { 0x00 }; 263 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 264 265 /* version */ 266 eeprom[pos++] = 0x01; 267 268 /* count */ 269 eeprom[pos++] = 0x02; 270 271 /* MAC address */ 272 eeprom[pos++] = 0x01; /* MAC */ 273 eeprom[pos++] = 0x06; /* length */ 274 memcpy(&eeprom[pos], mac, sizeof(mac)); 275 pos += sizeof(mac); 276 277 /* serial number */ 278 eeprom[pos++] = 0x02; /* serial */ 279 eeprom[pos++] = 0x05; /* length */ 280 memcpy(&eeprom[pos], sn, sizeof(sn)); 281 pos += sizeof(sn); 282 283 /* checksum */ 284 eeprom[pos] = 0; 285 for (i = 0; i < pos; i++) { 286 eeprom[pos] += eeprom[i]; 287 } 288 } 289 290 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) 291 { 292 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", 293 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); 294 return eeprom->sda; 295 } 296 297 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) 298 { 299 if (eeprom->scl && scl && (eeprom->sda != sda)) { 300 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", 301 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, 302 sda ? "stop" : "start"); 303 if (!sda) { 304 eeprom->tick = 1; 305 eeprom->command = 0; 306 } 307 } else if (eeprom->tick == 0 && !eeprom->ack) { 308 /* Waiting for start. */ 309 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", 310 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 311 } else if (!eeprom->scl && scl) { 312 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", 313 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 314 if (eeprom->ack) { 315 logout("\ti2c ack bit = 0\n"); 316 sda = 0; 317 eeprom->ack = 0; 318 } else if (eeprom->sda == sda) { 319 uint8_t bit = (sda != 0); 320 logout("\ti2c bit = %d\n", bit); 321 if (eeprom->tick < 9) { 322 eeprom->command <<= 1; 323 eeprom->command += bit; 324 eeprom->tick++; 325 if (eeprom->tick == 9) { 326 logout("\tcommand 0x%04x, %s\n", eeprom->command, 327 bit ? "read" : "write"); 328 eeprom->ack = 1; 329 } 330 } else if (eeprom->tick < 17) { 331 if (eeprom->command & 1) { 332 sda = ((eeprom->data & 0x80) != 0); 333 } 334 eeprom->address <<= 1; 335 eeprom->address += bit; 336 eeprom->tick++; 337 eeprom->data <<= 1; 338 if (eeprom->tick == 17) { 339 eeprom->data = eeprom->contents[eeprom->address]; 340 logout("\taddress 0x%04x, data 0x%02x\n", 341 eeprom->address, eeprom->data); 342 eeprom->ack = 1; 343 eeprom->tick = 0; 344 } 345 } else if (eeprom->tick >= 17) { 346 sda = 0; 347 } 348 } else { 349 logout("\tsda changed with raising scl\n"); 350 } 351 } else { 352 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, 353 scl, eeprom->sda, sda); 354 } 355 eeprom->scl = scl; 356 eeprom->sda = sda; 357 } 358 359 static uint64_t malta_fpga_read(void *opaque, hwaddr addr, 360 unsigned size) 361 { 362 MaltaFPGAState *s = opaque; 363 uint32_t val = 0; 364 uint32_t saddr; 365 366 saddr = (addr & 0xfffff); 367 368 switch (saddr) { 369 370 /* SWITCH Register */ 371 case 0x00200: 372 val = 0x00000000; 373 break; 374 375 /* STATUS Register */ 376 case 0x00208: 377 #if TARGET_BIG_ENDIAN 378 val = 0x00000012; 379 #else 380 val = 0x00000010; 381 #endif 382 break; 383 384 /* JMPRS Register */ 385 case 0x00210: 386 val = 0x00; 387 break; 388 389 /* LEDBAR Register */ 390 case 0x00408: 391 val = s->leds; 392 break; 393 394 /* BRKRES Register */ 395 case 0x00508: 396 val = s->brk; 397 break; 398 399 /* UART Registers are handled directly by the serial device */ 400 401 /* GPOUT Register */ 402 case 0x00a00: 403 val = s->gpout; 404 break; 405 406 /* XXX: implement a real I2C controller */ 407 408 /* GPINP Register */ 409 case 0x00a08: 410 /* IN = OUT until a real I2C control is implemented */ 411 if (s->i2csel) { 412 val = s->i2cout; 413 } else { 414 val = 0x00; 415 } 416 break; 417 418 /* I2CINP Register */ 419 case 0x00b00: 420 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); 421 break; 422 423 /* I2COE Register */ 424 case 0x00b08: 425 val = s->i2coe; 426 break; 427 428 /* I2COUT Register */ 429 case 0x00b10: 430 val = s->i2cout; 431 break; 432 433 /* I2CSEL Register */ 434 case 0x00b18: 435 val = s->i2csel; 436 break; 437 438 default: 439 qemu_log_mask(LOG_GUEST_ERROR, 440 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", 441 addr); 442 break; 443 } 444 return val; 445 } 446 447 static void malta_fpga_write(void *opaque, hwaddr addr, 448 uint64_t val, unsigned size) 449 { 450 MaltaFPGAState *s = opaque; 451 uint32_t saddr; 452 453 saddr = (addr & 0xfffff); 454 455 switch (saddr) { 456 457 /* SWITCH Register */ 458 case 0x00200: 459 break; 460 461 /* JMPRS Register */ 462 case 0x00210: 463 break; 464 465 /* LEDBAR Register */ 466 case 0x00408: 467 s->leds = val & 0xff; 468 malta_fpga_update_display_leds(s); 469 break; 470 471 /* ASCIIWORD Register */ 472 case 0x00410: 473 snprintf(s->display_text, 9, "%08X", (uint32_t)val); 474 malta_fpga_update_display_ascii(s); 475 break; 476 477 /* ASCIIPOS0 to ASCIIPOS7 Registers */ 478 case 0x00418: 479 case 0x00420: 480 case 0x00428: 481 case 0x00430: 482 case 0x00438: 483 case 0x00440: 484 case 0x00448: 485 case 0x00450: 486 s->display_text[(saddr - 0x00418) >> 3] = (char) val; 487 malta_fpga_update_display_ascii(s); 488 break; 489 490 /* SOFTRES Register */ 491 case 0x00500: 492 if (val == 0x42) { 493 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 494 } 495 break; 496 497 /* BRKRES Register */ 498 case 0x00508: 499 s->brk = val & 0xff; 500 break; 501 502 /* UART Registers are handled directly by the serial device */ 503 504 /* GPOUT Register */ 505 case 0x00a00: 506 s->gpout = val & 0xff; 507 break; 508 509 /* I2COE Register */ 510 case 0x00b08: 511 s->i2coe = val & 0x03; 512 break; 513 514 /* I2COUT Register */ 515 case 0x00b10: 516 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); 517 s->i2cout = val; 518 break; 519 520 /* I2CSEL Register */ 521 case 0x00b18: 522 s->i2csel = val & 0x01; 523 break; 524 525 default: 526 qemu_log_mask(LOG_GUEST_ERROR, 527 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", 528 addr); 529 break; 530 } 531 } 532 533 static const MemoryRegionOps malta_fpga_ops = { 534 .read = malta_fpga_read, 535 .write = malta_fpga_write, 536 .endianness = DEVICE_NATIVE_ENDIAN, 537 }; 538 539 static void malta_fpga_reset(void *opaque) 540 { 541 MaltaFPGAState *s = opaque; 542 543 s->leds = 0x00; 544 s->brk = 0x0a; 545 s->gpout = 0x00; 546 s->i2cin = 0x3; 547 s->i2coe = 0x0; 548 s->i2cout = 0x3; 549 s->i2csel = 0x1; 550 551 s->display_text[8] = '\0'; 552 snprintf(s->display_text, 9, " "); 553 } 554 555 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) 556 { 557 MaltaFPGAState *s = opaque; 558 559 if (event == CHR_EVENT_OPENED && !s->display_inited) { 560 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); 561 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 562 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 563 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 564 qemu_chr_fe_printf(&s->display, "\n"); 565 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); 566 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 567 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 568 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 569 s->display_inited = true; 570 } 571 } 572 573 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, 574 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) 575 { 576 MaltaFPGAState *s; 577 Chardev *chr; 578 579 s = g_new0(MaltaFPGAState, 1); 580 581 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, 582 "malta-fpga", 0x100000); 583 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", 584 &s->iomem, 0, 0x900); 585 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", 586 &s->iomem, 0xa00, 0x100000 - 0xa00); 587 588 memory_region_add_subregion(address_space, base, &s->iomem_lo); 589 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); 590 591 chr = qemu_chr_new("fpga", "vc:320x200", NULL); 592 qemu_chr_fe_init(&s->display, chr, NULL); 593 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, 594 malta_fgpa_display_event, NULL, s, NULL, true); 595 596 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, 597 230400, uart_chr, DEVICE_NATIVE_ENDIAN); 598 599 malta_fpga_reset(s); 600 qemu_register_reset(malta_fpga_reset, s); 601 602 return s; 603 } 604 605 /* Network support */ 606 static void network_init(PCIBus *pci_bus) 607 { 608 int i; 609 610 for (i = 0; i < nb_nics; i++) { 611 NICInfo *nd = &nd_table[i]; 612 const char *default_devaddr = NULL; 613 614 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) 615 /* The malta board has a PCNet card using PCI SLOT 11 */ 616 default_devaddr = "0b"; 617 618 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); 619 } 620 } 621 622 static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, 623 uint64_t kernel_entry) 624 { 625 static const char pci_pins_cfg[PCI_NUM_PINS] = { 626 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ 627 }; 628 629 /* Bus endianness is always reversed */ 630 #if TARGET_BIG_ENDIAN 631 #define cpu_to_gt32(x) (x) 632 #else 633 #define cpu_to_gt32(x) bswap32(x) 634 #endif 635 636 /* setup MEM-to-PCI0 mapping as done by YAMON */ 637 638 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 639 bl_gen_write_u32(p, /* GT_ISD */ 640 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), 641 cpu_to_gt32(0x1be00000 << 3)); 642 643 /* setup PCI0 io window to 0x18000000-0x181fffff */ 644 bl_gen_write_u32(p, /* GT_PCI0IOLD */ 645 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), 646 cpu_to_gt32(0x18000000 << 3)); 647 bl_gen_write_u32(p, /* GT_PCI0IOHD */ 648 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), 649 cpu_to_gt32(0x08000000 << 3)); 650 651 /* setup PCI0 mem windows */ 652 bl_gen_write_u32(p, /* GT_PCI0M0LD */ 653 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), 654 cpu_to_gt32(0x10000000 << 3)); 655 bl_gen_write_u32(p, /* GT_PCI0M0HD */ 656 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), 657 cpu_to_gt32(0x07e00000 << 3)); 658 bl_gen_write_u32(p, /* GT_PCI0M1LD */ 659 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), 660 cpu_to_gt32(0x18200000 << 3)); 661 bl_gen_write_u32(p, /* GT_PCI0M1HD */ 662 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), 663 cpu_to_gt32(0x0bc00000 << 3)); 664 665 #undef cpu_to_gt32 666 667 /* 668 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. 669 * Load the PIIX IRQC[A:D] routing config address, then 670 * write routing configuration to the config data register. 671 */ 672 bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ 673 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), 674 tswap32((1 << 31) /* ConfigEn */ 675 | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 676 | PIIX_PIRQCA)); 677 bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ 678 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), 679 tswap32(ldl_be_p(pci_pins_cfg))); 680 681 bl_gen_jump_kernel(p, 682 true, ENVP_VADDR - 64, 683 /* 684 * If semihosting is used, arguments have already 685 * been passed, so we preserve $a0. 686 */ 687 !semihosting_get_argc(), 2, 688 true, ENVP_VADDR, 689 true, ENVP_VADDR + 8, 690 true, loaderparams.ram_low_size, 691 kernel_entry); 692 } 693 694 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, 695 uint64_t kernel_entry) 696 { 697 uint16_t *p; 698 699 /* Small bootloader */ 700 p = (uint16_t *)base; 701 702 stw_p(p++, 0x2800); stw_p(p++, 0x001c); 703 /* bc to_here */ 704 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 705 /* nop */ 706 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 707 /* nop */ 708 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 709 /* nop */ 710 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 711 /* nop */ 712 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 713 /* nop */ 714 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 715 /* nop */ 716 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 717 /* nop */ 718 719 /* to_here: */ 720 721 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); 722 } 723 724 /* 725 * ROM and pseudo bootloader 726 * 727 * The following code implements a very very simple bootloader. It first 728 * loads the registers a0 to a3 to the values expected by the OS, and 729 * then jump at the kernel address. 730 * 731 * The bootloader should pass the locations of the kernel arguments and 732 * environment variables tables. Those tables contain the 32-bit address 733 * of NULL terminated strings. The environment variables table should be 734 * terminated by a NULL address. 735 * 736 * For a simpler implementation, the number of kernel arguments is fixed 737 * to two (the name of the kernel and the command line), and the two 738 * tables are actually the same one. 739 * 740 * The registers a0 to a3 should contain the following values: 741 * a0 - number of kernel arguments 742 * a1 - 32-bit address of the kernel arguments table 743 * a2 - 32-bit address of the environment variables table 744 * a3 - RAM size in bytes 745 */ 746 static void write_bootloader(uint8_t *base, uint64_t run_addr, 747 uint64_t kernel_entry) 748 { 749 uint32_t *p; 750 751 /* Small bootloader */ 752 p = (uint32_t *)base; 753 754 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ 755 ((run_addr + 0x580) & 0x0fffffff) >> 2); 756 stl_p(p++, 0x00000000); /* nop */ 757 758 /* YAMON service vector */ 759 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ 760 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ 761 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ 762 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ 763 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ 764 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ 765 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ 766 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ 767 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ 768 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ 769 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ 770 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ 771 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ 772 773 774 /* Second part of the bootloader */ 775 p = (uint32_t *) (base + 0x580); 776 777 /* 778 * Load BAR registers as done by YAMON: 779 * 780 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 781 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 782 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 783 * 784 */ 785 786 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); 787 788 /* YAMON subroutines */ 789 p = (uint32_t *) (base + 0x800); 790 stl_p(p++, 0x03e00009); /* jalr ra */ 791 stl_p(p++, 0x24020000); /* li v0,0 */ 792 /* 808 YAMON print */ 793 stl_p(p++, 0x03e06821); /* move t5,ra */ 794 stl_p(p++, 0x00805821); /* move t3,a0 */ 795 stl_p(p++, 0x00a05021); /* move t2,a1 */ 796 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 797 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 798 stl_p(p++, 0x10800005); /* beqz a0,834 */ 799 stl_p(p++, 0x00000000); /* nop */ 800 stl_p(p++, 0x0ff0021c); /* jal 870 */ 801 stl_p(p++, 0x00000000); /* nop */ 802 stl_p(p++, 0x1000fff9); /* b 814 */ 803 stl_p(p++, 0x00000000); /* nop */ 804 stl_p(p++, 0x01a00009); /* jalr t5 */ 805 stl_p(p++, 0x01602021); /* move a0,t3 */ 806 /* 0x83c YAMON print_count */ 807 stl_p(p++, 0x03e06821); /* move t5,ra */ 808 stl_p(p++, 0x00805821); /* move t3,a0 */ 809 stl_p(p++, 0x00a05021); /* move t2,a1 */ 810 stl_p(p++, 0x00c06021); /* move t4,a2 */ 811 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 812 stl_p(p++, 0x0ff0021c); /* jal 870 */ 813 stl_p(p++, 0x00000000); /* nop */ 814 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 815 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ 816 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ 817 stl_p(p++, 0x00000000); /* nop */ 818 stl_p(p++, 0x01a00009); /* jalr t5 */ 819 stl_p(p++, 0x01602021); /* move a0,t3 */ 820 /* 0x870 */ 821 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ 822 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ 823 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ 824 stl_p(p++, 0x00000000); /* nop */ 825 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ 826 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ 827 stl_p(p++, 0x00000000); /* nop */ 828 stl_p(p++, 0x03e00009); /* jalr ra */ 829 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ 830 } 831 832 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index, 833 const char *string, ...) 834 { 835 va_list ap; 836 uint32_t table_addr; 837 838 if (index >= ENVP_NB_ENTRIES) { 839 return; 840 } 841 842 if (string == NULL) { 843 prom_buf[index] = 0; 844 return; 845 } 846 847 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 848 prom_buf[index] = tswap32(ENVP_VADDR + table_addr); 849 850 va_start(ap, string); 851 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 852 va_end(ap); 853 } 854 855 static void reinitialize_rng_seed(void *opaque) 856 { 857 char *rng_seed_hex = opaque; 858 uint8_t rng_seed[32]; 859 860 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 861 for (size_t i = 0; i < sizeof(rng_seed); ++i) { 862 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); 863 } 864 } 865 866 /* Kernel */ 867 static uint64_t load_kernel(void) 868 { 869 uint64_t kernel_entry, kernel_high, initrd_size; 870 long kernel_size; 871 ram_addr_t initrd_offset; 872 uint32_t *prom_buf; 873 long prom_size; 874 int prom_index = 0; 875 uint8_t rng_seed[32]; 876 char rng_seed_hex[sizeof(rng_seed) * 2 + 1]; 877 size_t rng_seed_prom_offset; 878 879 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 880 cpu_mips_kseg0_to_phys, NULL, 881 &kernel_entry, NULL, 882 &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS, 883 1, 0); 884 if (kernel_size < 0) { 885 error_report("could not load kernel '%s': %s", 886 loaderparams.kernel_filename, 887 load_elf_strerror(kernel_size)); 888 exit(1); 889 } 890 891 /* Check where the kernel has been linked */ 892 if (kernel_entry <= USEG_LIMIT) { 893 error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)" 894 " are not supported"); 895 exit(1); 896 } 897 898 /* load initrd */ 899 initrd_size = 0; 900 initrd_offset = 0; 901 if (loaderparams.initrd_filename) { 902 initrd_size = get_image_size(loaderparams.initrd_filename); 903 if (initrd_size > 0) { 904 /* 905 * The kernel allocates the bootmap memory in the low memory after 906 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB 907 * pages. 908 */ 909 initrd_offset = ROUND_UP(loaderparams.ram_low_size 910 - (initrd_size + 128 * KiB), 911 INITRD_PAGE_SIZE); 912 if (kernel_high >= initrd_offset) { 913 error_report("memory too small for initial ram disk '%s'", 914 loaderparams.initrd_filename); 915 exit(1); 916 } 917 initrd_size = load_image_targphys(loaderparams.initrd_filename, 918 initrd_offset, 919 loaderparams.ram_size - initrd_offset); 920 } 921 if (initrd_size == (target_ulong) -1) { 922 error_report("could not load initial ram disk '%s'", 923 loaderparams.initrd_filename); 924 exit(1); 925 } 926 } 927 928 /* Setup prom parameters. */ 929 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 930 prom_buf = g_malloc(prom_size); 931 932 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); 933 if (initrd_size > 0) { 934 prom_set(prom_buf, prom_index++, 935 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 936 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 937 initrd_size, loaderparams.kernel_cmdline); 938 } else { 939 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); 940 } 941 942 prom_set(prom_buf, prom_index++, "memsize"); 943 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); 944 945 prom_set(prom_buf, prom_index++, "ememsize"); 946 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); 947 948 prom_set(prom_buf, prom_index++, "modetty0"); 949 prom_set(prom_buf, prom_index++, "38400n8r"); 950 951 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 952 for (size_t i = 0; i < sizeof(rng_seed); ++i) { 953 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); 954 } 955 prom_set(prom_buf, prom_index++, "rngseed"); 956 rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE + 957 sizeof(uint32_t) * ENVP_NB_ENTRIES; 958 prom_set(prom_buf, prom_index++, "%s", rng_seed_hex); 959 960 prom_set(prom_buf, prom_index++, NULL); 961 962 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); 963 qemu_register_reset_nosnapshotload(reinitialize_rng_seed, 964 rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset); 965 966 g_free(prom_buf); 967 return kernel_entry; 968 } 969 970 static void malta_mips_config(MIPSCPU *cpu) 971 { 972 MachineState *ms = MACHINE(qdev_get_machine()); 973 unsigned int smp_cpus = ms->smp.cpus; 974 CPUMIPSState *env = &cpu->env; 975 CPUState *cs = CPU(cpu); 976 977 if (ase_mt_available(env)) { 978 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 979 CP0MVPC0_PTC, 8, 980 smp_cpus * cs->nr_threads - 1); 981 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 982 CP0MVPC0_PVPE, 4, smp_cpus - 1); 983 } 984 } 985 986 static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) 987 { 988 int slot; 989 990 slot = PCI_SLOT(pci_dev->devfn); 991 992 switch (slot) { 993 /* PIIX4 USB */ 994 case 10: 995 return 3; 996 /* AMD 79C973 Ethernet */ 997 case 11: 998 return 1; 999 /* Crystal 4281 Sound */ 1000 case 12: 1001 return 2; 1002 /* PCI slot 1 to 4 */ 1003 case 18 ... 21: 1004 return ((slot - 18) + irq_num) & 0x03; 1005 /* Unknown device, don't do any translation */ 1006 default: 1007 return irq_num; 1008 } 1009 } 1010 1011 static void main_cpu_reset(void *opaque) 1012 { 1013 MIPSCPU *cpu = opaque; 1014 CPUMIPSState *env = &cpu->env; 1015 1016 cpu_reset(CPU(cpu)); 1017 1018 /* 1019 * The bootloader does not need to be rewritten as it is located in a 1020 * read only location. The kernel location and the arguments table 1021 * location does not change. 1022 */ 1023 if (loaderparams.kernel_filename) { 1024 env->CP0_Status &= ~(1 << CP0St_ERL); 1025 } 1026 1027 malta_mips_config(cpu); 1028 } 1029 1030 static void create_cpu_without_cps(MachineState *ms, MaltaState *s, 1031 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1032 { 1033 CPUMIPSState *env; 1034 MIPSCPU *cpu; 1035 int i; 1036 1037 for (i = 0; i < ms->smp.cpus; i++) { 1038 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); 1039 1040 /* Init internal devices */ 1041 cpu_mips_irq_init_cpu(cpu); 1042 cpu_mips_clock_init(cpu); 1043 qemu_register_reset(main_cpu_reset, cpu); 1044 } 1045 1046 cpu = MIPS_CPU(first_cpu); 1047 env = &cpu->env; 1048 *i8259_irq = env->irq[2]; 1049 *cbus_irq = env->irq[4]; 1050 } 1051 1052 static void create_cps(MachineState *ms, MaltaState *s, 1053 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1054 { 1055 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1056 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1057 &error_fatal); 1058 object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1059 &error_fatal); 1060 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); 1061 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1062 1063 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1064 1065 *i8259_irq = get_cps_irq(&s->cps, 3); 1066 *cbus_irq = NULL; 1067 } 1068 1069 static void mips_create_cpu(MachineState *ms, MaltaState *s, 1070 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1071 { 1072 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { 1073 create_cps(ms, s, cbus_irq, i8259_irq); 1074 } else { 1075 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); 1076 } 1077 } 1078 1079 static 1080 void mips_malta_init(MachineState *machine) 1081 { 1082 ram_addr_t ram_size = machine->ram_size; 1083 ram_addr_t ram_low_size; 1084 const char *kernel_filename = machine->kernel_filename; 1085 const char *kernel_cmdline = machine->kernel_cmdline; 1086 const char *initrd_filename = machine->initrd_filename; 1087 char *filename; 1088 PFlashCFI01 *fl; 1089 MemoryRegion *system_memory = get_system_memory(); 1090 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1091 MemoryRegion *ram_low_postio; 1092 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); 1093 const size_t smbus_eeprom_size = 8 * 256; 1094 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 1095 uint64_t kernel_entry, bootloader_run_addr; 1096 PCIBus *pci_bus; 1097 ISABus *isa_bus; 1098 qemu_irq cbus_irq, i8259_irq; 1099 I2CBus *smbus; 1100 DriveInfo *dinfo; 1101 int fl_idx = 0; 1102 MaltaState *s; 1103 PCIDevice *piix4; 1104 DeviceState *dev; 1105 1106 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); 1107 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 1108 1109 /* create CPU */ 1110 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); 1111 1112 /* allocate RAM */ 1113 if (ram_size > 2 * GiB) { 1114 error_report("Too much memory for this machine: %" PRId64 "MB," 1115 " maximum 2048MB", ram_size / MiB); 1116 exit(1); 1117 } 1118 1119 /* register RAM at high address where it is undisturbed by IO */ 1120 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1121 1122 /* alias for pre IO hole access */ 1123 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1124 machine->ram, 0, MIN(ram_size, 256 * MiB)); 1125 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1126 1127 /* alias for post IO hole access, if there is enough RAM */ 1128 if (ram_size > 512 * MiB) { 1129 ram_low_postio = g_new(MemoryRegion, 1); 1130 memory_region_init_alias(ram_low_postio, NULL, 1131 "mips_malta_low_postio.ram", 1132 machine->ram, 512 * MiB, 1133 ram_size - 512 * MiB); 1134 memory_region_add_subregion(system_memory, 512 * MiB, 1135 ram_low_postio); 1136 } 1137 1138 /* FPGA */ 1139 1140 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ 1141 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); 1142 1143 /* Load firmware in flash / BIOS. */ 1144 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 1145 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", 1146 FLASH_SIZE, 1147 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 1148 65536, 1149 4, 0x0000, 0x0000, 0x0000, 0x0000, 1150 TARGET_BIG_ENDIAN); 1151 bios = pflash_cfi01_get_memory(fl); 1152 fl_idx++; 1153 if (kernel_filename) { 1154 ram_low_size = MIN(ram_size, 256 * MiB); 1155 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); 1156 1157 /* Write a small bootloader to the flash location. */ 1158 loaderparams.ram_size = ram_size; 1159 loaderparams.ram_low_size = ram_low_size; 1160 loaderparams.kernel_filename = kernel_filename; 1161 loaderparams.kernel_cmdline = kernel_cmdline; 1162 loaderparams.initrd_filename = initrd_filename; 1163 kernel_entry = load_kernel(); 1164 1165 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { 1166 write_bootloader(memory_region_get_ram_ptr(bios), 1167 bootloader_run_addr, kernel_entry); 1168 } else { 1169 write_bootloader_nanomips(memory_region_get_ram_ptr(bios), 1170 bootloader_run_addr, kernel_entry); 1171 } 1172 } else { 1173 target_long bios_size = FLASH_SIZE; 1174 /* Load firmware from flash. */ 1175 if (!dinfo) { 1176 /* Load a BIOS image. */ 1177 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 1178 machine->firmware ?: BIOS_FILENAME); 1179 if (filename) { 1180 bios_size = load_image_targphys(filename, FLASH_ADDRESS, 1181 BIOS_SIZE); 1182 g_free(filename); 1183 } else { 1184 bios_size = -1; 1185 } 1186 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 1187 machine->firmware && !qtest_enabled()) { 1188 error_report("Could not load MIPS bios '%s'", machine->firmware); 1189 exit(1); 1190 } 1191 } 1192 /* 1193 * In little endian mode the 32bit words in the bios are swapped, 1194 * a neat trick which allows bi-endian firmware. 1195 */ 1196 #if !TARGET_BIG_ENDIAN 1197 { 1198 uint32_t *end, *addr; 1199 const size_t swapsize = MIN(bios_size, 0x3e0000); 1200 addr = rom_ptr(FLASH_ADDRESS, swapsize); 1201 if (!addr) { 1202 addr = memory_region_get_ram_ptr(bios); 1203 } 1204 end = (void *)addr + swapsize; 1205 while (addr < end) { 1206 bswap32s(addr); 1207 addr++; 1208 } 1209 } 1210 #endif 1211 } 1212 1213 /* 1214 * Map the BIOS at a 2nd physical location, as on the real board. 1215 * Copy it so that we can patch in the MIPS revision, which cannot be 1216 * handled by an overlapping region as the resulting ROM code subpage 1217 * regions are not executable. 1218 */ 1219 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, 1220 &error_fatal); 1221 if (!rom_copy(memory_region_get_ram_ptr(bios_copy), 1222 FLASH_ADDRESS, BIOS_SIZE)) { 1223 memcpy(memory_region_get_ram_ptr(bios_copy), 1224 memory_region_get_ram_ptr(bios), BIOS_SIZE); 1225 } 1226 memory_region_set_readonly(bios_copy, true); 1227 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); 1228 1229 /* Board ID = 0x420 (Malta Board with CoreLV) */ 1230 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); 1231 1232 /* Northbridge */ 1233 dev = qdev_new("gt64120"); 1234 qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN); 1235 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1236 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 1237 pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); 1238 1239 /* Southbridge */ 1240 piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE); 1241 qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); 1242 pci_realize_and_unref(piix4, pci_bus, &error_fatal); 1243 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); 1244 1245 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); 1246 pci_ide_create_devs(PCI_DEVICE(dev)); 1247 1248 /* Interrupt controller */ 1249 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); 1250 1251 /* generate SPD EEPROM data */ 1252 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); 1253 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); 1254 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); 1255 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 1256 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); 1257 g_free(smbus_eeprom_buf); 1258 1259 /* Super I/O: SMS FDC37M817 */ 1260 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); 1261 1262 /* Network card */ 1263 network_init(pci_bus); 1264 1265 /* Optional PCI video card */ 1266 pci_vga_init(pci_bus); 1267 } 1268 1269 static void mips_malta_instance_init(Object *obj) 1270 { 1271 MaltaState *s = MIPS_MALTA(obj); 1272 1273 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 1274 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ 1275 } 1276 1277 static const TypeInfo mips_malta_device = { 1278 .name = TYPE_MIPS_MALTA, 1279 .parent = TYPE_SYS_BUS_DEVICE, 1280 .instance_size = sizeof(MaltaState), 1281 .instance_init = mips_malta_instance_init, 1282 }; 1283 1284 GlobalProperty malta_compat[] = { 1285 { "PIIX4_PM", "memory-hotplug-support", "off" }, 1286 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 1287 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" }, 1288 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" }, 1289 }; 1290 const size_t malta_compat_len = G_N_ELEMENTS(malta_compat); 1291 1292 static void mips_malta_machine_init(MachineClass *mc) 1293 { 1294 mc->desc = "MIPS Malta Core LV"; 1295 mc->init = mips_malta_init; 1296 mc->block_default_type = IF_IDE; 1297 mc->max_cpus = 16; 1298 mc->is_default = true; 1299 #ifdef TARGET_MIPS64 1300 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1301 #else 1302 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1303 #endif 1304 mc->default_ram_id = "mips_malta.ram"; 1305 compat_props_add(mc->compat_props, malta_compat, malta_compat_len); 1306 } 1307 1308 DEFINE_MACHINE("malta", mips_malta_machine_init) 1309 1310 static void mips_malta_register_types(void) 1311 { 1312 type_register_static(&mips_malta_device); 1313 } 1314 1315 type_init(mips_malta_register_types) 1316