1 /* 2 * Generic Loongson-3 Platform support 3 * 4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) 5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <https://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with 23 * extensions, 800~2000MHz) 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qemu/cutils.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "elf.h" 32 #include "hw/char/serial.h" 33 #include "hw/intc/loongson_liointc.h" 34 #include "hw/mips/mips.h" 35 #include "hw/mips/fw_cfg.h" 36 #include "hw/mips/loongson3_bootp.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/loader.h" 40 #include "hw/isa/superio.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci/pci_host.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/usb.h" 46 #include "net/net.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "sysemu/reset.h" 50 #include "sysemu/runstate.h" 51 #include "qemu/error-report.h" 52 53 #define PM_CNTL_MODE 0x10 54 55 #define LOONGSON_MAX_VCPUS 16 56 57 /* 58 * Loongson-3's virtual machine BIOS can be obtained here: 59 * 1, https://github.com/loongson-community/firmware-nonfree 60 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin 61 */ 62 #define LOONGSON3_BIOSNAME "bios_loongson3.bin" 63 64 #define UART_IRQ 0 65 #define RTC_IRQ 1 66 #define PCIE_IRQ_BASE 2 67 68 const MemMapEntry virt_memmap[] = { 69 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, 70 [VIRT_PM] = { 0x10080000, 0x100 }, 71 [VIRT_FW_CFG] = { 0x10080100, 0x100 }, 72 [VIRT_RTC] = { 0x10081000, 0x1000 }, 73 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, 74 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, 75 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, 76 [VIRT_UART] = { 0x1fe001e0, 0x8 }, 77 [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, 78 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 79 [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ 80 }; 81 82 static const MemMapEntry loader_memmap[] = { 83 [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, 84 [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ 85 [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, 86 }; 87 88 static const MemMapEntry loader_rommap[] = { 89 [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, 90 [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, 91 }; 92 93 struct LoongsonMachineState { 94 MachineState parent_obj; 95 MemoryRegion *pio_alias; 96 MemoryRegion *mmio_alias; 97 MemoryRegion *ecam_alias; 98 }; 99 typedef struct LoongsonMachineState LoongsonMachineState; 100 101 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") 102 DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) 103 104 static struct _loaderparams { 105 uint64_t cpu_freq; 106 uint64_t ram_size; 107 const char *kernel_cmdline; 108 const char *kernel_filename; 109 const char *initrd_filename; 110 uint64_t kernel_entry; 111 uint64_t a0, a1, a2; 112 } loaderparams; 113 114 static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) 115 { 116 return 0; 117 } 118 119 static void loongson3_pm_write(void *opaque, hwaddr addr, 120 uint64_t val, unsigned size) 121 { 122 if (addr != PM_CNTL_MODE) { 123 return; 124 } 125 126 switch (val) { 127 case 0x00: 128 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 129 return; 130 case 0x01: 131 qemu_system_suspend_request(); 132 return; 133 case 0xff: 134 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 135 return; 136 default: 137 return; 138 } 139 } 140 141 static const MemoryRegionOps loongson3_pm_ops = { 142 .read = loongson3_pm_read, 143 .write = loongson3_pm_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 .valid = { 146 .min_access_size = 1, 147 .max_access_size = 1 148 } 149 }; 150 151 #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) 152 153 static uint64_t get_cpu_freq_hz(void) 154 { 155 #ifdef CONFIG_KVM 156 int ret; 157 uint64_t freq; 158 struct kvm_one_reg freq_reg = { 159 .id = KVM_REG_MIPS_COUNT_HZ, 160 .addr = (uintptr_t)(&freq) 161 }; 162 163 if (kvm_enabled()) { 164 ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg); 165 if (ret >= 0) { 166 return freq * 2; 167 } 168 } 169 #endif 170 return DEF_LOONGSON3_FREQ; 171 } 172 173 static void init_boot_param(void) 174 { 175 static void *p; 176 struct boot_params *bp; 177 178 p = g_malloc0(loader_rommap[LOADER_PARAM].size); 179 bp = p; 180 181 bp->efi.smbios.vers = cpu_to_le16(1); 182 init_reset_system(&(bp->reset_system)); 183 p += ROUND_UP(sizeof(struct boot_params), 64); 184 init_loongson_params(&(bp->efi.smbios.lp), p, 185 loaderparams.cpu_freq, loaderparams.ram_size); 186 187 rom_add_blob_fixed("params_rom", bp, 188 loader_rommap[LOADER_PARAM].size, 189 loader_rommap[LOADER_PARAM].base); 190 191 g_free(bp); 192 193 loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, 194 loader_rommap[LOADER_PARAM].base); 195 } 196 197 static void init_boot_rom(void) 198 { 199 const unsigned int boot_code[] = { 200 0x40086000, /* mfc0 t0, CP0_STATUS */ 201 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ 202 0x01094025, /* or t0, t0, t1 */ 203 0x3C090040, /* lui t1, 0x40 #set bev */ 204 0x01094025, /* or t0, t0, t1 */ 205 0x40886000, /* mtc0 t0, CP0_STATUS */ 206 0x00000000, 207 0x40806800, /* mtc0 zero, CP0_CAUSE */ 208 0x00000000, 209 0x400A7801, /* mfc0 t2, $15, 1 */ 210 0x314A00FF, /* andi t2, 0x0ff */ 211 0x3C089000, /* dli t0, 0x900000003ff01000 */ 212 0x00084438, 213 0x35083FF0, 214 0x00084438, 215 0x35081000, 216 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ 217 0x000B5A00, /* sll t3, 8 */ 218 0x010B4025, /* or t0, t0, t3 */ 219 0x314C000C, /* andi t4, t2, 0xc #node id */ 220 0x000C62BC, /* dsll t4, 42 */ 221 0x010C4025, /* or t0, t0, t4 */ 222 /* WaitForInit: */ 223 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ 224 0x1040FFFE, /* beqz v0, WaitForInit */ 225 0x00000000, /* nop */ 226 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ 227 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ 228 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ 229 0x00400008, /* jr v0 #byebye */ 230 0x00000000, /* nop */ 231 0x1000FFFF, /* 1: b 1b */ 232 0x00000000, /* nop */ 233 234 /* Reset */ 235 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 236 0x358C0000, 237 0x000C6438, 238 0x358C1008, 239 0x000C6438, 240 0x358C0010, 241 0x240D0000, /* li t1, 0x00 */ 242 0xA18D0000, /* sb t1, (t0) */ 243 0x1000FFFF, /* 1: b 1b */ 244 0x00000000, /* nop */ 245 246 /* Shutdown */ 247 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 248 0x358C0000, 249 0x000C6438, 250 0x358C1008, 251 0x000C6438, 252 0x358C0010, 253 0x240D00FF, /* li t1, 0xff */ 254 0xA18D0000, /* sb t1, (t0) */ 255 0x1000FFFF, /* 1: b 1b */ 256 0x00000000, /* nop */ 257 /* Suspend */ 258 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 259 0x358C0000, 260 0x000C6438, 261 0x358C1008, 262 0x000C6438, 263 0x358C0010, 264 0x240D0001, /* li t1, 0x01 */ 265 0xA18D0000, /* sb t1, (t0) */ 266 0x03e00008, /* jr ra */ 267 0x00000000 /* nop */ 268 }; 269 270 rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), 271 loader_rommap[LOADER_BOOTROM].base); 272 } 273 274 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 275 Error **errp) 276 { 277 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 278 } 279 280 static void fw_conf_init(unsigned long ram_size) 281 { 282 static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 283 FWCfgState *fw_cfg; 284 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; 285 286 fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); 287 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); 288 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); 289 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 290 fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); 291 fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz()); 292 293 fw_cfg_add_file(fw_cfg, "etc/system-states", 294 g_memdup2(suspend, sizeof(suspend)), sizeof(suspend)); 295 296 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 297 } 298 299 static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) 300 { 301 int ret = 0; 302 void *cmdline_buf; 303 hwaddr cmdline_vaddr; 304 unsigned int *parg_env; 305 306 /* Allocate cmdline_buf for command line. */ 307 cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); 308 cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, 309 loader_memmap[LOADER_CMDLINE].base); 310 311 /* 312 * Layout of cmdline_buf looks like this: 313 * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, 314 * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 315 */ 316 parg_env = (void *)cmdline_buf; 317 318 ret = (3 + 1) * 4; 319 *parg_env++ = cmdline_vaddr + ret; 320 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); 321 322 /* argv1 */ 323 *parg_env++ = cmdline_vaddr + ret; 324 if (initrd_size > 0) 325 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, 326 "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", 327 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 328 initrd_size, loaderparams.kernel_cmdline)); 329 else 330 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", 331 loaderparams.kernel_cmdline)); 332 333 /* argv2 */ 334 *parg_env++ = cmdline_vaddr + 4 * ret; 335 336 rom_add_blob_fixed("cmdline", cmdline_buf, 337 loader_memmap[LOADER_CMDLINE].size, 338 loader_memmap[LOADER_CMDLINE].base); 339 340 g_free(cmdline_buf); 341 342 loaderparams.a0 = 2; 343 loaderparams.a1 = cmdline_vaddr; 344 345 return 0; 346 } 347 348 static uint64_t load_kernel(CPUMIPSState *env) 349 { 350 long kernel_size; 351 ram_addr_t initrd_offset; 352 uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; 353 354 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 355 cpu_mips_kseg0_to_phys, NULL, 356 (uint64_t *)&kernel_entry, 357 (uint64_t *)&kernel_low, (uint64_t *)&kernel_high, 358 NULL, 0, EM_MIPS, 1, 0); 359 if (kernel_size < 0) { 360 error_report("could not load kernel '%s': %s", 361 loaderparams.kernel_filename, 362 load_elf_strerror(kernel_size)); 363 exit(1); 364 } 365 366 /* load initrd */ 367 initrd_size = 0; 368 initrd_offset = 0; 369 if (loaderparams.initrd_filename) { 370 initrd_size = get_image_size(loaderparams.initrd_filename); 371 if (initrd_size > 0) { 372 initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, 373 ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); 374 375 if (initrd_offset + initrd_size > loaderparams.ram_size) { 376 error_report("memory too small for initial ram disk '%s'", 377 loaderparams.initrd_filename); 378 exit(1); 379 } 380 381 initrd_size = load_image_targphys(loaderparams.initrd_filename, 382 initrd_offset, 383 loaderparams.ram_size - initrd_offset); 384 } 385 386 if (initrd_size == (target_ulong) -1) { 387 error_report("could not load initial ram disk '%s'", 388 loaderparams.initrd_filename); 389 exit(1); 390 } 391 } 392 393 /* Setup prom cmdline. */ 394 set_prom_cmdline(initrd_offset, initrd_size); 395 396 return kernel_entry; 397 } 398 399 static void main_cpu_reset(void *opaque) 400 { 401 MIPSCPU *cpu = opaque; 402 CPUMIPSState *env = &cpu->env; 403 404 cpu_reset(CPU(cpu)); 405 406 /* Loongson-3 reset stuff */ 407 if (loaderparams.kernel_filename) { 408 if (cpu == MIPS_CPU(first_cpu)) { 409 env->active_tc.gpr[4] = loaderparams.a0; 410 env->active_tc.gpr[5] = loaderparams.a1; 411 env->active_tc.gpr[6] = loaderparams.a2; 412 env->active_tc.PC = loaderparams.kernel_entry; 413 } 414 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 415 } 416 } 417 418 static inline void loongson3_virt_devices_init(MachineState *machine, 419 DeviceState *pic) 420 { 421 int i; 422 qemu_irq irq; 423 PCIBus *pci_bus; 424 DeviceState *dev; 425 MemoryRegion *mmio_reg, *ecam_reg; 426 MachineClass *mc = MACHINE_GET_CLASS(machine); 427 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 428 429 dev = qdev_new(TYPE_GPEX_HOST); 430 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 431 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 432 433 s->ecam_alias = g_new0(MemoryRegion, 1); 434 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 435 memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", 436 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); 437 memory_region_add_subregion(get_system_memory(), 438 virt_memmap[VIRT_PCIE_ECAM].base, 439 s->ecam_alias); 440 441 s->mmio_alias = g_new0(MemoryRegion, 1); 442 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 443 memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", 444 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, 445 virt_memmap[VIRT_PCIE_MMIO].size); 446 memory_region_add_subregion(get_system_memory(), 447 virt_memmap[VIRT_PCIE_MMIO].base, 448 s->mmio_alias); 449 450 s->pio_alias = g_new0(MemoryRegion, 1); 451 memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", 452 get_system_io(), 0, 453 virt_memmap[VIRT_PCIE_PIO].size); 454 memory_region_add_subregion(get_system_memory(), 455 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); 456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); 457 458 for (i = 0; i < GPEX_NUM_IRQS; i++) { 459 irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); 460 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 461 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); 462 } 463 msi_nonbroken = true; 464 465 pci_vga_init(pci_bus); 466 467 if (defaults_enabled() && object_class_by_name("pci-ohci")) { 468 USBBus *usb_bus; 469 470 pci_create_simple(pci_bus, -1, "pci-ohci"); 471 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 472 &error_abort)); 473 usb_create_simple(usb_bus, "usb-kbd"); 474 usb_create_simple(usb_bus, "usb-tablet"); 475 } 476 477 pci_init_nic_devices(pci_bus, mc->default_nic); 478 } 479 480 static void mips_loongson3_virt_init(MachineState *machine) 481 { 482 int i; 483 long bios_size; 484 MIPSCPU *cpu; 485 Clock *cpuclk; 486 CPUMIPSState *env; 487 DeviceState *liointc; 488 char *filename; 489 const char *kernel_cmdline = machine->kernel_cmdline; 490 const char *kernel_filename = machine->kernel_filename; 491 const char *initrd_filename = machine->initrd_filename; 492 ram_addr_t ram_size = machine->ram_size; 493 MemoryRegion *address_space_mem = get_system_memory(); 494 MemoryRegion *ram = g_new(MemoryRegion, 1); 495 MemoryRegion *bios = g_new(MemoryRegion, 1); 496 MemoryRegion *iomem = g_new(MemoryRegion, 1); 497 498 /* TODO: TCG will support all CPU types */ 499 if (!kvm_enabled()) { 500 if (!machine->cpu_type) { 501 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); 502 } 503 if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) { 504 error_report("Loongson-3/TCG needs a Loongson-3 series cpu"); 505 exit(1); 506 } 507 } else { 508 if (!machine->cpu_type) { 509 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); 510 } 511 if (!strstr(machine->cpu_type, "Loongson-3A4000")) { 512 error_report("Loongson-3/KVM needs cpu type Loongson-3A4000"); 513 exit(1); 514 } 515 } 516 517 if (ram_size < 512 * MiB) { 518 error_report("Loongson-3 machine needs at least 512MB memory"); 519 exit(1); 520 } 521 522 /* 523 * The whole MMIO range among configure registers doesn't generate 524 * exception when accessing invalid memory. Create some unimplememted 525 * devices to emulate this feature. 526 */ 527 create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); 528 create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); 529 530 liointc = qdev_new("loongson.liointc"); 531 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); 532 533 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); 534 535 serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, 536 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), 537 DEVICE_NATIVE_ENDIAN); 538 539 sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, 540 qdev_get_gpio_in(liointc, RTC_IRQ)); 541 542 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 543 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); 544 545 for (i = 0; i < machine->smp.cpus; i++) { 546 int ip; 547 548 /* init CPUs */ 549 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 550 551 /* Init internal devices */ 552 cpu_mips_irq_init_cpu(cpu); 553 cpu_mips_clock_init(cpu); 554 qemu_register_reset(main_cpu_reset, cpu); 555 556 if (i >= 4) { 557 continue; /* Only node-0 can be connected to LIOINTC */ 558 } 559 560 for (ip = 0; ip < 4 ; ip++) { 561 int pin = i * 4 + ip; 562 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), 563 pin, cpu->env.irq[ip + 2]); 564 } 565 } 566 env = &MIPS_CPU(first_cpu)->env; 567 568 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ 569 memory_region_init_rom(bios, NULL, "loongson3.bios", 570 virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); 571 memory_region_init_alias(ram, NULL, "loongson3.lowmem", 572 machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); 573 memory_region_init_io(iomem, NULL, &loongson3_pm_ops, 574 NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); 575 qemu_register_wakeup_support(); 576 577 memory_region_add_subregion(address_space_mem, 578 virt_memmap[VIRT_LOWMEM].base, ram); 579 memory_region_add_subregion(address_space_mem, 580 virt_memmap[VIRT_BIOS_ROM].base, bios); 581 memory_region_add_subregion(address_space_mem, 582 virt_memmap[VIRT_HIGHMEM].base, machine->ram); 583 memory_region_add_subregion(address_space_mem, 584 virt_memmap[VIRT_PM].base, iomem); 585 586 /* 587 * We do not support flash operation, just loading bios.bin as raw BIOS. 588 * Please use -L to set the BIOS path and -bios to set bios name. 589 */ 590 591 if (kernel_filename) { 592 loaderparams.cpu_freq = get_cpu_freq_hz(); 593 loaderparams.ram_size = ram_size; 594 loaderparams.kernel_filename = kernel_filename; 595 loaderparams.kernel_cmdline = kernel_cmdline; 596 loaderparams.initrd_filename = initrd_filename; 597 loaderparams.kernel_entry = load_kernel(env); 598 599 init_boot_rom(); 600 init_boot_param(); 601 } else { 602 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 603 machine->firmware ?: LOONGSON3_BIOSNAME); 604 if (filename) { 605 bios_size = load_image_targphys(filename, 606 virt_memmap[VIRT_BIOS_ROM].base, 607 virt_memmap[VIRT_BIOS_ROM].size); 608 g_free(filename); 609 } else { 610 bios_size = -1; 611 } 612 613 if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && 614 !kernel_filename && !qtest_enabled()) { 615 error_report("Could not load MIPS bios '%s'", machine->firmware); 616 exit(1); 617 } 618 619 fw_conf_init(ram_size); 620 } 621 622 loongson3_virt_devices_init(machine, liointc); 623 } 624 625 static void loongson3v_machine_class_init(ObjectClass *oc, void *data) 626 { 627 MachineClass *mc = MACHINE_CLASS(oc); 628 629 mc->desc = "Loongson-3 Virtualization Platform"; 630 mc->init = mips_loongson3_virt_init; 631 mc->block_default_type = IF_IDE; 632 mc->max_cpus = LOONGSON_MAX_VCPUS; 633 mc->default_ram_id = "loongson3.highram"; 634 mc->default_ram_size = 1600 * MiB; 635 mc->minimum_page_bits = 14; 636 mc->default_nic = "virtio-net-pci"; 637 } 638 639 static const TypeInfo loongson3_machine_types[] = { 640 { 641 .name = TYPE_LOONGSON_MACHINE, 642 .parent = TYPE_MACHINE, 643 .instance_size = sizeof(LoongsonMachineState), 644 .class_init = loongson3v_machine_class_init, 645 } 646 }; 647 648 DEFINE_TYPES(loongson3_machine_types) 649