1 /* 2 * Generic Loongson-3 Platform support 3 * 4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) 5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <https://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with 23 * extensions, 800~2000MHz) 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qemu/cutils.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "elf.h" 32 #include "hw/char/serial.h" 33 #include "hw/intc/loongson_liointc.h" 34 #include "hw/mips/mips.h" 35 #include "hw/mips/fw_cfg.h" 36 #include "hw/mips/loongson3_bootp.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/intc/loongson_ipi.h" 40 #include "hw/loader.h" 41 #include "hw/isa/superio.h" 42 #include "hw/pci/msi.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci/pci_host.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/usb.h" 47 #include "net/net.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "sysemu/reset.h" 51 #include "sysemu/runstate.h" 52 #include "qemu/error-report.h" 53 54 #define PM_CNTL_MODE 0x10 55 56 #define LOONGSON_MAX_VCPUS 16 57 58 /* 59 * Loongson-3's virtual machine BIOS can be obtained here: 60 * 1, https://github.com/loongson-community/firmware-nonfree 61 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin 62 */ 63 #define LOONGSON3_BIOSNAME "bios_loongson3.bin" 64 65 #define UART_IRQ 0 66 #define RTC_IRQ 1 67 #define PCIE_IRQ_BASE 2 68 69 const MemMapEntry virt_memmap[] = { 70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, 71 [VIRT_PM] = { 0x10080000, 0x100 }, 72 [VIRT_FW_CFG] = { 0x10080100, 0x100 }, 73 [VIRT_RTC] = { 0x10081000, 0x1000 }, 74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, 75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, 76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, 77 [VIRT_UART] = { 0x1fe001e0, 0x8 }, 78 [VIRT_IPI] = { 0x3ff01000, 0x400 }, 79 [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, 80 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 81 [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ 82 }; 83 84 static const MemMapEntry loader_memmap[] = { 85 [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, 86 [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ 87 [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, 88 }; 89 90 static const MemMapEntry loader_rommap[] = { 91 [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, 92 [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, 93 }; 94 95 struct LoongsonMachineState { 96 MachineState parent_obj; 97 MemoryRegion *pio_alias; 98 MemoryRegion *mmio_alias; 99 MemoryRegion *ecam_alias; 100 }; 101 typedef struct LoongsonMachineState LoongsonMachineState; 102 103 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") 104 DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) 105 106 static struct _loaderparams { 107 uint64_t cpu_freq; 108 uint64_t ram_size; 109 const char *kernel_cmdline; 110 const char *kernel_filename; 111 const char *initrd_filename; 112 uint64_t kernel_entry; 113 uint64_t a0, a1, a2; 114 } loaderparams; 115 116 static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) 117 { 118 return 0; 119 } 120 121 static void loongson3_pm_write(void *opaque, hwaddr addr, 122 uint64_t val, unsigned size) 123 { 124 if (addr != PM_CNTL_MODE) { 125 return; 126 } 127 128 switch (val) { 129 case 0x00: 130 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 131 return; 132 case 0x01: 133 qemu_system_suspend_request(); 134 return; 135 case 0xff: 136 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 137 return; 138 default: 139 return; 140 } 141 } 142 143 static const MemoryRegionOps loongson3_pm_ops = { 144 .read = loongson3_pm_read, 145 .write = loongson3_pm_write, 146 .endianness = DEVICE_NATIVE_ENDIAN, 147 .valid = { 148 .min_access_size = 1, 149 .max_access_size = 1 150 } 151 }; 152 153 #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) 154 155 static uint64_t get_cpu_freq_hz(void) 156 { 157 #ifdef CONFIG_KVM 158 int ret; 159 uint64_t freq; 160 struct kvm_one_reg freq_reg = { 161 .id = KVM_REG_MIPS_COUNT_HZ, 162 .addr = (uintptr_t)(&freq) 163 }; 164 165 if (kvm_enabled()) { 166 ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg); 167 if (ret >= 0) { 168 return freq * 2; 169 } 170 } 171 #endif 172 return DEF_LOONGSON3_FREQ; 173 } 174 175 static void init_boot_param(void) 176 { 177 static void *p; 178 struct boot_params *bp; 179 180 p = g_malloc0(loader_rommap[LOADER_PARAM].size); 181 bp = p; 182 183 bp->efi.smbios.vers = cpu_to_le16(1); 184 init_reset_system(&(bp->reset_system)); 185 p += ROUND_UP(sizeof(struct boot_params), 64); 186 init_loongson_params(&(bp->efi.smbios.lp), p, 187 loaderparams.cpu_freq, loaderparams.ram_size); 188 189 rom_add_blob_fixed("params_rom", bp, 190 loader_rommap[LOADER_PARAM].size, 191 loader_rommap[LOADER_PARAM].base); 192 193 g_free(bp); 194 195 loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, 196 loader_rommap[LOADER_PARAM].base); 197 } 198 199 static void init_boot_rom(void) 200 { 201 const unsigned int boot_code[] = { 202 0x40086000, /* mfc0 t0, CP0_STATUS */ 203 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ 204 0x01094025, /* or t0, t0, t1 */ 205 0x3C090040, /* lui t1, 0x40 #set bev */ 206 0x01094025, /* or t0, t0, t1 */ 207 0x40886000, /* mtc0 t0, CP0_STATUS */ 208 0x00000000, 209 0x40806800, /* mtc0 zero, CP0_CAUSE */ 210 0x00000000, 211 0x400A7801, /* mfc0 t2, $15, 1 */ 212 0x314A00FF, /* andi t2, 0x0ff */ 213 0x3C089000, /* dli t0, 0x900000003ff01000 */ 214 0x00084438, 215 0x35083FF0, 216 0x00084438, 217 0x35081000, 218 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ 219 0x000B5A00, /* sll t3, 8 */ 220 0x010B4025, /* or t0, t0, t3 */ 221 0x314C000C, /* andi t4, t2, 0xc #node id */ 222 0x000C62BC, /* dsll t4, 42 */ 223 0x010C4025, /* or t0, t0, t4 */ 224 /* WaitForInit: */ 225 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ 226 0x1040FFFE, /* beqz v0, WaitForInit */ 227 0x00000000, /* nop */ 228 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ 229 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ 230 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ 231 0x00400008, /* jr v0 #byebye */ 232 0x00000000, /* nop */ 233 0x1000FFFF, /* 1: b 1b */ 234 0x00000000, /* nop */ 235 236 /* Reset */ 237 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 238 0x358C0000, 239 0x000C6438, 240 0x358C1008, 241 0x000C6438, 242 0x358C0010, 243 0x240D0000, /* li t1, 0x00 */ 244 0xA18D0000, /* sb t1, (t0) */ 245 0x1000FFFF, /* 1: b 1b */ 246 0x00000000, /* nop */ 247 248 /* Shutdown */ 249 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 250 0x358C0000, 251 0x000C6438, 252 0x358C1008, 253 0x000C6438, 254 0x358C0010, 255 0x240D00FF, /* li t1, 0xff */ 256 0xA18D0000, /* sb t1, (t0) */ 257 0x1000FFFF, /* 1: b 1b */ 258 0x00000000, /* nop */ 259 /* Suspend */ 260 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 261 0x358C0000, 262 0x000C6438, 263 0x358C1008, 264 0x000C6438, 265 0x358C0010, 266 0x240D0001, /* li t1, 0x01 */ 267 0xA18D0000, /* sb t1, (t0) */ 268 0x03e00008, /* jr ra */ 269 0x00000000 /* nop */ 270 }; 271 272 rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), 273 loader_rommap[LOADER_BOOTROM].base); 274 } 275 276 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 277 Error **errp) 278 { 279 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 280 } 281 282 static void fw_conf_init(unsigned long ram_size) 283 { 284 static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 285 FWCfgState *fw_cfg; 286 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; 287 288 fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); 289 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); 290 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); 291 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 292 fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); 293 fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz()); 294 295 fw_cfg_add_file(fw_cfg, "etc/system-states", 296 g_memdup2(suspend, sizeof(suspend)), sizeof(suspend)); 297 298 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 299 } 300 301 static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) 302 { 303 int ret = 0; 304 void *cmdline_buf; 305 hwaddr cmdline_vaddr; 306 unsigned int *parg_env; 307 308 /* Allocate cmdline_buf for command line. */ 309 cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); 310 cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, 311 loader_memmap[LOADER_CMDLINE].base); 312 313 /* 314 * Layout of cmdline_buf looks like this: 315 * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, 316 * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 317 */ 318 parg_env = (void *)cmdline_buf; 319 320 ret = (3 + 1) * 4; 321 *parg_env++ = cmdline_vaddr + ret; 322 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); 323 324 /* argv1 */ 325 *parg_env++ = cmdline_vaddr + ret; 326 if (initrd_size > 0) 327 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, 328 "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", 329 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 330 initrd_size, loaderparams.kernel_cmdline)); 331 else 332 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", 333 loaderparams.kernel_cmdline)); 334 335 /* argv2 */ 336 *parg_env++ = cmdline_vaddr + 4 * ret; 337 338 rom_add_blob_fixed("cmdline", cmdline_buf, 339 loader_memmap[LOADER_CMDLINE].size, 340 loader_memmap[LOADER_CMDLINE].base); 341 342 g_free(cmdline_buf); 343 344 loaderparams.a0 = 2; 345 loaderparams.a1 = cmdline_vaddr; 346 347 return 0; 348 } 349 350 static uint64_t load_kernel(CPUMIPSState *env) 351 { 352 long kernel_size; 353 ram_addr_t initrd_offset; 354 uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; 355 356 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 357 cpu_mips_kseg0_to_phys, NULL, 358 &kernel_entry, 359 &kernel_low, &kernel_high, 360 NULL, 0, EM_MIPS, 1, 0); 361 if (kernel_size < 0) { 362 error_report("could not load kernel '%s': %s", 363 loaderparams.kernel_filename, 364 load_elf_strerror(kernel_size)); 365 exit(1); 366 } 367 368 /* load initrd */ 369 initrd_size = 0; 370 initrd_offset = 0; 371 if (loaderparams.initrd_filename) { 372 initrd_size = get_image_size(loaderparams.initrd_filename); 373 if (initrd_size > 0) { 374 initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, 375 ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); 376 377 if (initrd_offset + initrd_size > loaderparams.ram_size) { 378 error_report("memory too small for initial ram disk '%s'", 379 loaderparams.initrd_filename); 380 exit(1); 381 } 382 383 initrd_size = load_image_targphys(loaderparams.initrd_filename, 384 initrd_offset, 385 loaderparams.ram_size - initrd_offset); 386 } 387 388 if (initrd_size == (target_ulong) -1) { 389 error_report("could not load initial ram disk '%s'", 390 loaderparams.initrd_filename); 391 exit(1); 392 } 393 } 394 395 /* Setup prom cmdline. */ 396 set_prom_cmdline(initrd_offset, initrd_size); 397 398 return kernel_entry; 399 } 400 401 static void main_cpu_reset(void *opaque) 402 { 403 MIPSCPU *cpu = opaque; 404 CPUMIPSState *env = &cpu->env; 405 406 cpu_reset(CPU(cpu)); 407 408 /* Loongson-3 reset stuff */ 409 if (loaderparams.kernel_filename) { 410 if (cpu == MIPS_CPU(first_cpu)) { 411 env->active_tc.gpr[4] = loaderparams.a0; 412 env->active_tc.gpr[5] = loaderparams.a1; 413 env->active_tc.gpr[6] = loaderparams.a2; 414 env->active_tc.PC = loaderparams.kernel_entry; 415 } 416 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 417 } 418 } 419 420 static inline void loongson3_virt_devices_init(MachineState *machine, 421 DeviceState *pic) 422 { 423 int i; 424 qemu_irq irq; 425 PCIBus *pci_bus; 426 DeviceState *dev; 427 MemoryRegion *mmio_reg, *ecam_reg; 428 MachineClass *mc = MACHINE_GET_CLASS(machine); 429 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 430 431 dev = qdev_new(TYPE_GPEX_HOST); 432 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 433 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 434 435 s->ecam_alias = g_new0(MemoryRegion, 1); 436 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 437 memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", 438 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); 439 memory_region_add_subregion(get_system_memory(), 440 virt_memmap[VIRT_PCIE_ECAM].base, 441 s->ecam_alias); 442 443 s->mmio_alias = g_new0(MemoryRegion, 1); 444 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 445 memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", 446 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, 447 virt_memmap[VIRT_PCIE_MMIO].size); 448 memory_region_add_subregion(get_system_memory(), 449 virt_memmap[VIRT_PCIE_MMIO].base, 450 s->mmio_alias); 451 452 s->pio_alias = g_new0(MemoryRegion, 1); 453 memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", 454 get_system_io(), 0, 455 virt_memmap[VIRT_PCIE_PIO].size); 456 memory_region_add_subregion(get_system_memory(), 457 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); 458 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); 459 460 for (i = 0; i < GPEX_NUM_IRQS; i++) { 461 irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); 462 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 463 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); 464 } 465 msi_nonbroken = true; 466 467 pci_vga_init(pci_bus); 468 469 if (defaults_enabled() && object_class_by_name("pci-ohci")) { 470 USBBus *usb_bus; 471 472 pci_create_simple(pci_bus, -1, "pci-ohci"); 473 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 474 &error_abort)); 475 usb_create_simple(usb_bus, "usb-kbd"); 476 usb_create_simple(usb_bus, "usb-tablet"); 477 } 478 479 pci_init_nic_devices(pci_bus, mc->default_nic); 480 } 481 482 static void mips_loongson3_virt_init(MachineState *machine) 483 { 484 int i; 485 long bios_size; 486 MIPSCPU *cpu; 487 Clock *cpuclk; 488 CPUMIPSState *env; 489 DeviceState *liointc; 490 DeviceState *ipi = NULL; 491 char *filename; 492 const char *kernel_cmdline = machine->kernel_cmdline; 493 const char *kernel_filename = machine->kernel_filename; 494 const char *initrd_filename = machine->initrd_filename; 495 ram_addr_t ram_size = machine->ram_size; 496 MemoryRegion *address_space_mem = get_system_memory(); 497 MemoryRegion *ram = g_new(MemoryRegion, 1); 498 MemoryRegion *bios = g_new(MemoryRegion, 1); 499 MemoryRegion *iomem = g_new(MemoryRegion, 1); 500 MemoryRegion *iocsr = g_new(MemoryRegion, 1); 501 502 /* TODO: TCG will support all CPU types */ 503 if (!kvm_enabled()) { 504 if (!machine->cpu_type) { 505 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); 506 } 507 if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) { 508 error_report("Loongson-3/TCG needs a Loongson-3 series cpu"); 509 exit(1); 510 } 511 } else { 512 if (!machine->cpu_type) { 513 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); 514 } 515 if (!strstr(machine->cpu_type, "Loongson-3A4000")) { 516 error_report("Loongson-3/KVM needs cpu type Loongson-3A4000"); 517 exit(1); 518 } 519 } 520 521 if (ram_size < 512 * MiB) { 522 error_report("Loongson-3 machine needs at least 512MB memory"); 523 exit(1); 524 } 525 526 /* 527 * The whole MMIO range among configure registers doesn't generate 528 * exception when accessing invalid memory. Create some unimplememted 529 * devices to emulate this feature. 530 */ 531 create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); 532 create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); 533 534 memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX); 535 536 /* IPI controller is in kernel for KVM */ 537 if (!kvm_enabled()) { 538 ipi = qdev_new(TYPE_LOONGSON_IPI); 539 qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus); 540 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 541 memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX, 542 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 543 memory_region_add_subregion(iocsr, MAIL_SEND_ADDR, 544 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 545 } 546 547 liointc = qdev_new("loongson.liointc"); 548 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); 549 550 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); 551 552 serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, 553 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), 554 DEVICE_NATIVE_ENDIAN); 555 556 sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, 557 qdev_get_gpio_in(liointc, RTC_IRQ)); 558 559 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 560 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); 561 562 for (i = 0; i < machine->smp.cpus; i++) { 563 int node = i / LOONGSON3_CORE_PER_NODE; 564 int core = i % LOONGSON3_CORE_PER_NODE; 565 int ip; 566 567 /* init CPUs */ 568 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 569 570 /* Init internal devices */ 571 cpu_mips_irq_init_cpu(cpu); 572 cpu_mips_clock_init(cpu); 573 qemu_register_reset(main_cpu_reset, cpu); 574 575 if (ipi) { 576 hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base; 577 base += core * 0x100; 578 qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]); 579 sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base); 580 } 581 582 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { 583 MemoryRegion *core_iocsr = g_new(MemoryRegion, 1); 584 g_autofree char *name = g_strdup_printf("core%d_iocsr", i); 585 memory_region_init_alias(core_iocsr, OBJECT(cpu), name, 586 iocsr, 0, UINT32_MAX); 587 memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr, 588 0, core_iocsr); 589 } 590 591 if (node > 0) { 592 continue; /* Only node-0 can be connected to LIOINTC */ 593 } 594 595 for (ip = 0; ip < 4 ; ip++) { 596 int pin = core * LOONGSON3_CORE_PER_NODE + ip; 597 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), 598 pin, cpu->env.irq[ip + 2]); 599 } 600 } 601 env = &MIPS_CPU(first_cpu)->env; 602 603 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ 604 memory_region_init_rom(bios, NULL, "loongson3.bios", 605 virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); 606 memory_region_init_alias(ram, NULL, "loongson3.lowmem", 607 machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); 608 memory_region_init_io(iomem, NULL, &loongson3_pm_ops, 609 NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); 610 qemu_register_wakeup_support(); 611 612 memory_region_add_subregion(address_space_mem, 613 virt_memmap[VIRT_LOWMEM].base, ram); 614 memory_region_add_subregion(address_space_mem, 615 virt_memmap[VIRT_BIOS_ROM].base, bios); 616 memory_region_add_subregion(address_space_mem, 617 virt_memmap[VIRT_HIGHMEM].base, machine->ram); 618 memory_region_add_subregion(address_space_mem, 619 virt_memmap[VIRT_PM].base, iomem); 620 621 /* 622 * We do not support flash operation, just loading bios.bin as raw BIOS. 623 * Please use -L to set the BIOS path and -bios to set bios name. 624 */ 625 626 if (kernel_filename) { 627 loaderparams.cpu_freq = get_cpu_freq_hz(); 628 loaderparams.ram_size = ram_size; 629 loaderparams.kernel_filename = kernel_filename; 630 loaderparams.kernel_cmdline = kernel_cmdline; 631 loaderparams.initrd_filename = initrd_filename; 632 loaderparams.kernel_entry = load_kernel(env); 633 634 init_boot_rom(); 635 init_boot_param(); 636 } else { 637 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 638 machine->firmware ?: LOONGSON3_BIOSNAME); 639 if (filename) { 640 bios_size = load_image_targphys(filename, 641 virt_memmap[VIRT_BIOS_ROM].base, 642 virt_memmap[VIRT_BIOS_ROM].size); 643 g_free(filename); 644 } else { 645 bios_size = -1; 646 } 647 648 if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && 649 !kernel_filename && !qtest_enabled()) { 650 error_report("Could not load MIPS bios '%s'", machine->firmware); 651 exit(1); 652 } 653 654 fw_conf_init(ram_size); 655 } 656 657 loongson3_virt_devices_init(machine, liointc); 658 } 659 660 static void loongson3v_machine_class_init(ObjectClass *oc, void *data) 661 { 662 MachineClass *mc = MACHINE_CLASS(oc); 663 664 mc->desc = "Loongson-3 Virtualization Platform"; 665 mc->init = mips_loongson3_virt_init; 666 mc->block_default_type = IF_IDE; 667 mc->max_cpus = LOONGSON_MAX_VCPUS; 668 mc->default_ram_id = "loongson3.highram"; 669 mc->default_ram_size = 1600 * MiB; 670 mc->minimum_page_bits = 14; 671 mc->default_nic = "virtio-net-pci"; 672 } 673 674 static const TypeInfo loongson3_machine_types[] = { 675 { 676 .name = TYPE_LOONGSON_MACHINE, 677 .parent = TYPE_MACHINE, 678 .instance_size = sizeof(LoongsonMachineState), 679 .class_init = loongson3v_machine_class_init, 680 } 681 }; 682 683 DEFINE_TYPES(loongson3_machine_types) 684