1 /* 2 * Generic Loongson-3 Platform support 3 * 4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) 5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <https://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with 23 * extensions, 800~2000MHz) 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qemu/cutils.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "elf.h" 32 #include "hw/char/serial-mm.h" 33 #include "hw/intc/loongson_liointc.h" 34 #include "hw/mips/mips.h" 35 #include "hw/mips/fw_cfg.h" 36 #include "hw/mips/loongson3_bootp.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/intc/loongson_ipi.h" 40 #include "hw/loader.h" 41 #include "hw/isa/superio.h" 42 #include "hw/pci/msi.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci/pci_host.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/usb.h" 47 #include "net/net.h" 48 #include "system/kvm.h" 49 #include "system/qtest.h" 50 #include "system/reset.h" 51 #include "system/runstate.h" 52 #include "qemu/error-report.h" 53 54 #define PM_CNTL_MODE 0x10 55 56 #define LOONGSON_MAX_VCPUS 16 57 58 /* 59 * Loongson-3's virtual machine BIOS can be obtained here: 60 * 1, https://github.com/loongson-community/firmware-nonfree 61 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin 62 */ 63 #define LOONGSON3_BIOSNAME "bios_loongson3.bin" 64 65 #define UART_IRQ 0 66 #define RTC_IRQ 1 67 #define PCIE_IRQ_BASE 2 68 69 const MemMapEntry virt_memmap[] = { 70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, 71 [VIRT_PM] = { 0x10080000, 0x100 }, 72 [VIRT_FW_CFG] = { 0x10080100, 0x100 }, 73 [VIRT_RTC] = { 0x10081000, 0x1000 }, 74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, 75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, 76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, 77 [VIRT_UART] = { 0x1fe001e0, 0x8 }, 78 [VIRT_IPI] = { 0x3ff01000, 0x400 }, 79 [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, 80 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 81 [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ 82 }; 83 84 static const MemMapEntry loader_memmap[] = { 85 [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, 86 [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ 87 [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, 88 }; 89 90 static const MemMapEntry loader_rommap[] = { 91 [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, 92 [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, 93 }; 94 95 struct LoongsonMachineState { 96 MachineState parent_obj; 97 MemoryRegion *pio_alias; 98 MemoryRegion *mmio_alias; 99 MemoryRegion *ecam_alias; 100 MemoryRegion *core_iocsr[LOONGSON_MAX_VCPUS]; 101 }; 102 typedef struct LoongsonMachineState LoongsonMachineState; 103 104 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") 105 DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) 106 107 static struct _loaderparams { 108 uint64_t cpu_freq; 109 uint64_t ram_size; 110 const char *kernel_cmdline; 111 const char *kernel_filename; 112 const char *initrd_filename; 113 uint64_t kernel_entry; 114 uint64_t a0, a1, a2; 115 } loaderparams; 116 117 static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) 118 { 119 return 0; 120 } 121 122 static void loongson3_pm_write(void *opaque, hwaddr addr, 123 uint64_t val, unsigned size) 124 { 125 if (addr != PM_CNTL_MODE) { 126 return; 127 } 128 129 switch (val) { 130 case 0x00: 131 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 132 return; 133 case 0x01: 134 qemu_system_suspend_request(); 135 return; 136 case 0xff: 137 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 138 return; 139 default: 140 return; 141 } 142 } 143 144 static const MemoryRegionOps loongson3_pm_ops = { 145 .read = loongson3_pm_read, 146 .write = loongson3_pm_write, 147 .endianness = DEVICE_NATIVE_ENDIAN, 148 .valid = { 149 .min_access_size = 1, 150 .max_access_size = 1 151 } 152 }; 153 154 #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) 155 156 static uint64_t get_cpu_freq_hz(const MIPSCPU *cpu) 157 { 158 #ifdef CONFIG_KVM 159 int ret; 160 uint64_t freq; 161 struct kvm_one_reg freq_reg = { 162 .id = KVM_REG_MIPS_COUNT_HZ, 163 .addr = (uintptr_t)(&freq) 164 }; 165 166 if (kvm_enabled()) { 167 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_ONE_REG, &freq_reg); 168 if (ret >= 0) { 169 return freq * 2; 170 } 171 } 172 #endif 173 return DEF_LOONGSON3_FREQ; 174 } 175 176 static void init_boot_param(void) 177 { 178 static void *p; 179 struct boot_params *bp; 180 181 p = g_malloc0(loader_rommap[LOADER_PARAM].size); 182 bp = p; 183 184 bp->efi.smbios.vers = cpu_to_le16(1); 185 init_reset_system(&(bp->reset_system)); 186 p += ROUND_UP(sizeof(struct boot_params), 64); 187 init_loongson_params(&(bp->efi.smbios.lp), p, 188 current_machine->smp.cpus, 189 loaderparams.cpu_freq, loaderparams.ram_size); 190 191 rom_add_blob_fixed("params_rom", bp, 192 loader_rommap[LOADER_PARAM].size, 193 loader_rommap[LOADER_PARAM].base); 194 195 g_free(bp); 196 197 loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, 198 loader_rommap[LOADER_PARAM].base); 199 } 200 201 static void init_boot_rom(void) 202 { 203 const unsigned int boot_code[] = { 204 0x40086000, /* mfc0 t0, CP0_STATUS */ 205 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ 206 0x01094025, /* or t0, t0, t1 */ 207 0x3C090040, /* lui t1, 0x40 #set bev */ 208 0x01094025, /* or t0, t0, t1 */ 209 0x40886000, /* mtc0 t0, CP0_STATUS */ 210 0x00000000, 211 0x40806800, /* mtc0 zero, CP0_CAUSE */ 212 0x00000000, 213 0x400A7801, /* mfc0 t2, $15, 1 */ 214 0x314A00FF, /* andi t2, 0x0ff */ 215 0x3C089000, /* dli t0, 0x900000003ff01000 */ 216 0x00084438, 217 0x35083FF0, 218 0x00084438, 219 0x35081000, 220 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ 221 0x000B5A00, /* sll t3, 8 */ 222 0x010B4025, /* or t0, t0, t3 */ 223 0x314C000C, /* andi t4, t2, 0xc #node id */ 224 0x000C62BC, /* dsll t4, 42 */ 225 0x010C4025, /* or t0, t0, t4 */ 226 /* WaitForInit: */ 227 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ 228 0x1040FFFE, /* beqz v0, WaitForInit */ 229 0x00000000, /* nop */ 230 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ 231 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ 232 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ 233 0x00400008, /* jr v0 #byebye */ 234 0x00000000, /* nop */ 235 0x1000FFFF, /* 1: b 1b */ 236 0x00000000, /* nop */ 237 238 /* Reset */ 239 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 240 0x358C0000, 241 0x000C6438, 242 0x358C1008, 243 0x000C6438, 244 0x358C0010, 245 0x240D0000, /* li t1, 0x00 */ 246 0xA18D0000, /* sb t1, (t0) */ 247 0x1000FFFF, /* 1: b 1b */ 248 0x00000000, /* nop */ 249 250 /* Shutdown */ 251 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 252 0x358C0000, 253 0x000C6438, 254 0x358C1008, 255 0x000C6438, 256 0x358C0010, 257 0x240D00FF, /* li t1, 0xff */ 258 0xA18D0000, /* sb t1, (t0) */ 259 0x1000FFFF, /* 1: b 1b */ 260 0x00000000, /* nop */ 261 /* Suspend */ 262 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 263 0x358C0000, 264 0x000C6438, 265 0x358C1008, 266 0x000C6438, 267 0x358C0010, 268 0x240D0001, /* li t1, 0x01 */ 269 0xA18D0000, /* sb t1, (t0) */ 270 0x03e00008, /* jr ra */ 271 0x00000000 /* nop */ 272 }; 273 274 rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), 275 loader_rommap[LOADER_BOOTROM].base); 276 } 277 278 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 279 Error **errp) 280 { 281 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 282 } 283 284 static void fw_conf_init(void) 285 { 286 static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 287 FWCfgState *fw_cfg; 288 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; 289 290 fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); 291 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); 292 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); 293 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, loaderparams.ram_size); 294 fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); 295 fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, loaderparams.cpu_freq); 296 297 fw_cfg_add_file(fw_cfg, "etc/system-states", 298 g_memdup2(suspend, sizeof(suspend)), sizeof(suspend)); 299 300 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 301 } 302 303 static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) 304 { 305 int ret = 0; 306 void *cmdline_buf; 307 hwaddr cmdline_vaddr; 308 unsigned int *parg_env; 309 310 /* Allocate cmdline_buf for command line. */ 311 cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); 312 cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, 313 loader_memmap[LOADER_CMDLINE].base); 314 315 /* 316 * Layout of cmdline_buf looks like this: 317 * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, 318 * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 319 */ 320 parg_env = (void *)cmdline_buf; 321 322 ret = (3 + 1) * 4; 323 *parg_env++ = cmdline_vaddr + ret; 324 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); 325 326 /* argv1 */ 327 *parg_env++ = cmdline_vaddr + ret; 328 if (initrd_size > 0) 329 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, 330 "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", 331 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 332 initrd_size, loaderparams.kernel_cmdline)); 333 else 334 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", 335 loaderparams.kernel_cmdline)); 336 337 /* argv2 */ 338 *parg_env++ = cmdline_vaddr + 4 * ret; 339 340 rom_add_blob_fixed("cmdline", cmdline_buf, 341 loader_memmap[LOADER_CMDLINE].size, 342 loader_memmap[LOADER_CMDLINE].base); 343 344 g_free(cmdline_buf); 345 346 loaderparams.a0 = 2; 347 loaderparams.a1 = cmdline_vaddr; 348 349 return 0; 350 } 351 352 static uint64_t load_kernel(CPUMIPSState *env) 353 { 354 long kernel_size; 355 ram_addr_t initrd_offset; 356 uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; 357 358 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 359 cpu_mips_kseg0_to_phys, NULL, 360 &kernel_entry, 361 &kernel_low, &kernel_high, 362 NULL, 0, EM_MIPS, 1, 0); 363 if (kernel_size < 0) { 364 error_report("could not load kernel '%s': %s", 365 loaderparams.kernel_filename, 366 load_elf_strerror(kernel_size)); 367 exit(1); 368 } 369 370 /* load initrd */ 371 initrd_size = 0; 372 initrd_offset = 0; 373 if (loaderparams.initrd_filename) { 374 initrd_size = get_image_size(loaderparams.initrd_filename); 375 if (initrd_size > 0) { 376 initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, 377 ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); 378 379 if (initrd_offset + initrd_size > loaderparams.ram_size) { 380 error_report("memory too small for initial ram disk '%s'", 381 loaderparams.initrd_filename); 382 exit(1); 383 } 384 385 initrd_size = load_image_targphys(loaderparams.initrd_filename, 386 initrd_offset, 387 loaderparams.ram_size - initrd_offset); 388 } 389 390 if (initrd_size == (target_ulong) -1) { 391 error_report("could not load initial ram disk '%s'", 392 loaderparams.initrd_filename); 393 exit(1); 394 } 395 } 396 397 /* Setup prom cmdline. */ 398 set_prom_cmdline(initrd_offset, initrd_size); 399 400 return kernel_entry; 401 } 402 403 static void generic_cpu_reset(void *opaque) 404 { 405 MIPSCPU *cpu = opaque; 406 CPUMIPSState *env = &cpu->env; 407 408 cpu_reset(CPU(cpu)); 409 410 if (loaderparams.kernel_filename) { 411 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 412 } 413 } 414 415 static void main_cpu_reset(void *opaque) 416 { 417 generic_cpu_reset(opaque); 418 419 if (loaderparams.kernel_filename) { 420 MIPSCPU *cpu = opaque; 421 CPUMIPSState *env = &cpu->env; 422 423 env->active_tc.gpr[4] = loaderparams.a0; 424 env->active_tc.gpr[5] = loaderparams.a1; 425 env->active_tc.gpr[6] = loaderparams.a2; 426 env->active_tc.PC = loaderparams.kernel_entry; 427 } 428 } 429 430 static inline void loongson3_virt_devices_init(MachineState *machine, 431 DeviceState *pic) 432 { 433 int i; 434 qemu_irq irq; 435 PCIBus *pci_bus; 436 DeviceState *dev; 437 MemoryRegion *mmio_reg, *ecam_reg; 438 MachineClass *mc = MACHINE_GET_CLASS(machine); 439 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 440 441 dev = qdev_new(TYPE_GPEX_HOST); 442 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 443 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 444 445 s->ecam_alias = g_new0(MemoryRegion, 1); 446 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 447 memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", 448 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); 449 memory_region_add_subregion(get_system_memory(), 450 virt_memmap[VIRT_PCIE_ECAM].base, 451 s->ecam_alias); 452 453 s->mmio_alias = g_new0(MemoryRegion, 1); 454 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 455 memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", 456 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, 457 virt_memmap[VIRT_PCIE_MMIO].size); 458 memory_region_add_subregion(get_system_memory(), 459 virt_memmap[VIRT_PCIE_MMIO].base, 460 s->mmio_alias); 461 462 s->pio_alias = g_new0(MemoryRegion, 1); 463 memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", 464 get_system_io(), 0, 465 virt_memmap[VIRT_PCIE_PIO].size); 466 memory_region_add_subregion(get_system_memory(), 467 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); 468 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); 469 470 for (i = 0; i < PCI_NUM_PINS; i++) { 471 irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); 472 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 473 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); 474 } 475 msi_nonbroken = true; 476 477 pci_vga_init(pci_bus); 478 479 if (defaults_enabled() && object_class_by_name("pci-ohci")) { 480 USBBus *usb_bus; 481 482 pci_create_simple(pci_bus, -1, "pci-ohci"); 483 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 484 &error_abort)); 485 usb_create_simple(usb_bus, "usb-kbd"); 486 usb_create_simple(usb_bus, "usb-tablet"); 487 } 488 489 pci_init_nic_devices(pci_bus, mc->default_nic); 490 } 491 492 static void mips_loongson3_virt_init(MachineState *machine) 493 { 494 int i; 495 long bios_size; 496 MIPSCPU *cpu = NULL; 497 Clock *cpuclk; 498 DeviceState *liointc; 499 DeviceState *ipi = NULL; 500 char *filename; 501 const char *kernel_cmdline = machine->kernel_cmdline; 502 const char *kernel_filename = machine->kernel_filename; 503 const char *initrd_filename = machine->initrd_filename; 504 ram_addr_t ram_size = machine->ram_size; 505 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 506 MemoryRegion *address_space_mem = get_system_memory(); 507 MemoryRegion *ram = g_new(MemoryRegion, 1); 508 MemoryRegion *bios = g_new(MemoryRegion, 1); 509 MemoryRegion *iomem = g_new(MemoryRegion, 1); 510 MemoryRegion *iocsr = g_new(MemoryRegion, 1); 511 512 /* TODO: TCG will support all CPU types */ 513 if (!kvm_enabled()) { 514 if (!machine->cpu_type) { 515 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); 516 } 517 if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) { 518 error_report("Loongson-3/TCG needs a Loongson-3 series cpu"); 519 exit(1); 520 } 521 } else { 522 if (!machine->cpu_type) { 523 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); 524 } 525 if (!strstr(machine->cpu_type, "Loongson-3A4000")) { 526 error_report("Loongson-3/KVM needs cpu type Loongson-3A4000"); 527 exit(1); 528 } 529 } 530 531 if (ram_size < 512 * MiB) { 532 error_report("Loongson-3 machine needs at least 512MB memory"); 533 exit(1); 534 } 535 536 /* 537 * The whole MMIO range among configure registers doesn't generate 538 * exception when accessing invalid memory. Create some unimplememted 539 * devices to emulate this feature. 540 */ 541 create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); 542 create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); 543 544 memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX); 545 546 /* IPI controller is in kernel for KVM */ 547 if (!kvm_enabled()) { 548 ipi = qdev_new(TYPE_LOONGSON_IPI); 549 qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus); 550 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 551 memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX, 552 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 553 memory_region_add_subregion(iocsr, MAIL_SEND_ADDR, 554 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 555 } 556 557 liointc = qdev_new("loongson.liointc"); 558 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); 559 560 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); 561 562 serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, 563 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), 564 DEVICE_NATIVE_ENDIAN); 565 566 sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, 567 qdev_get_gpio_in(liointc, RTC_IRQ)); 568 569 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 570 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); 571 572 for (i = machine->smp.cpus - 1; i >= 0; --i) { 573 int node = i / LOONGSON3_CORE_PER_NODE; 574 int core = i % LOONGSON3_CORE_PER_NODE; 575 int ip; 576 577 /* init CPUs */ 578 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); 579 580 /* Init internal devices */ 581 cpu_mips_irq_init_cpu(cpu); 582 cpu_mips_clock_init(cpu); 583 qemu_register_reset(i ? generic_cpu_reset : main_cpu_reset, cpu); 584 585 if (!kvm_enabled()) { 586 hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base; 587 base += core * 0x100; 588 qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]); 589 sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base); 590 } 591 592 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { 593 MemoryRegion *core_iocsr = g_new(MemoryRegion, 1); 594 g_autofree char *name = g_strdup_printf("core%d_iocsr", i); 595 memory_region_init_alias(core_iocsr, OBJECT(cpu), name, 596 iocsr, 0, UINT32_MAX); 597 memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr, 598 0, core_iocsr); 599 s->core_iocsr[i] = core_iocsr; 600 } 601 602 if (node > 0) { 603 continue; /* Only node-0 can be connected to LIOINTC */ 604 } 605 606 for (ip = 0; ip < 4 ; ip++) { 607 int pin = core * LOONGSON3_CORE_PER_NODE + ip; 608 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), 609 pin, cpu->env.irq[ip + 2]); 610 } 611 } 612 assert(cpu); /* This variable points to the first created cpu. */ 613 614 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ 615 memory_region_init_rom(bios, NULL, "loongson3.bios", 616 virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); 617 memory_region_init_alias(ram, NULL, "loongson3.lowmem", 618 machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); 619 memory_region_init_io(iomem, NULL, &loongson3_pm_ops, 620 NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); 621 qemu_register_wakeup_support(); 622 623 memory_region_add_subregion(address_space_mem, 624 virt_memmap[VIRT_LOWMEM].base, ram); 625 memory_region_add_subregion(address_space_mem, 626 virt_memmap[VIRT_BIOS_ROM].base, bios); 627 memory_region_add_subregion(address_space_mem, 628 virt_memmap[VIRT_HIGHMEM].base, machine->ram); 629 memory_region_add_subregion(address_space_mem, 630 virt_memmap[VIRT_PM].base, iomem); 631 632 /* 633 * We do not support flash operation, just loading bios.bin as raw BIOS. 634 * Please use -L to set the BIOS path and -bios to set bios name. 635 */ 636 637 loaderparams.cpu_freq = get_cpu_freq_hz(cpu); 638 loaderparams.ram_size = ram_size; 639 if (kernel_filename) { 640 loaderparams.kernel_filename = kernel_filename; 641 loaderparams.kernel_cmdline = kernel_cmdline; 642 loaderparams.initrd_filename = initrd_filename; 643 loaderparams.kernel_entry = load_kernel(&cpu->env); 644 645 init_boot_rom(); 646 init_boot_param(); 647 } else { 648 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 649 machine->firmware ?: LOONGSON3_BIOSNAME); 650 if (filename) { 651 bios_size = load_image_targphys(filename, 652 virt_memmap[VIRT_BIOS_ROM].base, 653 virt_memmap[VIRT_BIOS_ROM].size); 654 g_free(filename); 655 } else { 656 bios_size = -1; 657 } 658 659 if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && 660 !kernel_filename && !qtest_enabled()) { 661 error_report("Could not load MIPS bios '%s'", machine->firmware); 662 exit(1); 663 } 664 665 fw_conf_init(); 666 } 667 668 loongson3_virt_devices_init(machine, liointc); 669 } 670 671 static void loongson3v_machine_class_init(ObjectClass *oc, void *data) 672 { 673 MachineClass *mc = MACHINE_CLASS(oc); 674 675 mc->desc = "Loongson-3 Virtualization Platform"; 676 mc->init = mips_loongson3_virt_init; 677 mc->block_default_type = IF_IDE; 678 mc->max_cpus = LOONGSON_MAX_VCPUS; 679 mc->default_ram_id = "loongson3.highram"; 680 mc->default_ram_size = 1600 * MiB; 681 mc->minimum_page_bits = 14; 682 mc->default_nic = "virtio-net-pci"; 683 } 684 685 static const TypeInfo loongson3_machine_types[] = { 686 { 687 .name = TYPE_LOONGSON_MACHINE, 688 .parent = TYPE_MACHINE, 689 .instance_size = sizeof(LoongsonMachineState), 690 .class_init = loongson3v_machine_class_init, 691 } 692 }; 693 694 DEFINE_TYPES(loongson3_machine_types) 695