1 /* 2 * Generic Loongson-3 Platform support 3 * 4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) 5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <https://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with 23 * extensions, 800~2000MHz) 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qemu/cutils.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "elf.h" 32 #include "hw/char/serial.h" 33 #include "hw/intc/loongson_liointc.h" 34 #include "hw/mips/mips.h" 35 #include "hw/mips/cpudevs.h" 36 #include "hw/mips/fw_cfg.h" 37 #include "hw/mips/loongson3_bootp.h" 38 #include "hw/misc/unimp.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/loader.h" 41 #include "hw/isa/superio.h" 42 #include "hw/pci/msi.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci/pci_host.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/usb.h" 47 #include "net/net.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "sysemu/reset.h" 51 #include "sysemu/runstate.h" 52 #include "qemu/error-report.h" 53 54 #define PM_CNTL_MODE 0x10 55 56 #define LOONGSON_MAX_VCPUS 16 57 58 /* 59 * Loongson-3's virtual machine BIOS can be obtained here: 60 * 1, https://github.com/loongson-community/firmware-nonfree 61 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin 62 */ 63 #define LOONGSON3_BIOSNAME "bios_loongson3.bin" 64 65 #define UART_IRQ 0 66 #define RTC_IRQ 1 67 #define PCIE_IRQ_BASE 2 68 69 const MemMapEntry virt_memmap[] = { 70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, 71 [VIRT_PM] = { 0x10080000, 0x100 }, 72 [VIRT_FW_CFG] = { 0x10080100, 0x100 }, 73 [VIRT_RTC] = { 0x10081000, 0x1000 }, 74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, 75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, 76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, 77 [VIRT_UART] = { 0x1fe001e0, 0x8 }, 78 [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, 79 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 80 [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ 81 }; 82 83 static const MemMapEntry loader_memmap[] = { 84 [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, 85 [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ 86 [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, 87 }; 88 89 static const MemMapEntry loader_rommap[] = { 90 [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, 91 [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, 92 }; 93 94 struct LoongsonMachineState { 95 MachineState parent_obj; 96 MemoryRegion *pio_alias; 97 MemoryRegion *mmio_alias; 98 MemoryRegion *ecam_alias; 99 }; 100 typedef struct LoongsonMachineState LoongsonMachineState; 101 102 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") 103 DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) 104 105 static struct _loaderparams { 106 uint64_t cpu_freq; 107 uint64_t ram_size; 108 const char *kernel_cmdline; 109 const char *kernel_filename; 110 const char *initrd_filename; 111 uint64_t kernel_entry; 112 uint64_t a0, a1, a2; 113 } loaderparams; 114 115 static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) 116 { 117 return 0; 118 } 119 120 static void loongson3_pm_write(void *opaque, hwaddr addr, 121 uint64_t val, unsigned size) 122 { 123 if (addr != PM_CNTL_MODE) { 124 return; 125 } 126 127 switch (val) { 128 case 0x00: 129 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 130 return; 131 case 0xff: 132 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 133 return; 134 default: 135 return; 136 } 137 } 138 139 static const MemoryRegionOps loongson3_pm_ops = { 140 .read = loongson3_pm_read, 141 .write = loongson3_pm_write, 142 .endianness = DEVICE_NATIVE_ENDIAN, 143 .valid = { 144 .min_access_size = 1, 145 .max_access_size = 1 146 } 147 }; 148 149 #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) 150 151 static uint64_t get_cpu_freq_hz(void) 152 { 153 #ifdef CONFIG_KVM 154 int ret; 155 uint64_t freq; 156 struct kvm_one_reg freq_reg = { 157 .id = KVM_REG_MIPS_COUNT_HZ, 158 .addr = (uintptr_t)(&freq) 159 }; 160 161 if (kvm_enabled()) { 162 ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg); 163 if (ret >= 0) { 164 return freq * 2; 165 } 166 } 167 #endif 168 return DEF_LOONGSON3_FREQ; 169 } 170 171 static void init_boot_param(void) 172 { 173 static void *p; 174 struct boot_params *bp; 175 176 p = g_malloc0(loader_rommap[LOADER_PARAM].size); 177 bp = p; 178 179 bp->efi.smbios.vers = cpu_to_le16(1); 180 init_reset_system(&(bp->reset_system)); 181 p += ROUND_UP(sizeof(struct boot_params), 64); 182 init_loongson_params(&(bp->efi.smbios.lp), p, 183 loaderparams.cpu_freq, loaderparams.ram_size); 184 185 rom_add_blob_fixed("params_rom", bp, 186 loader_rommap[LOADER_PARAM].size, 187 loader_rommap[LOADER_PARAM].base); 188 189 g_free(bp); 190 191 loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, 192 loader_rommap[LOADER_PARAM].base); 193 } 194 195 static void init_boot_rom(void) 196 { 197 const unsigned int boot_code[] = { 198 0x40086000, /* mfc0 t0, CP0_STATUS */ 199 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ 200 0x01094025, /* or t0, t0, t1 */ 201 0x3C090040, /* lui t1, 0x40 #set bev */ 202 0x01094025, /* or t0, t0, t1 */ 203 0x40886000, /* mtc0 t0, CP0_STATUS */ 204 0x00000000, 205 0x40806800, /* mtc0 zero, CP0_CAUSE */ 206 0x00000000, 207 0x400A7801, /* mfc0 t2, $15, 1 */ 208 0x314A00FF, /* andi t2, 0x0ff */ 209 0x3C089000, /* dli t0, 0x900000003ff01000 */ 210 0x00084438, 211 0x35083FF0, 212 0x00084438, 213 0x35081000, 214 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ 215 0x000B5A00, /* sll t3, 8 */ 216 0x010B4025, /* or t0, t0, t3 */ 217 0x314C000C, /* andi t4, t2, 0xc #node id */ 218 0x000C62BC, /* dsll t4, 42 */ 219 0x010C4025, /* or t0, t0, t4 */ 220 /* WaitForInit: */ 221 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ 222 0x1040FFFE, /* beqz v0, WaitForInit */ 223 0x00000000, /* nop */ 224 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ 225 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ 226 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ 227 0x00400008, /* jr v0 #byebye */ 228 0x00000000, /* nop */ 229 0x1000FFFF, /* 1: b 1b */ 230 0x00000000, /* nop */ 231 232 /* Reset */ 233 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 234 0x358C0000, 235 0x000C6438, 236 0x358C1008, 237 0x000C6438, 238 0x358C0010, 239 0x240D0000, /* li t1, 0x00 */ 240 0xA18D0000, /* sb t1, (t0) */ 241 0x1000FFFF, /* 1: b 1b */ 242 0x00000000, /* nop */ 243 244 /* Shutdown */ 245 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 246 0x358C0000, 247 0x000C6438, 248 0x358C1008, 249 0x000C6438, 250 0x358C0010, 251 0x240D00FF, /* li t1, 0xff */ 252 0xA18D0000, /* sb t1, (t0) */ 253 0x1000FFFF, /* 1: b 1b */ 254 0x00000000 /* nop */ 255 }; 256 257 rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), 258 loader_rommap[LOADER_BOOTROM].base); 259 } 260 261 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 262 Error **errp) 263 { 264 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 265 } 266 267 static void fw_conf_init(unsigned long ram_size) 268 { 269 FWCfgState *fw_cfg; 270 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; 271 272 fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); 273 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); 274 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); 275 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 276 fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); 277 fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz()); 278 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 279 } 280 281 static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) 282 { 283 int ret = 0; 284 void *cmdline_buf; 285 hwaddr cmdline_vaddr; 286 unsigned int *parg_env; 287 288 /* Allocate cmdline_buf for command line. */ 289 cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); 290 cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, 291 loader_memmap[LOADER_CMDLINE].base); 292 293 /* 294 * Layout of cmdline_buf looks like this: 295 * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, 296 * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 297 */ 298 parg_env = (void *)cmdline_buf; 299 300 ret = (3 + 1) * 4; 301 *parg_env++ = cmdline_vaddr + ret; 302 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); 303 304 /* argv1 */ 305 *parg_env++ = cmdline_vaddr + ret; 306 if (initrd_size > 0) 307 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, 308 "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", 309 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 310 initrd_size, loaderparams.kernel_cmdline)); 311 else 312 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", 313 loaderparams.kernel_cmdline)); 314 315 /* argv2 */ 316 *parg_env++ = cmdline_vaddr + 4 * ret; 317 318 rom_add_blob_fixed("cmdline", cmdline_buf, 319 loader_memmap[LOADER_CMDLINE].size, 320 loader_memmap[LOADER_CMDLINE].base); 321 322 g_free(cmdline_buf); 323 324 loaderparams.a0 = 2; 325 loaderparams.a1 = cmdline_vaddr; 326 327 return 0; 328 } 329 330 static uint64_t load_kernel(CPUMIPSState *env) 331 { 332 long kernel_size; 333 ram_addr_t initrd_offset; 334 uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; 335 336 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 337 cpu_mips_kseg0_to_phys, NULL, 338 (uint64_t *)&kernel_entry, 339 (uint64_t *)&kernel_low, (uint64_t *)&kernel_high, 340 NULL, 0, EM_MIPS, 1, 0); 341 if (kernel_size < 0) { 342 error_report("could not load kernel '%s': %s", 343 loaderparams.kernel_filename, 344 load_elf_strerror(kernel_size)); 345 exit(1); 346 } 347 348 /* load initrd */ 349 initrd_size = 0; 350 initrd_offset = 0; 351 if (loaderparams.initrd_filename) { 352 initrd_size = get_image_size(loaderparams.initrd_filename); 353 if (initrd_size > 0) { 354 initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, 355 ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); 356 357 if (initrd_offset + initrd_size > loaderparams.ram_size) { 358 error_report("memory too small for initial ram disk '%s'", 359 loaderparams.initrd_filename); 360 exit(1); 361 } 362 363 initrd_size = load_image_targphys(loaderparams.initrd_filename, 364 initrd_offset, 365 loaderparams.ram_size - initrd_offset); 366 } 367 368 if (initrd_size == (target_ulong) -1) { 369 error_report("could not load initial ram disk '%s'", 370 loaderparams.initrd_filename); 371 exit(1); 372 } 373 } 374 375 /* Setup prom cmdline. */ 376 set_prom_cmdline(initrd_offset, initrd_size); 377 378 return kernel_entry; 379 } 380 381 static void main_cpu_reset(void *opaque) 382 { 383 MIPSCPU *cpu = opaque; 384 CPUMIPSState *env = &cpu->env; 385 386 cpu_reset(CPU(cpu)); 387 388 /* Loongson-3 reset stuff */ 389 if (loaderparams.kernel_filename) { 390 if (cpu == MIPS_CPU(first_cpu)) { 391 env->active_tc.gpr[4] = loaderparams.a0; 392 env->active_tc.gpr[5] = loaderparams.a1; 393 env->active_tc.gpr[6] = loaderparams.a2; 394 env->active_tc.PC = loaderparams.kernel_entry; 395 } 396 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 397 } 398 } 399 400 static inline void loongson3_virt_devices_init(MachineState *machine, 401 DeviceState *pic) 402 { 403 int i; 404 qemu_irq irq; 405 PCIBus *pci_bus; 406 DeviceState *dev; 407 MemoryRegion *mmio_reg, *ecam_reg; 408 MachineClass *mc = MACHINE_GET_CLASS(machine); 409 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 410 411 dev = qdev_new(TYPE_GPEX_HOST); 412 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 413 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 414 415 s->ecam_alias = g_new0(MemoryRegion, 1); 416 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 417 memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", 418 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); 419 memory_region_add_subregion(get_system_memory(), 420 virt_memmap[VIRT_PCIE_ECAM].base, 421 s->ecam_alias); 422 423 s->mmio_alias = g_new0(MemoryRegion, 1); 424 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 425 memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", 426 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, 427 virt_memmap[VIRT_PCIE_MMIO].size); 428 memory_region_add_subregion(get_system_memory(), 429 virt_memmap[VIRT_PCIE_MMIO].base, 430 s->mmio_alias); 431 432 s->pio_alias = g_new0(MemoryRegion, 1); 433 memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", 434 get_system_io(), 0, 435 virt_memmap[VIRT_PCIE_PIO].size); 436 memory_region_add_subregion(get_system_memory(), 437 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); 438 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); 439 440 for (i = 0; i < GPEX_NUM_IRQS; i++) { 441 irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); 442 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 443 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); 444 } 445 msi_nonbroken = true; 446 447 pci_vga_init(pci_bus); 448 449 if (defaults_enabled() && object_class_by_name("pci-ohci")) { 450 pci_create_simple(pci_bus, -1, "pci-ohci"); 451 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 452 usb_create_simple(usb_bus_find(-1), "usb-tablet"); 453 } 454 455 for (i = 0; i < nb_nics; i++) { 456 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 457 } 458 } 459 460 static void mips_loongson3_virt_init(MachineState *machine) 461 { 462 int i; 463 long bios_size; 464 MIPSCPU *cpu; 465 Clock *cpuclk; 466 CPUMIPSState *env; 467 DeviceState *liointc; 468 char *filename; 469 const char *kernel_cmdline = machine->kernel_cmdline; 470 const char *kernel_filename = machine->kernel_filename; 471 const char *initrd_filename = machine->initrd_filename; 472 ram_addr_t ram_size = machine->ram_size; 473 MemoryRegion *address_space_mem = get_system_memory(); 474 MemoryRegion *ram = g_new(MemoryRegion, 1); 475 MemoryRegion *bios = g_new(MemoryRegion, 1); 476 MemoryRegion *iomem = g_new(MemoryRegion, 1); 477 478 /* TODO: TCG will support all CPU types */ 479 if (!kvm_enabled()) { 480 if (!machine->cpu_type) { 481 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); 482 } 483 if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) { 484 error_report("Loongson-3/TCG needs a Loongson-3 series cpu"); 485 exit(1); 486 } 487 } else { 488 if (!machine->cpu_type) { 489 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); 490 } 491 if (!strstr(machine->cpu_type, "Loongson-3A4000")) { 492 error_report("Loongson-3/KVM needs cpu type Loongson-3A4000"); 493 exit(1); 494 } 495 } 496 497 if (ram_size < 512 * MiB) { 498 error_report("Loongson-3 machine needs at least 512MB memory"); 499 exit(1); 500 } 501 502 /* 503 * The whole MMIO range among configure registers doesn't generate 504 * exception when accessing invalid memory. Create some unimplememted 505 * devices to emulate this feature. 506 */ 507 create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); 508 create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); 509 510 liointc = qdev_new("loongson.liointc"); 511 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); 512 513 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); 514 515 serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, 516 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), 517 DEVICE_NATIVE_ENDIAN); 518 519 sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, 520 qdev_get_gpio_in(liointc, RTC_IRQ)); 521 522 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 523 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); 524 525 for (i = 0; i < machine->smp.cpus; i++) { 526 int ip; 527 528 /* init CPUs */ 529 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 530 531 /* Init internal devices */ 532 cpu_mips_irq_init_cpu(cpu); 533 cpu_mips_clock_init(cpu); 534 qemu_register_reset(main_cpu_reset, cpu); 535 536 if (i >= 4) { 537 continue; /* Only node-0 can be connected to LIOINTC */ 538 } 539 540 for (ip = 0; ip < 4 ; ip++) { 541 int pin = i * 4 + ip; 542 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), 543 pin, cpu->env.irq[ip + 2]); 544 } 545 } 546 env = &MIPS_CPU(first_cpu)->env; 547 548 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ 549 memory_region_init_rom(bios, NULL, "loongson3.bios", 550 virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); 551 memory_region_init_alias(ram, NULL, "loongson3.lowmem", 552 machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); 553 memory_region_init_io(iomem, NULL, &loongson3_pm_ops, 554 NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); 555 556 memory_region_add_subregion(address_space_mem, 557 virt_memmap[VIRT_LOWMEM].base, ram); 558 memory_region_add_subregion(address_space_mem, 559 virt_memmap[VIRT_BIOS_ROM].base, bios); 560 memory_region_add_subregion(address_space_mem, 561 virt_memmap[VIRT_HIGHMEM].base, machine->ram); 562 memory_region_add_subregion(address_space_mem, 563 virt_memmap[VIRT_PM].base, iomem); 564 565 /* 566 * We do not support flash operation, just loading bios.bin as raw BIOS. 567 * Please use -L to set the BIOS path and -bios to set bios name. 568 */ 569 570 if (kernel_filename) { 571 loaderparams.cpu_freq = get_cpu_freq_hz(); 572 loaderparams.ram_size = ram_size; 573 loaderparams.kernel_filename = kernel_filename; 574 loaderparams.kernel_cmdline = kernel_cmdline; 575 loaderparams.initrd_filename = initrd_filename; 576 loaderparams.kernel_entry = load_kernel(env); 577 578 init_boot_rom(); 579 init_boot_param(); 580 } else { 581 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 582 machine->firmware ?: LOONGSON3_BIOSNAME); 583 if (filename) { 584 bios_size = load_image_targphys(filename, 585 virt_memmap[VIRT_BIOS_ROM].base, 586 virt_memmap[VIRT_BIOS_ROM].size); 587 g_free(filename); 588 } else { 589 bios_size = -1; 590 } 591 592 if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && 593 !kernel_filename && !qtest_enabled()) { 594 error_report("Could not load MIPS bios '%s'", machine->firmware); 595 exit(1); 596 } 597 598 fw_conf_init(ram_size); 599 } 600 601 loongson3_virt_devices_init(machine, liointc); 602 } 603 604 static void loongson3v_machine_class_init(ObjectClass *oc, void *data) 605 { 606 MachineClass *mc = MACHINE_CLASS(oc); 607 608 mc->desc = "Loongson-3 Virtualization Platform"; 609 mc->init = mips_loongson3_virt_init; 610 mc->block_default_type = IF_IDE; 611 mc->max_cpus = LOONGSON_MAX_VCPUS; 612 mc->default_ram_id = "loongson3.highram"; 613 mc->default_ram_size = 1600 * MiB; 614 mc->minimum_page_bits = 14; 615 mc->default_nic = "virtio-net-pci"; 616 } 617 618 static const TypeInfo loongson3_machine_types[] = { 619 { 620 .name = TYPE_LOONGSON_MACHINE, 621 .parent = TYPE_MACHINE, 622 .instance_size = sizeof(LoongsonMachineState), 623 .class_init = loongson3v_machine_class_init, 624 } 625 }; 626 627 DEFINE_TYPES(loongson3_machine_types) 628