1 /* 2 * Generic Loongson-3 Platform support 3 * 4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) 5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <https://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with 23 * extensions, 800~2000MHz) 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "qemu/units.h" 29 #include "qemu/cutils.h" 30 #include "qemu/datadir.h" 31 #include "qapi/error.h" 32 #include "cpu.h" 33 #include "elf.h" 34 #include "kvm_mips.h" 35 #include "hw/boards.h" 36 #include "hw/char/serial.h" 37 #include "hw/intc/loongson_liointc.h" 38 #include "hw/mips/mips.h" 39 #include "hw/mips/cpudevs.h" 40 #include "hw/mips/fw_cfg.h" 41 #include "hw/mips/loongson3_bootp.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/intc/i8259.h" 44 #include "hw/loader.h" 45 #include "hw/isa/superio.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci/pci.h" 48 #include "hw/pci/pci_host.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/usb.h" 51 #include "net/net.h" 52 #include "exec/address-spaces.h" 53 #include "sysemu/kvm.h" 54 #include "sysemu/qtest.h" 55 #include "sysemu/reset.h" 56 #include "sysemu/runstate.h" 57 #include "qemu/error-report.h" 58 59 #define PM_CNTL_MODE 0x10 60 61 #define LOONGSON_MAX_VCPUS 16 62 63 /* 64 * Loongson-3's virtual machine BIOS can be obtained here: 65 * 1, https://github.com/loongson-community/firmware-nonfree 66 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin 67 */ 68 #define LOONGSON3_BIOSNAME "bios_loongson3.bin" 69 70 #define UART_IRQ 0 71 #define RTC_IRQ 1 72 #define PCIE_IRQ_BASE 2 73 74 const MemMapEntry virt_memmap[] = { 75 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, 76 [VIRT_PM] = { 0x10080000, 0x100 }, 77 [VIRT_FW_CFG] = { 0x10080100, 0x100 }, 78 [VIRT_RTC] = { 0x10081000, 0x1000 }, 79 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, 80 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, 81 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, 82 [VIRT_UART] = { 0x1fe001e0, 0x8 }, 83 [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, 84 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 85 [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ 86 }; 87 88 static const MemMapEntry loader_memmap[] = { 89 [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, 90 [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ 91 [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, 92 }; 93 94 static const MemMapEntry loader_rommap[] = { 95 [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, 96 [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, 97 }; 98 99 struct LoongsonMachineState { 100 MachineState parent_obj; 101 MemoryRegion *pio_alias; 102 MemoryRegion *mmio_alias; 103 MemoryRegion *ecam_alias; 104 }; 105 typedef struct LoongsonMachineState LoongsonMachineState; 106 107 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") 108 DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) 109 110 static struct _loaderparams { 111 uint64_t cpu_freq; 112 uint64_t ram_size; 113 const char *kernel_cmdline; 114 const char *kernel_filename; 115 const char *initrd_filename; 116 uint64_t kernel_entry; 117 uint64_t a0, a1, a2; 118 } loaderparams; 119 120 static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) 121 { 122 return 0; 123 } 124 125 static void loongson3_pm_write(void *opaque, hwaddr addr, 126 uint64_t val, unsigned size) 127 { 128 if (addr != PM_CNTL_MODE) { 129 return; 130 } 131 132 switch (val) { 133 case 0x00: 134 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 135 return; 136 case 0xff: 137 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 138 return; 139 default: 140 return; 141 } 142 } 143 144 static const MemoryRegionOps loongson3_pm_ops = { 145 .read = loongson3_pm_read, 146 .write = loongson3_pm_write, 147 .endianness = DEVICE_NATIVE_ENDIAN, 148 .valid = { 149 .min_access_size = 1, 150 .max_access_size = 1 151 } 152 }; 153 154 #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) 155 156 static uint64_t get_cpu_freq_hz(void) 157 { 158 #ifdef CONFIG_KVM 159 int ret; 160 uint64_t freq; 161 struct kvm_one_reg freq_reg = { 162 .id = KVM_REG_MIPS_COUNT_HZ, 163 .addr = (uintptr_t)(&freq) 164 }; 165 166 if (kvm_enabled()) { 167 ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg); 168 if (ret >= 0) { 169 return freq * 2; 170 } 171 } 172 #endif 173 return DEF_LOONGSON3_FREQ; 174 } 175 176 static void init_boot_param(void) 177 { 178 static void *p; 179 struct boot_params *bp; 180 181 p = g_malloc0(loader_rommap[LOADER_PARAM].size); 182 bp = p; 183 184 bp->efi.smbios.vers = cpu_to_le16(1); 185 init_reset_system(&(bp->reset_system)); 186 p += ROUND_UP(sizeof(struct boot_params), 64); 187 init_loongson_params(&(bp->efi.smbios.lp), p, 188 loaderparams.cpu_freq, loaderparams.ram_size); 189 190 rom_add_blob_fixed("params_rom", bp, 191 loader_rommap[LOADER_PARAM].size, 192 loader_rommap[LOADER_PARAM].base); 193 194 g_free(bp); 195 196 loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, 197 loader_rommap[LOADER_PARAM].base); 198 } 199 200 static void init_boot_rom(void) 201 { 202 const unsigned int boot_code[] = { 203 0x40086000, /* mfc0 t0, CP0_STATUS */ 204 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ 205 0x01094025, /* or t0, t0, t1 */ 206 0x3C090040, /* lui t1, 0x40 #set bev */ 207 0x01094025, /* or t0, t0, t1 */ 208 0x40886000, /* mtc0 t0, CP0_STATUS */ 209 0x00000000, 210 0x40806800, /* mtc0 zero, CP0_CAUSE */ 211 0x00000000, 212 0x400A7801, /* mfc0 t2, $15, 1 */ 213 0x314A00FF, /* andi t2, 0x0ff */ 214 0x3C089000, /* dli t0, 0x900000003ff01000 */ 215 0x00084438, 216 0x35083FF0, 217 0x00084438, 218 0x35081000, 219 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ 220 0x000B5A00, /* sll t3, 8 */ 221 0x010B4025, /* or t0, t0, t3 */ 222 0x314C000C, /* andi t4, t2, 0xc #node id */ 223 0x000C62BC, /* dsll t4, 42 */ 224 0x010C4025, /* or t0, t0, t4 */ 225 /* WaitForInit: */ 226 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ 227 0x1040FFFE, /* beqz v0, WaitForInit */ 228 0x00000000, /* nop */ 229 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ 230 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ 231 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ 232 0x00400008, /* jr v0 #byebye */ 233 0x00000000, /* nop */ 234 0x1000FFFF, /* 1: b 1b */ 235 0x00000000, /* nop */ 236 237 /* Reset */ 238 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 239 0x358C0000, 240 0x000C6438, 241 0x358C1008, 242 0x000C6438, 243 0x358C0010, 244 0x240D0000, /* li t1, 0x00 */ 245 0xA18D0000, /* sb t1, (t0) */ 246 0x1000FFFF, /* 1: b 1b */ 247 0x00000000, /* nop */ 248 249 /* Shutdown */ 250 0x3C0C9000, /* dli t0, 0x9000000010080010 */ 251 0x358C0000, 252 0x000C6438, 253 0x358C1008, 254 0x000C6438, 255 0x358C0010, 256 0x240D00FF, /* li t1, 0xff */ 257 0xA18D0000, /* sb t1, (t0) */ 258 0x1000FFFF, /* 1: b 1b */ 259 0x00000000 /* nop */ 260 }; 261 262 rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), 263 loader_rommap[LOADER_BOOTROM].base); 264 } 265 266 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 267 Error **errp) 268 { 269 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 270 } 271 272 static void fw_conf_init(unsigned long ram_size) 273 { 274 FWCfgState *fw_cfg; 275 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; 276 277 fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); 278 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); 279 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); 280 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 281 fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); 282 fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz()); 283 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 284 } 285 286 static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) 287 { 288 int ret = 0; 289 void *cmdline_buf; 290 hwaddr cmdline_vaddr; 291 unsigned int *parg_env; 292 293 /* Allocate cmdline_buf for command line. */ 294 cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); 295 cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, 296 loader_memmap[LOADER_CMDLINE].base); 297 298 /* 299 * Layout of cmdline_buf looks like this: 300 * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, 301 * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 302 */ 303 parg_env = (void *)cmdline_buf; 304 305 ret = (3 + 1) * 4; 306 *parg_env++ = cmdline_vaddr + ret; 307 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); 308 309 /* argv1 */ 310 *parg_env++ = cmdline_vaddr + ret; 311 if (initrd_size > 0) 312 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, 313 "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", 314 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 315 initrd_size, loaderparams.kernel_cmdline)); 316 else 317 ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", 318 loaderparams.kernel_cmdline)); 319 320 /* argv2 */ 321 *parg_env++ = cmdline_vaddr + 4 * ret; 322 323 rom_add_blob_fixed("cmdline", cmdline_buf, 324 loader_memmap[LOADER_CMDLINE].size, 325 loader_memmap[LOADER_CMDLINE].base); 326 327 g_free(cmdline_buf); 328 329 loaderparams.a0 = 2; 330 loaderparams.a1 = cmdline_vaddr; 331 332 return 0; 333 } 334 335 static uint64_t load_kernel(CPUMIPSState *env) 336 { 337 long kernel_size; 338 ram_addr_t initrd_offset; 339 uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; 340 341 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 342 cpu_mips_kseg0_to_phys, NULL, 343 (uint64_t *)&kernel_entry, 344 (uint64_t *)&kernel_low, (uint64_t *)&kernel_high, 345 NULL, 0, EM_MIPS, 1, 0); 346 if (kernel_size < 0) { 347 error_report("could not load kernel '%s': %s", 348 loaderparams.kernel_filename, 349 load_elf_strerror(kernel_size)); 350 exit(1); 351 } 352 353 /* load initrd */ 354 initrd_size = 0; 355 initrd_offset = 0; 356 if (loaderparams.initrd_filename) { 357 initrd_size = get_image_size(loaderparams.initrd_filename); 358 if (initrd_size > 0) { 359 initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, 360 ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); 361 362 if (initrd_offset + initrd_size > loaderparams.ram_size) { 363 error_report("memory too small for initial ram disk '%s'", 364 loaderparams.initrd_filename); 365 exit(1); 366 } 367 368 initrd_size = load_image_targphys(loaderparams.initrd_filename, 369 initrd_offset, 370 loaderparams.ram_size - initrd_offset); 371 } 372 373 if (initrd_size == (target_ulong) -1) { 374 error_report("could not load initial ram disk '%s'", 375 loaderparams.initrd_filename); 376 exit(1); 377 } 378 } 379 380 /* Setup prom cmdline. */ 381 set_prom_cmdline(initrd_offset, initrd_size); 382 383 return kernel_entry; 384 } 385 386 static void main_cpu_reset(void *opaque) 387 { 388 MIPSCPU *cpu = opaque; 389 CPUMIPSState *env = &cpu->env; 390 391 cpu_reset(CPU(cpu)); 392 393 /* Loongson-3 reset stuff */ 394 if (loaderparams.kernel_filename) { 395 if (cpu == MIPS_CPU(first_cpu)) { 396 env->active_tc.gpr[4] = loaderparams.a0; 397 env->active_tc.gpr[5] = loaderparams.a1; 398 env->active_tc.gpr[6] = loaderparams.a2; 399 env->active_tc.PC = loaderparams.kernel_entry; 400 } 401 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 402 } 403 } 404 405 static inline void loongson3_virt_devices_init(MachineState *machine, 406 DeviceState *pic) 407 { 408 int i; 409 qemu_irq irq; 410 PCIBus *pci_bus; 411 DeviceState *dev; 412 MemoryRegion *mmio_reg, *ecam_reg; 413 LoongsonMachineState *s = LOONGSON_MACHINE(machine); 414 415 dev = qdev_new(TYPE_GPEX_HOST); 416 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 417 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 418 419 s->ecam_alias = g_new0(MemoryRegion, 1); 420 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 421 memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", 422 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); 423 memory_region_add_subregion(get_system_memory(), 424 virt_memmap[VIRT_PCIE_ECAM].base, 425 s->ecam_alias); 426 427 s->mmio_alias = g_new0(MemoryRegion, 1); 428 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 429 memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", 430 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, 431 virt_memmap[VIRT_PCIE_MMIO].size); 432 memory_region_add_subregion(get_system_memory(), 433 virt_memmap[VIRT_PCIE_MMIO].base, 434 s->mmio_alias); 435 436 s->pio_alias = g_new0(MemoryRegion, 1); 437 memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", 438 get_system_io(), 0, 439 virt_memmap[VIRT_PCIE_PIO].size); 440 memory_region_add_subregion(get_system_memory(), 441 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); 442 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); 443 444 for (i = 0; i < GPEX_NUM_IRQS; i++) { 445 irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); 446 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 447 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); 448 } 449 msi_nonbroken = true; 450 451 pci_vga_init(pci_bus); 452 453 if (defaults_enabled()) { 454 pci_create_simple(pci_bus, -1, "pci-ohci"); 455 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 456 usb_create_simple(usb_bus_find(-1), "usb-tablet"); 457 } 458 459 for (i = 0; i < nb_nics; i++) { 460 NICInfo *nd = &nd_table[i]; 461 462 if (!nd->model) { 463 nd->model = g_strdup("virtio"); 464 } 465 466 pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); 467 } 468 } 469 470 static void mips_loongson3_virt_init(MachineState *machine) 471 { 472 int i; 473 long bios_size; 474 MIPSCPU *cpu; 475 Clock *cpuclk; 476 CPUMIPSState *env; 477 DeviceState *liointc; 478 char *filename; 479 const char *kernel_cmdline = machine->kernel_cmdline; 480 const char *kernel_filename = machine->kernel_filename; 481 const char *initrd_filename = machine->initrd_filename; 482 ram_addr_t ram_size = machine->ram_size; 483 MemoryRegion *address_space_mem = get_system_memory(); 484 MemoryRegion *ram = g_new(MemoryRegion, 1); 485 MemoryRegion *bios = g_new(MemoryRegion, 1); 486 MemoryRegion *iomem = g_new(MemoryRegion, 1); 487 488 /* TODO: TCG will support all CPU types */ 489 if (!kvm_enabled()) { 490 if (!machine->cpu_type) { 491 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); 492 } 493 if (!strstr(machine->cpu_type, "Loongson-3A1000")) { 494 error_report("Loongson-3/TCG needs cpu type Loongson-3A1000"); 495 exit(1); 496 } 497 } else { 498 if (!machine->cpu_type) { 499 machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); 500 } 501 if (!strstr(machine->cpu_type, "Loongson-3A4000")) { 502 error_report("Loongson-3/KVM needs cpu type Loongson-3A4000"); 503 exit(1); 504 } 505 } 506 507 if (ram_size < 512 * MiB) { 508 error_report("Loongson-3 machine needs at least 512MB memory"); 509 exit(1); 510 } 511 512 /* 513 * The whole MMIO range among configure registers doesn't generate 514 * exception when accessing invalid memory. Create some unimplememted 515 * devices to emulate this feature. 516 */ 517 create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); 518 create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); 519 520 liointc = qdev_new("loongson.liointc"); 521 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); 522 523 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); 524 525 serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, 526 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), 527 DEVICE_NATIVE_ENDIAN); 528 529 sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, 530 qdev_get_gpio_in(liointc, RTC_IRQ)); 531 532 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 533 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); 534 535 for (i = 0; i < machine->smp.cpus; i++) { 536 int ip; 537 538 /* init CPUs */ 539 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 540 541 /* Init internal devices */ 542 cpu_mips_irq_init_cpu(cpu); 543 cpu_mips_clock_init(cpu); 544 qemu_register_reset(main_cpu_reset, cpu); 545 546 if (i >= 4) { 547 continue; /* Only node-0 can be connected to LIOINTC */ 548 } 549 550 for (ip = 0; ip < 4 ; ip++) { 551 int pin = i * 4 + ip; 552 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), 553 pin, cpu->env.irq[ip + 2]); 554 } 555 } 556 env = &MIPS_CPU(first_cpu)->env; 557 558 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ 559 memory_region_init_rom(bios, NULL, "loongson3.bios", 560 virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); 561 memory_region_init_alias(ram, NULL, "loongson3.lowmem", 562 machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); 563 memory_region_init_io(iomem, NULL, &loongson3_pm_ops, 564 NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); 565 566 memory_region_add_subregion(address_space_mem, 567 virt_memmap[VIRT_LOWMEM].base, ram); 568 memory_region_add_subregion(address_space_mem, 569 virt_memmap[VIRT_BIOS_ROM].base, bios); 570 memory_region_add_subregion(address_space_mem, 571 virt_memmap[VIRT_HIGHMEM].base, machine->ram); 572 memory_region_add_subregion(address_space_mem, 573 virt_memmap[VIRT_PM].base, iomem); 574 575 /* 576 * We do not support flash operation, just loading bios.bin as raw BIOS. 577 * Please use -L to set the BIOS path and -bios to set bios name. 578 */ 579 580 if (kernel_filename) { 581 loaderparams.cpu_freq = get_cpu_freq_hz(); 582 loaderparams.ram_size = ram_size; 583 loaderparams.kernel_filename = kernel_filename; 584 loaderparams.kernel_cmdline = kernel_cmdline; 585 loaderparams.initrd_filename = initrd_filename; 586 loaderparams.kernel_entry = load_kernel(env); 587 588 init_boot_rom(); 589 init_boot_param(); 590 } else { 591 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 592 machine->firmware ?: LOONGSON3_BIOSNAME); 593 if (filename) { 594 bios_size = load_image_targphys(filename, 595 virt_memmap[VIRT_BIOS_ROM].base, 596 virt_memmap[VIRT_BIOS_ROM].size); 597 g_free(filename); 598 } else { 599 bios_size = -1; 600 } 601 602 if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && 603 !kernel_filename && !qtest_enabled()) { 604 error_report("Could not load MIPS bios '%s'", machine->firmware); 605 exit(1); 606 } 607 608 fw_conf_init(ram_size); 609 } 610 611 loongson3_virt_devices_init(machine, liointc); 612 } 613 614 static void loongson3v_machine_class_init(ObjectClass *oc, void *data) 615 { 616 MachineClass *mc = MACHINE_CLASS(oc); 617 618 mc->desc = "Loongson-3 Virtualization Platform"; 619 mc->init = mips_loongson3_virt_init; 620 mc->block_default_type = IF_IDE; 621 mc->max_cpus = LOONGSON_MAX_VCPUS; 622 mc->default_ram_id = "loongson3.highram"; 623 mc->default_ram_size = 1600 * MiB; 624 mc->kvm_type = mips_kvm_type; 625 mc->minimum_page_bits = 14; 626 } 627 628 static const TypeInfo loongson3_machine_types[] = { 629 { 630 .name = TYPE_LOONGSON_MACHINE, 631 .parent = TYPE_MACHINE, 632 .instance_size = sizeof(LoongsonMachineState), 633 .class_init = loongson3v_machine_class_init, 634 } 635 }; 636 637 DEFINE_TYPES(loongson3_machine_types) 638