1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "hw/clock.h" 29 #include "hw/mips/mips.h" 30 #include "hw/mips/cpudevs.h" 31 #include "hw/intc/i8259.h" 32 #include "hw/dma/i8257.h" 33 #include "hw/char/serial.h" 34 #include "hw/char/parallel.h" 35 #include "hw/isa/isa.h" 36 #include "hw/block/fdc.h" 37 #include "sysemu/sysemu.h" 38 #include "sysemu/arch_init.h" 39 #include "hw/boards.h" 40 #include "net/net.h" 41 #include "hw/scsi/esp.h" 42 #include "hw/mips/bios.h" 43 #include "hw/loader.h" 44 #include "hw/rtc/mc146818rtc.h" 45 #include "hw/timer/i8254.h" 46 #include "hw/display/vga.h" 47 #include "hw/audio/pcspk.h" 48 #include "hw/input/i8042.h" 49 #include "hw/sysbus.h" 50 #include "sysemu/qtest.h" 51 #include "sysemu/reset.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "qemu/help_option.h" 55 #ifdef CONFIG_TCG 56 #include "hw/core/tcg-cpu-ops.h" 57 #endif /* CONFIG_TCG */ 58 59 enum jazz_model_e { 60 JAZZ_MAGNUM, 61 JAZZ_PICA61, 62 }; 63 64 static void main_cpu_reset(void *opaque) 65 { 66 MIPSCPU *cpu = opaque; 67 68 cpu_reset(CPU(cpu)); 69 } 70 71 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 72 { 73 uint8_t val; 74 address_space_read(&address_space_memory, 0x90000071, 75 MEMTXATTRS_UNSPECIFIED, &val, 1); 76 return val; 77 } 78 79 static void rtc_write(void *opaque, hwaddr addr, 80 uint64_t val, unsigned size) 81 { 82 uint8_t buf = val & 0xff; 83 address_space_write(&address_space_memory, 0x90000071, 84 MEMTXATTRS_UNSPECIFIED, &buf, 1); 85 } 86 87 static const MemoryRegionOps rtc_ops = { 88 .read = rtc_read, 89 .write = rtc_write, 90 .endianness = DEVICE_NATIVE_ENDIAN, 91 }; 92 93 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 94 unsigned size) 95 { 96 /* 97 * Nothing to do. That is only to ensure that 98 * the current DMA acknowledge cycle is completed. 99 */ 100 return 0xff; 101 } 102 103 static void dma_dummy_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 /* 107 * Nothing to do. That is only to ensure that 108 * the current DMA acknowledge cycle is completed. 109 */ 110 } 111 112 static const MemoryRegionOps dma_dummy_ops = { 113 .read = dma_dummy_read, 114 .write = dma_dummy_write, 115 .endianness = DEVICE_NATIVE_ENDIAN, 116 }; 117 118 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 119 #define MAGNUM_BIOS_SIZE \ 120 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 121 122 #define SONIC_PROM_SIZE 0x1000 123 124 static void mips_jazz_init(MachineState *machine, 125 enum jazz_model_e jazz_model) 126 { 127 MemoryRegion *address_space = get_system_memory(); 128 char *filename; 129 int bios_size, n, big_endian; 130 Clock *cpuclk; 131 MIPSCPU *cpu; 132 MIPSCPUClass *mcc; 133 CPUMIPSState *env; 134 qemu_irq *i8259; 135 rc4030_dma *dmas; 136 IOMMUMemoryRegion *rc4030_dma_mr; 137 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 138 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 139 MemoryRegion *rtc = g_new(MemoryRegion, 1); 140 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 141 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 142 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); 143 NICInfo *nd; 144 DeviceState *dev, *rc4030; 145 SysBusDevice *sysbus; 146 ISABus *isa_bus; 147 ISADevice *pit; 148 DriveInfo *fds[MAX_FD]; 149 MemoryRegion *bios = g_new(MemoryRegion, 1); 150 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 151 SysBusESPState *sysbus_esp; 152 ESPState *esp; 153 static const struct { 154 unsigned freq_hz; 155 unsigned pll_mult; 156 } ext_clk[] = { 157 [JAZZ_MAGNUM] = {50000000, 2}, 158 [JAZZ_PICA61] = {33333333, 4}, 159 }; 160 161 #ifdef TARGET_WORDS_BIGENDIAN 162 big_endian = 1; 163 #else 164 big_endian = 0; 165 #endif 166 167 if (machine->ram_size > 256 * MiB) { 168 error_report("RAM size more than 256Mb is not supported"); 169 exit(EXIT_FAILURE); 170 } 171 172 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 173 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz 174 * ext_clk[jazz_model].pll_mult); 175 176 /* init CPUs */ 177 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 178 env = &cpu->env; 179 qemu_register_reset(main_cpu_reset, cpu); 180 181 /* 182 * Chipset returns 0 in invalid reads and do not raise data exceptions. 183 * However, we can't simply add a global memory region to catch 184 * everything, as this would make all accesses including instruction 185 * accesses be ignored and not raise exceptions. 186 * 187 * NOTE: this behaviour of raising exceptions for bad instruction 188 * fetches but not bad data accesses was added in commit 54e755588cf1e9 189 * to restore behaviour broken by c658b94f6e8c206, but it is not clear 190 * whether the real hardware behaves this way. It is possible that 191 * real hardware ignores bad instruction fetches as well -- if so then 192 * we could replace this hijacking of CPU methods with a simple global 193 * memory region that catches all memory accesses, as we do on Malta. 194 */ 195 mcc = MIPS_CPU_GET_CLASS(cpu); 196 mcc->no_data_aborts = true; 197 198 /* allocate RAM */ 199 memory_region_add_subregion(address_space, 0, machine->ram); 200 201 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 202 &error_fatal); 203 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 204 0, MAGNUM_BIOS_SIZE); 205 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 206 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 207 208 /* load the BIOS image. */ 209 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); 210 if (filename) { 211 bios_size = load_image_targphys(filename, 0xfff00000LL, 212 MAGNUM_BIOS_SIZE); 213 g_free(filename); 214 } else { 215 bios_size = -1; 216 } 217 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) 218 && machine->firmware && !qtest_enabled()) { 219 error_report("Could not load MIPS bios '%s'", machine->firmware); 220 exit(1); 221 } 222 223 /* Init CPU internal devices */ 224 cpu_mips_irq_init_cpu(cpu); 225 cpu_mips_clock_init(cpu); 226 227 /* Chipset */ 228 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 229 sysbus = SYS_BUS_DEVICE(rc4030); 230 sysbus_connect_irq(sysbus, 0, env->irq[6]); 231 sysbus_connect_irq(sysbus, 1, env->irq[3]); 232 memory_region_add_subregion(address_space, 0x80000000, 233 sysbus_mmio_get_region(sysbus, 0)); 234 memory_region_add_subregion(address_space, 0xf0000000, 235 sysbus_mmio_get_region(sysbus, 1)); 236 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, 237 NULL, "dummy_dma", 0x1000); 238 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 239 240 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom", 241 SONIC_PROM_SIZE, &error_fatal); 242 memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom); 243 244 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 245 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 246 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 247 memory_region_add_subregion(address_space, 0x90000000, isa_io); 248 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 249 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 250 251 /* ISA devices */ 252 i8259 = i8259_init(isa_bus, env->irq[4]); 253 isa_bus_irqs(isa_bus, i8259); 254 i8257_dma_init(isa_bus, 0); 255 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 256 pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit); 257 258 /* Video card */ 259 switch (jazz_model) { 260 case JAZZ_MAGNUM: 261 dev = qdev_new("sysbus-g364"); 262 sysbus = SYS_BUS_DEVICE(dev); 263 sysbus_realize_and_unref(sysbus, &error_fatal); 264 sysbus_mmio_map(sysbus, 0, 0x60080000); 265 sysbus_mmio_map(sysbus, 1, 0x40000000); 266 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 267 { 268 /* Simple ROM, so user doesn't have to provide one */ 269 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 270 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, 271 &error_fatal); 272 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 273 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 274 rom[0] = 0x10; /* Mips G364 */ 275 } 276 break; 277 case JAZZ_PICA61: 278 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 279 break; 280 default: 281 break; 282 } 283 284 /* Network controller */ 285 for (n = 0; n < nb_nics; n++) { 286 nd = &nd_table[n]; 287 if (!nd->model) { 288 nd->model = g_strdup("dp83932"); 289 } 290 if (strcmp(nd->model, "dp83932") == 0) { 291 int checksum, i; 292 uint8_t *prom; 293 294 qemu_check_nic_model(nd, "dp83932"); 295 296 dev = qdev_new("dp8393x"); 297 qdev_set_nic_properties(dev, nd); 298 qdev_prop_set_uint8(dev, "it_shift", 2); 299 qdev_prop_set_bit(dev, "big_endian", big_endian > 0); 300 object_property_set_link(OBJECT(dev), "dma_mr", 301 OBJECT(rc4030_dma_mr), &error_abort); 302 sysbus = SYS_BUS_DEVICE(dev); 303 sysbus_realize_and_unref(sysbus, &error_fatal); 304 sysbus_mmio_map(sysbus, 0, 0x80001000); 305 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 306 307 /* Add MAC address with valid checksum to PROM */ 308 prom = memory_region_get_ram_ptr(dp8393x_prom); 309 checksum = 0; 310 for (i = 0; i < 6; i++) { 311 prom[i] = nd->macaddr.a[i]; 312 checksum += prom[i]; 313 if (checksum > 0xff) { 314 checksum = (checksum + 1) & 0xff; 315 } 316 } 317 prom[7] = 0xff - checksum; 318 break; 319 } else if (is_help_option(nd->model)) { 320 error_report("Supported NICs: dp83932"); 321 exit(1); 322 } else { 323 error_report("Unsupported NIC: %s", nd->model); 324 exit(1); 325 } 326 } 327 328 /* SCSI adapter */ 329 dev = qdev_new(TYPE_SYSBUS_ESP); 330 sysbus_esp = SYSBUS_ESP(dev); 331 esp = &sysbus_esp->esp; 332 esp->dma_memory_read = rc4030_dma_read; 333 esp->dma_memory_write = rc4030_dma_write; 334 esp->dma_opaque = dmas[0]; 335 sysbus_esp->it_shift = 0; 336 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 337 esp->dma_enabled = 1; 338 339 sysbus = SYS_BUS_DEVICE(dev); 340 sysbus_realize_and_unref(sysbus, &error_fatal); 341 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 342 sysbus_mmio_map(sysbus, 0, 0x80002000); 343 344 scsi_bus_legacy_handle_cmdline(&esp->bus); 345 346 /* Floppy */ 347 for (n = 0; n < MAX_FD; n++) { 348 fds[n] = drive_get(IF_FLOPPY, 0, n); 349 } 350 /* FIXME: we should enable DMA with a custom IsaDma device */ 351 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); 352 353 /* Real time clock */ 354 mc146818_rtc_init(isa_bus, 1980, NULL); 355 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 356 memory_region_add_subregion(address_space, 0x80004000, rtc); 357 358 /* Keyboard (i8042) */ 359 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 360 i8042, 0x1000, 0x1); 361 memory_region_add_subregion(address_space, 0x80005000, i8042); 362 363 /* Serial ports */ 364 serial_mm_init(address_space, 0x80006000, 0, 365 qdev_get_gpio_in(rc4030, 8), 8000000 / 16, 366 serial_hd(0), DEVICE_NATIVE_ENDIAN); 367 serial_mm_init(address_space, 0x80007000, 0, 368 qdev_get_gpio_in(rc4030, 9), 8000000 / 16, 369 serial_hd(1), DEVICE_NATIVE_ENDIAN); 370 371 /* Parallel port */ 372 if (parallel_hds[0]) 373 parallel_mm_init(address_space, 0x80008000, 0, 374 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 375 376 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 377 378 /* NVRAM */ 379 dev = qdev_new("ds1225y"); 380 sysbus = SYS_BUS_DEVICE(dev); 381 sysbus_realize_and_unref(sysbus, &error_fatal); 382 sysbus_mmio_map(sysbus, 0, 0x80009000); 383 384 /* LED indicator */ 385 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 386 387 g_free(dmas); 388 } 389 390 static 391 void mips_magnum_init(MachineState *machine) 392 { 393 mips_jazz_init(machine, JAZZ_MAGNUM); 394 } 395 396 static 397 void mips_pica61_init(MachineState *machine) 398 { 399 mips_jazz_init(machine, JAZZ_PICA61); 400 } 401 402 static void mips_magnum_class_init(ObjectClass *oc, void *data) 403 { 404 MachineClass *mc = MACHINE_CLASS(oc); 405 406 mc->desc = "MIPS Magnum"; 407 mc->init = mips_magnum_init; 408 mc->block_default_type = IF_SCSI; 409 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 410 mc->default_ram_id = "mips_jazz.ram"; 411 } 412 413 static const TypeInfo mips_magnum_type = { 414 .name = MACHINE_TYPE_NAME("magnum"), 415 .parent = TYPE_MACHINE, 416 .class_init = mips_magnum_class_init, 417 }; 418 419 static void mips_pica61_class_init(ObjectClass *oc, void *data) 420 { 421 MachineClass *mc = MACHINE_CLASS(oc); 422 423 mc->desc = "Acer Pica 61"; 424 mc->init = mips_pica61_init; 425 mc->block_default_type = IF_SCSI; 426 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 427 mc->default_ram_id = "mips_jazz.ram"; 428 } 429 430 static const TypeInfo mips_pica61_type = { 431 .name = MACHINE_TYPE_NAME("pica61"), 432 .parent = TYPE_MACHINE, 433 .class_init = mips_pica61_class_init, 434 }; 435 436 static void mips_jazz_machine_init(void) 437 { 438 type_register_static(&mips_magnum_type); 439 type_register_static(&mips_pica61_type); 440 } 441 442 type_init(mips_jazz_machine_init) 443