1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "hw/clock.h" 28 #include "hw/mips/mips.h" 29 #include "hw/intc/i8259.h" 30 #include "hw/dma/i8257.h" 31 #include "hw/char/serial.h" 32 #include "hw/char/parallel.h" 33 #include "hw/isa/isa.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "hw/boards.h" 37 #include "net/net.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/loader.h" 40 #include "hw/rtc/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/display/vga.h" 43 #include "hw/display/bochs-vbe.h" 44 #include "hw/audio/pcspk.h" 45 #include "hw/input/i8042.h" 46 #include "hw/sysbus.h" 47 #include "sysemu/qtest.h" 48 #include "sysemu/reset.h" 49 #include "qapi/error.h" 50 #include "qemu/error-report.h" 51 #include "qemu/help_option.h" 52 #ifdef CONFIG_TCG 53 #include "hw/core/tcg-cpu-ops.h" 54 #endif /* CONFIG_TCG */ 55 #include "cpu.h" 56 57 enum jazz_model_e { 58 JAZZ_MAGNUM, 59 JAZZ_PICA61, 60 }; 61 62 #if TARGET_BIG_ENDIAN 63 #define BIOS_FILENAME "mips_bios.bin" 64 #else 65 #define BIOS_FILENAME "mipsel_bios.bin" 66 #endif 67 68 static void main_cpu_reset(void *opaque) 69 { 70 MIPSCPU *cpu = opaque; 71 72 cpu_reset(CPU(cpu)); 73 } 74 75 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 76 { 77 uint8_t val; 78 address_space_read(&address_space_memory, 0x90000071, 79 MEMTXATTRS_UNSPECIFIED, &val, 1); 80 return val; 81 } 82 83 static void rtc_write(void *opaque, hwaddr addr, 84 uint64_t val, unsigned size) 85 { 86 uint8_t buf = val & 0xff; 87 address_space_write(&address_space_memory, 0x90000071, 88 MEMTXATTRS_UNSPECIFIED, &buf, 1); 89 } 90 91 static const MemoryRegionOps rtc_ops = { 92 .read = rtc_read, 93 .write = rtc_write, 94 .endianness = DEVICE_NATIVE_ENDIAN, 95 }; 96 97 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 98 unsigned size) 99 { 100 /* 101 * Nothing to do. That is only to ensure that 102 * the current DMA acknowledge cycle is completed. 103 */ 104 return 0xff; 105 } 106 107 static void dma_dummy_write(void *opaque, hwaddr addr, 108 uint64_t val, unsigned size) 109 { 110 /* 111 * Nothing to do. That is only to ensure that 112 * the current DMA acknowledge cycle is completed. 113 */ 114 } 115 116 static const MemoryRegionOps dma_dummy_ops = { 117 .read = dma_dummy_read, 118 .write = dma_dummy_write, 119 .endianness = DEVICE_NATIVE_ENDIAN, 120 }; 121 122 static void mips_jazz_init_net(NICInfo *nd, IOMMUMemoryRegion *rc4030_dma_mr, 123 DeviceState *rc4030, MemoryRegion *dp8393x_prom) 124 { 125 DeviceState *dev; 126 SysBusDevice *sysbus; 127 int checksum, i; 128 uint8_t *prom; 129 130 qemu_check_nic_model(nd, "dp83932"); 131 132 dev = qdev_new("dp8393x"); 133 qdev_set_nic_properties(dev, nd); 134 qdev_prop_set_uint8(dev, "it_shift", 2); 135 qdev_prop_set_bit(dev, "big_endian", TARGET_BIG_ENDIAN); 136 object_property_set_link(OBJECT(dev), "dma_mr", 137 OBJECT(rc4030_dma_mr), &error_abort); 138 sysbus = SYS_BUS_DEVICE(dev); 139 sysbus_realize_and_unref(sysbus, &error_fatal); 140 sysbus_mmio_map(sysbus, 0, 0x80001000); 141 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 142 143 /* Add MAC address with valid checksum to PROM */ 144 prom = memory_region_get_ram_ptr(dp8393x_prom); 145 checksum = 0; 146 for (i = 0; i < 6; i++) { 147 prom[i] = nd->macaddr.a[i]; 148 checksum += prom[i]; 149 if (checksum > 0xff) { 150 checksum = (checksum + 1) & 0xff; 151 } 152 } 153 prom[7] = 0xff - checksum; 154 } 155 156 #define BIOS_SIZE (4 * MiB) 157 158 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 159 #define MAGNUM_BIOS_SIZE \ 160 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 161 162 #define SONIC_PROM_SIZE 0x1000 163 164 static void mips_jazz_init(MachineState *machine, 165 enum jazz_model_e jazz_model) 166 { 167 MemoryRegion *address_space = get_system_memory(); 168 char *filename; 169 int bios_size, n; 170 Clock *cpuclk; 171 MIPSCPU *cpu; 172 MIPSCPUClass *mcc; 173 CPUMIPSState *env; 174 qemu_irq *i8259; 175 rc4030_dma *dmas; 176 IOMMUMemoryRegion *rc4030_dma_mr; 177 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 178 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 179 MemoryRegion *rtc = g_new(MemoryRegion, 1); 180 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 181 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); 182 DeviceState *dev, *rc4030; 183 MMIOKBDState *i8042; 184 SysBusDevice *sysbus; 185 ISABus *isa_bus; 186 ISADevice *pit; 187 ISADevice *pcspk; 188 DriveInfo *fds[MAX_FD]; 189 MemoryRegion *bios = g_new(MemoryRegion, 1); 190 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 191 SysBusESPState *sysbus_esp; 192 ESPState *esp; 193 static const struct { 194 unsigned freq_hz; 195 unsigned pll_mult; 196 } ext_clk[] = { 197 [JAZZ_MAGNUM] = {50000000, 2}, 198 [JAZZ_PICA61] = {33333333, 4}, 199 }; 200 201 if (machine->ram_size > 256 * MiB) { 202 error_report("RAM size more than 256Mb is not supported"); 203 exit(EXIT_FAILURE); 204 } 205 206 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 207 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz 208 * ext_clk[jazz_model].pll_mult); 209 210 /* init CPUs */ 211 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 212 env = &cpu->env; 213 qemu_register_reset(main_cpu_reset, cpu); 214 215 /* 216 * Chipset returns 0 in invalid reads and do not raise data exceptions. 217 * However, we can't simply add a global memory region to catch 218 * everything, as this would make all accesses including instruction 219 * accesses be ignored and not raise exceptions. 220 * 221 * NOTE: this behaviour of raising exceptions for bad instruction 222 * fetches but not bad data accesses was added in commit 54e755588cf1e9 223 * to restore behaviour broken by c658b94f6e8c206, but it is not clear 224 * whether the real hardware behaves this way. It is possible that 225 * real hardware ignores bad instruction fetches as well -- if so then 226 * we could replace this hijacking of CPU methods with a simple global 227 * memory region that catches all memory accesses, as we do on Malta. 228 */ 229 mcc = MIPS_CPU_GET_CLASS(cpu); 230 mcc->no_data_aborts = true; 231 232 /* allocate RAM */ 233 memory_region_add_subregion(address_space, 0, machine->ram); 234 235 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 236 &error_fatal); 237 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 238 0, MAGNUM_BIOS_SIZE); 239 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 240 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 241 242 /* load the BIOS image. */ 243 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); 244 if (filename) { 245 bios_size = load_image_targphys(filename, 0xfff00000LL, 246 MAGNUM_BIOS_SIZE); 247 g_free(filename); 248 } else { 249 bios_size = -1; 250 } 251 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) 252 && machine->firmware && !qtest_enabled()) { 253 error_report("Could not load MIPS bios '%s'", machine->firmware); 254 exit(1); 255 } 256 257 /* Init CPU internal devices */ 258 cpu_mips_irq_init_cpu(cpu); 259 cpu_mips_clock_init(cpu); 260 261 /* Chipset */ 262 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 263 sysbus = SYS_BUS_DEVICE(rc4030); 264 sysbus_connect_irq(sysbus, 0, env->irq[6]); 265 sysbus_connect_irq(sysbus, 1, env->irq[3]); 266 memory_region_add_subregion(address_space, 0x80000000, 267 sysbus_mmio_get_region(sysbus, 0)); 268 memory_region_add_subregion(address_space, 0xf0000000, 269 sysbus_mmio_get_region(sysbus, 1)); 270 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, 271 NULL, "dummy_dma", 0x1000); 272 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 273 274 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom", 275 SONIC_PROM_SIZE, &error_fatal); 276 memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom); 277 278 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 279 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 280 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 281 memory_region_add_subregion(address_space, 0x90000000, isa_io); 282 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 283 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 284 285 /* ISA devices */ 286 i8259 = i8259_init(isa_bus, env->irq[4]); 287 isa_bus_register_input_irqs(isa_bus, i8259); 288 i8257_dma_init(isa_bus, 0); 289 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 290 pcspk = isa_new(TYPE_PC_SPEAKER); 291 object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal); 292 isa_realize_and_unref(pcspk, isa_bus, &error_fatal); 293 294 /* Video card */ 295 switch (jazz_model) { 296 case JAZZ_MAGNUM: 297 dev = qdev_new("sysbus-g364"); 298 sysbus = SYS_BUS_DEVICE(dev); 299 sysbus_realize_and_unref(sysbus, &error_fatal); 300 sysbus_mmio_map(sysbus, 0, 0x60080000); 301 sysbus_mmio_map(sysbus, 1, 0x40000000); 302 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 303 { 304 /* Simple ROM, so user doesn't have to provide one */ 305 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 306 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, 307 &error_fatal); 308 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 309 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 310 rom[0] = 0x10; /* Mips G364 */ 311 } 312 break; 313 case JAZZ_PICA61: 314 dev = qdev_new(TYPE_VGA_MMIO); 315 qdev_prop_set_uint8(dev, "it_shift", 0); 316 sysbus = SYS_BUS_DEVICE(dev); 317 sysbus_realize_and_unref(sysbus, &error_fatal); 318 sysbus_mmio_map(sysbus, 0, 0x60000000); 319 sysbus_mmio_map(sysbus, 1, 0x400a0000); 320 sysbus_mmio_map(sysbus, 2, VBE_DISPI_LFB_PHYSICAL_ADDRESS); 321 break; 322 default: 323 break; 324 } 325 326 /* Network controller */ 327 if (nb_nics == 1) { 328 mips_jazz_init_net(&nd_table[0], rc4030_dma_mr, rc4030, dp8393x_prom); 329 } else if (nb_nics > 1) { 330 error_report("This machine only supports one NIC"); 331 exit(1); 332 } 333 334 /* SCSI adapter */ 335 dev = qdev_new(TYPE_SYSBUS_ESP); 336 sysbus_esp = SYSBUS_ESP(dev); 337 esp = &sysbus_esp->esp; 338 esp->dma_memory_read = rc4030_dma_read; 339 esp->dma_memory_write = rc4030_dma_write; 340 esp->dma_opaque = dmas[0]; 341 sysbus_esp->it_shift = 0; 342 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 343 esp->dma_enabled = 1; 344 345 sysbus = SYS_BUS_DEVICE(dev); 346 sysbus_realize_and_unref(sysbus, &error_fatal); 347 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 348 sysbus_mmio_map(sysbus, 0, 0x80002000); 349 350 scsi_bus_legacy_handle_cmdline(&esp->bus); 351 352 /* Floppy */ 353 for (n = 0; n < MAX_FD; n++) { 354 fds[n] = drive_get(IF_FLOPPY, 0, n); 355 } 356 /* FIXME: we should enable DMA with a custom IsaDma device */ 357 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0x80003000, fds); 358 359 /* Real time clock */ 360 mc146818_rtc_init(isa_bus, 1980, NULL); 361 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 362 memory_region_add_subregion(address_space, 0x80004000, rtc); 363 364 /* Keyboard (i8042) */ 365 i8042 = I8042_MMIO(qdev_new(TYPE_I8042_MMIO)); 366 qdev_prop_set_uint64(DEVICE(i8042), "mask", 1); 367 qdev_prop_set_uint32(DEVICE(i8042), "size", 0x1000); 368 sysbus_realize_and_unref(SYS_BUS_DEVICE(i8042), &error_fatal); 369 370 qdev_connect_gpio_out(DEVICE(i8042), I8042_KBD_IRQ, 371 qdev_get_gpio_in(rc4030, 6)); 372 qdev_connect_gpio_out(DEVICE(i8042), I8042_MOUSE_IRQ, 373 qdev_get_gpio_in(rc4030, 7)); 374 375 memory_region_add_subregion(address_space, 0x80005000, 376 sysbus_mmio_get_region(SYS_BUS_DEVICE(i8042), 377 0)); 378 379 /* Serial ports */ 380 serial_mm_init(address_space, 0x80006000, 0, 381 qdev_get_gpio_in(rc4030, 8), 8000000 / 16, 382 serial_hd(0), DEVICE_NATIVE_ENDIAN); 383 serial_mm_init(address_space, 0x80007000, 0, 384 qdev_get_gpio_in(rc4030, 9), 8000000 / 16, 385 serial_hd(1), DEVICE_NATIVE_ENDIAN); 386 387 /* Parallel port */ 388 if (parallel_hds[0]) 389 parallel_mm_init(address_space, 0x80008000, 0, 390 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 391 392 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 393 394 /* NVRAM */ 395 dev = qdev_new("ds1225y"); 396 sysbus = SYS_BUS_DEVICE(dev); 397 sysbus_realize_and_unref(sysbus, &error_fatal); 398 sysbus_mmio_map(sysbus, 0, 0x80009000); 399 400 /* LED indicator */ 401 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 402 403 g_free(dmas); 404 } 405 406 static 407 void mips_magnum_init(MachineState *machine) 408 { 409 mips_jazz_init(machine, JAZZ_MAGNUM); 410 } 411 412 static 413 void mips_pica61_init(MachineState *machine) 414 { 415 mips_jazz_init(machine, JAZZ_PICA61); 416 } 417 418 static void mips_magnum_class_init(ObjectClass *oc, void *data) 419 { 420 MachineClass *mc = MACHINE_CLASS(oc); 421 422 mc->desc = "MIPS Magnum"; 423 mc->init = mips_magnum_init; 424 mc->block_default_type = IF_SCSI; 425 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 426 mc->default_ram_id = "mips_jazz.ram"; 427 } 428 429 static const TypeInfo mips_magnum_type = { 430 .name = MACHINE_TYPE_NAME("magnum"), 431 .parent = TYPE_MACHINE, 432 .class_init = mips_magnum_class_init, 433 }; 434 435 static void mips_pica61_class_init(ObjectClass *oc, void *data) 436 { 437 MachineClass *mc = MACHINE_CLASS(oc); 438 439 mc->desc = "Acer Pica 61"; 440 mc->init = mips_pica61_init; 441 mc->block_default_type = IF_SCSI; 442 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 443 mc->default_ram_id = "mips_jazz.ram"; 444 } 445 446 static const TypeInfo mips_pica61_type = { 447 .name = MACHINE_TYPE_NAME("pica61"), 448 .parent = TYPE_MACHINE, 449 .class_init = mips_pica61_class_init, 450 }; 451 452 static void mips_jazz_machine_init(void) 453 { 454 type_register_static(&mips_magnum_type); 455 type_register_static(&mips_pica61_type); 456 } 457 458 type_init(mips_jazz_machine_init) 459