1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "hw/clock.h" 28 #include "hw/mips/mips.h" 29 #include "hw/mips/cpudevs.h" 30 #include "hw/intc/i8259.h" 31 #include "hw/dma/i8257.h" 32 #include "hw/char/serial.h" 33 #include "hw/char/parallel.h" 34 #include "hw/isa/isa.h" 35 #include "hw/block/fdc.h" 36 #include "sysemu/sysemu.h" 37 #include "hw/boards.h" 38 #include "net/net.h" 39 #include "hw/scsi/esp.h" 40 #include "hw/mips/bios.h" 41 #include "hw/loader.h" 42 #include "hw/rtc/mc146818rtc.h" 43 #include "hw/timer/i8254.h" 44 #include "hw/display/vga.h" 45 #include "hw/display/bochs-vbe.h" 46 #include "hw/audio/pcspk.h" 47 #include "hw/input/i8042.h" 48 #include "hw/sysbus.h" 49 #include "sysemu/qtest.h" 50 #include "sysemu/reset.h" 51 #include "qapi/error.h" 52 #include "qemu/error-report.h" 53 #include "qemu/help_option.h" 54 #ifdef CONFIG_TCG 55 #include "hw/core/tcg-cpu-ops.h" 56 #endif /* CONFIG_TCG */ 57 58 enum jazz_model_e { 59 JAZZ_MAGNUM, 60 JAZZ_PICA61, 61 }; 62 63 static void main_cpu_reset(void *opaque) 64 { 65 MIPSCPU *cpu = opaque; 66 67 cpu_reset(CPU(cpu)); 68 } 69 70 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 71 { 72 uint8_t val; 73 address_space_read(&address_space_memory, 0x90000071, 74 MEMTXATTRS_UNSPECIFIED, &val, 1); 75 return val; 76 } 77 78 static void rtc_write(void *opaque, hwaddr addr, 79 uint64_t val, unsigned size) 80 { 81 uint8_t buf = val & 0xff; 82 address_space_write(&address_space_memory, 0x90000071, 83 MEMTXATTRS_UNSPECIFIED, &buf, 1); 84 } 85 86 static const MemoryRegionOps rtc_ops = { 87 .read = rtc_read, 88 .write = rtc_write, 89 .endianness = DEVICE_NATIVE_ENDIAN, 90 }; 91 92 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 93 unsigned size) 94 { 95 /* 96 * Nothing to do. That is only to ensure that 97 * the current DMA acknowledge cycle is completed. 98 */ 99 return 0xff; 100 } 101 102 static void dma_dummy_write(void *opaque, hwaddr addr, 103 uint64_t val, unsigned size) 104 { 105 /* 106 * Nothing to do. That is only to ensure that 107 * the current DMA acknowledge cycle is completed. 108 */ 109 } 110 111 static const MemoryRegionOps dma_dummy_ops = { 112 .read = dma_dummy_read, 113 .write = dma_dummy_write, 114 .endianness = DEVICE_NATIVE_ENDIAN, 115 }; 116 117 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 118 #define MAGNUM_BIOS_SIZE \ 119 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 120 121 #define SONIC_PROM_SIZE 0x1000 122 123 static void mips_jazz_init(MachineState *machine, 124 enum jazz_model_e jazz_model) 125 { 126 MemoryRegion *address_space = get_system_memory(); 127 char *filename; 128 int bios_size, n; 129 Clock *cpuclk; 130 MIPSCPU *cpu; 131 MIPSCPUClass *mcc; 132 CPUMIPSState *env; 133 qemu_irq *i8259; 134 rc4030_dma *dmas; 135 IOMMUMemoryRegion *rc4030_dma_mr; 136 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 137 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 138 MemoryRegion *rtc = g_new(MemoryRegion, 1); 139 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 140 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); 141 NICInfo *nd; 142 DeviceState *dev, *rc4030; 143 MMIOKBDState *i8042; 144 SysBusDevice *sysbus; 145 ISABus *isa_bus; 146 ISADevice *pit; 147 DriveInfo *fds[MAX_FD]; 148 MemoryRegion *bios = g_new(MemoryRegion, 1); 149 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 150 SysBusESPState *sysbus_esp; 151 ESPState *esp; 152 static const struct { 153 unsigned freq_hz; 154 unsigned pll_mult; 155 } ext_clk[] = { 156 [JAZZ_MAGNUM] = {50000000, 2}, 157 [JAZZ_PICA61] = {33333333, 4}, 158 }; 159 160 if (machine->ram_size > 256 * MiB) { 161 error_report("RAM size more than 256Mb is not supported"); 162 exit(EXIT_FAILURE); 163 } 164 165 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 166 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz 167 * ext_clk[jazz_model].pll_mult); 168 169 /* init CPUs */ 170 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 171 env = &cpu->env; 172 qemu_register_reset(main_cpu_reset, cpu); 173 174 /* 175 * Chipset returns 0 in invalid reads and do not raise data exceptions. 176 * However, we can't simply add a global memory region to catch 177 * everything, as this would make all accesses including instruction 178 * accesses be ignored and not raise exceptions. 179 * 180 * NOTE: this behaviour of raising exceptions for bad instruction 181 * fetches but not bad data accesses was added in commit 54e755588cf1e9 182 * to restore behaviour broken by c658b94f6e8c206, but it is not clear 183 * whether the real hardware behaves this way. It is possible that 184 * real hardware ignores bad instruction fetches as well -- if so then 185 * we could replace this hijacking of CPU methods with a simple global 186 * memory region that catches all memory accesses, as we do on Malta. 187 */ 188 mcc = MIPS_CPU_GET_CLASS(cpu); 189 mcc->no_data_aborts = true; 190 191 /* allocate RAM */ 192 memory_region_add_subregion(address_space, 0, machine->ram); 193 194 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 195 &error_fatal); 196 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 197 0, MAGNUM_BIOS_SIZE); 198 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 199 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 200 201 /* load the BIOS image. */ 202 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); 203 if (filename) { 204 bios_size = load_image_targphys(filename, 0xfff00000LL, 205 MAGNUM_BIOS_SIZE); 206 g_free(filename); 207 } else { 208 bios_size = -1; 209 } 210 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) 211 && machine->firmware && !qtest_enabled()) { 212 error_report("Could not load MIPS bios '%s'", machine->firmware); 213 exit(1); 214 } 215 216 /* Init CPU internal devices */ 217 cpu_mips_irq_init_cpu(cpu); 218 cpu_mips_clock_init(cpu); 219 220 /* Chipset */ 221 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 222 sysbus = SYS_BUS_DEVICE(rc4030); 223 sysbus_connect_irq(sysbus, 0, env->irq[6]); 224 sysbus_connect_irq(sysbus, 1, env->irq[3]); 225 memory_region_add_subregion(address_space, 0x80000000, 226 sysbus_mmio_get_region(sysbus, 0)); 227 memory_region_add_subregion(address_space, 0xf0000000, 228 sysbus_mmio_get_region(sysbus, 1)); 229 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, 230 NULL, "dummy_dma", 0x1000); 231 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 232 233 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom", 234 SONIC_PROM_SIZE, &error_fatal); 235 memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom); 236 237 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 238 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 239 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 240 memory_region_add_subregion(address_space, 0x90000000, isa_io); 241 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 242 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 243 244 /* ISA devices */ 245 i8259 = i8259_init(isa_bus, env->irq[4]); 246 isa_bus_register_input_irqs(isa_bus, i8259); 247 i8257_dma_init(isa_bus, 0); 248 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 249 pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit); 250 251 /* Video card */ 252 switch (jazz_model) { 253 case JAZZ_MAGNUM: 254 dev = qdev_new("sysbus-g364"); 255 sysbus = SYS_BUS_DEVICE(dev); 256 sysbus_realize_and_unref(sysbus, &error_fatal); 257 sysbus_mmio_map(sysbus, 0, 0x60080000); 258 sysbus_mmio_map(sysbus, 1, 0x40000000); 259 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 260 { 261 /* Simple ROM, so user doesn't have to provide one */ 262 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 263 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, 264 &error_fatal); 265 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 266 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 267 rom[0] = 0x10; /* Mips G364 */ 268 } 269 break; 270 case JAZZ_PICA61: 271 dev = qdev_new(TYPE_VGA_MMIO); 272 qdev_prop_set_uint8(dev, "it_shift", 0); 273 sysbus = SYS_BUS_DEVICE(dev); 274 sysbus_realize_and_unref(sysbus, &error_fatal); 275 sysbus_mmio_map(sysbus, 0, 0x60000000); 276 sysbus_mmio_map(sysbus, 1, 0x400a0000); 277 sysbus_mmio_map(sysbus, 2, VBE_DISPI_LFB_PHYSICAL_ADDRESS); 278 break; 279 default: 280 break; 281 } 282 283 /* Network controller */ 284 for (n = 0; n < nb_nics; n++) { 285 nd = &nd_table[n]; 286 if (!nd->model) { 287 nd->model = g_strdup("dp83932"); 288 } 289 if (strcmp(nd->model, "dp83932") == 0) { 290 int checksum, i; 291 uint8_t *prom; 292 293 qemu_check_nic_model(nd, "dp83932"); 294 295 dev = qdev_new("dp8393x"); 296 qdev_set_nic_properties(dev, nd); 297 qdev_prop_set_uint8(dev, "it_shift", 2); 298 qdev_prop_set_bit(dev, "big_endian", TARGET_BIG_ENDIAN); 299 object_property_set_link(OBJECT(dev), "dma_mr", 300 OBJECT(rc4030_dma_mr), &error_abort); 301 sysbus = SYS_BUS_DEVICE(dev); 302 sysbus_realize_and_unref(sysbus, &error_fatal); 303 sysbus_mmio_map(sysbus, 0, 0x80001000); 304 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 305 306 /* Add MAC address with valid checksum to PROM */ 307 prom = memory_region_get_ram_ptr(dp8393x_prom); 308 checksum = 0; 309 for (i = 0; i < 6; i++) { 310 prom[i] = nd->macaddr.a[i]; 311 checksum += prom[i]; 312 if (checksum > 0xff) { 313 checksum = (checksum + 1) & 0xff; 314 } 315 } 316 prom[7] = 0xff - checksum; 317 break; 318 } else if (is_help_option(nd->model)) { 319 error_report("Supported NICs: dp83932"); 320 exit(1); 321 } else { 322 error_report("Unsupported NIC: %s", nd->model); 323 exit(1); 324 } 325 } 326 327 /* SCSI adapter */ 328 dev = qdev_new(TYPE_SYSBUS_ESP); 329 sysbus_esp = SYSBUS_ESP(dev); 330 esp = &sysbus_esp->esp; 331 esp->dma_memory_read = rc4030_dma_read; 332 esp->dma_memory_write = rc4030_dma_write; 333 esp->dma_opaque = dmas[0]; 334 sysbus_esp->it_shift = 0; 335 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 336 esp->dma_enabled = 1; 337 338 sysbus = SYS_BUS_DEVICE(dev); 339 sysbus_realize_and_unref(sysbus, &error_fatal); 340 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 341 sysbus_mmio_map(sysbus, 0, 0x80002000); 342 343 scsi_bus_legacy_handle_cmdline(&esp->bus); 344 345 /* Floppy */ 346 for (n = 0; n < MAX_FD; n++) { 347 fds[n] = drive_get(IF_FLOPPY, 0, n); 348 } 349 /* FIXME: we should enable DMA with a custom IsaDma device */ 350 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0x80003000, fds); 351 352 /* Real time clock */ 353 mc146818_rtc_init(isa_bus, 1980, NULL); 354 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 355 memory_region_add_subregion(address_space, 0x80004000, rtc); 356 357 /* Keyboard (i8042) */ 358 i8042 = I8042_MMIO(qdev_new(TYPE_I8042_MMIO)); 359 qdev_prop_set_uint64(DEVICE(i8042), "mask", 1); 360 qdev_prop_set_uint32(DEVICE(i8042), "size", 0x1000); 361 sysbus_realize_and_unref(SYS_BUS_DEVICE(i8042), &error_fatal); 362 363 qdev_connect_gpio_out(DEVICE(i8042), I8042_KBD_IRQ, 364 qdev_get_gpio_in(rc4030, 6)); 365 qdev_connect_gpio_out(DEVICE(i8042), I8042_MOUSE_IRQ, 366 qdev_get_gpio_in(rc4030, 7)); 367 368 memory_region_add_subregion(address_space, 0x80005000, 369 sysbus_mmio_get_region(SYS_BUS_DEVICE(i8042), 370 0)); 371 372 /* Serial ports */ 373 serial_mm_init(address_space, 0x80006000, 0, 374 qdev_get_gpio_in(rc4030, 8), 8000000 / 16, 375 serial_hd(0), DEVICE_NATIVE_ENDIAN); 376 serial_mm_init(address_space, 0x80007000, 0, 377 qdev_get_gpio_in(rc4030, 9), 8000000 / 16, 378 serial_hd(1), DEVICE_NATIVE_ENDIAN); 379 380 /* Parallel port */ 381 if (parallel_hds[0]) 382 parallel_mm_init(address_space, 0x80008000, 0, 383 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 384 385 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 386 387 /* NVRAM */ 388 dev = qdev_new("ds1225y"); 389 sysbus = SYS_BUS_DEVICE(dev); 390 sysbus_realize_and_unref(sysbus, &error_fatal); 391 sysbus_mmio_map(sysbus, 0, 0x80009000); 392 393 /* LED indicator */ 394 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 395 396 g_free(dmas); 397 } 398 399 static 400 void mips_magnum_init(MachineState *machine) 401 { 402 mips_jazz_init(machine, JAZZ_MAGNUM); 403 } 404 405 static 406 void mips_pica61_init(MachineState *machine) 407 { 408 mips_jazz_init(machine, JAZZ_PICA61); 409 } 410 411 static void mips_magnum_class_init(ObjectClass *oc, void *data) 412 { 413 MachineClass *mc = MACHINE_CLASS(oc); 414 415 mc->desc = "MIPS Magnum"; 416 mc->init = mips_magnum_init; 417 mc->block_default_type = IF_SCSI; 418 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 419 mc->default_ram_id = "mips_jazz.ram"; 420 } 421 422 static const TypeInfo mips_magnum_type = { 423 .name = MACHINE_TYPE_NAME("magnum"), 424 .parent = TYPE_MACHINE, 425 .class_init = mips_magnum_class_init, 426 }; 427 428 static void mips_pica61_class_init(ObjectClass *oc, void *data) 429 { 430 MachineClass *mc = MACHINE_CLASS(oc); 431 432 mc->desc = "Acer Pica 61"; 433 mc->init = mips_pica61_init; 434 mc->block_default_type = IF_SCSI; 435 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 436 mc->default_ram_id = "mips_jazz.ram"; 437 } 438 439 static const TypeInfo mips_pica61_type = { 440 .name = MACHINE_TYPE_NAME("pica61"), 441 .parent = TYPE_MACHINE, 442 .class_init = mips_pica61_class_init, 443 }; 444 445 static void mips_jazz_machine_init(void) 446 { 447 type_register_static(&mips_magnum_type); 448 type_register_static(&mips_pica61_type); 449 } 450 451 type_init(mips_jazz_machine_init) 452