1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "hw/clock.h" 29 #include "hw/mips/mips.h" 30 #include "hw/mips/cpudevs.h" 31 #include "hw/intc/i8259.h" 32 #include "hw/dma/i8257.h" 33 #include "hw/char/serial.h" 34 #include "hw/char/parallel.h" 35 #include "hw/isa/isa.h" 36 #include "hw/block/fdc.h" 37 #include "sysemu/sysemu.h" 38 #include "sysemu/arch_init.h" 39 #include "hw/boards.h" 40 #include "net/net.h" 41 #include "hw/scsi/esp.h" 42 #include "hw/mips/bios.h" 43 #include "hw/loader.h" 44 #include "hw/rtc/mc146818rtc.h" 45 #include "hw/timer/i8254.h" 46 #include "hw/display/vga.h" 47 #include "hw/audio/pcspk.h" 48 #include "hw/input/i8042.h" 49 #include "hw/sysbus.h" 50 #include "sysemu/qtest.h" 51 #include "sysemu/reset.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "qemu/help_option.h" 55 #ifdef CONFIG_TCG 56 #include "hw/core/tcg-cpu-ops.h" 57 #endif /* CONFIG_TCG */ 58 59 enum jazz_model_e { 60 JAZZ_MAGNUM, 61 JAZZ_PICA61, 62 }; 63 64 static void main_cpu_reset(void *opaque) 65 { 66 MIPSCPU *cpu = opaque; 67 68 cpu_reset(CPU(cpu)); 69 } 70 71 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 72 { 73 uint8_t val; 74 address_space_read(&address_space_memory, 0x90000071, 75 MEMTXATTRS_UNSPECIFIED, &val, 1); 76 return val; 77 } 78 79 static void rtc_write(void *opaque, hwaddr addr, 80 uint64_t val, unsigned size) 81 { 82 uint8_t buf = val & 0xff; 83 address_space_write(&address_space_memory, 0x90000071, 84 MEMTXATTRS_UNSPECIFIED, &buf, 1); 85 } 86 87 static const MemoryRegionOps rtc_ops = { 88 .read = rtc_read, 89 .write = rtc_write, 90 .endianness = DEVICE_NATIVE_ENDIAN, 91 }; 92 93 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 94 unsigned size) 95 { 96 /* 97 * Nothing to do. That is only to ensure that 98 * the current DMA acknowledge cycle is completed. 99 */ 100 return 0xff; 101 } 102 103 static void dma_dummy_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 /* 107 * Nothing to do. That is only to ensure that 108 * the current DMA acknowledge cycle is completed. 109 */ 110 } 111 112 static const MemoryRegionOps dma_dummy_ops = { 113 .read = dma_dummy_read, 114 .write = dma_dummy_write, 115 .endianness = DEVICE_NATIVE_ENDIAN, 116 }; 117 118 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 119 #define MAGNUM_BIOS_SIZE \ 120 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 121 122 static void mips_jazz_init(MachineState *machine, 123 enum jazz_model_e jazz_model) 124 { 125 MemoryRegion *address_space = get_system_memory(); 126 char *filename; 127 int bios_size, n; 128 Clock *cpuclk; 129 MIPSCPU *cpu; 130 MIPSCPUClass *mcc; 131 CPUMIPSState *env; 132 qemu_irq *i8259; 133 rc4030_dma *dmas; 134 IOMMUMemoryRegion *rc4030_dma_mr; 135 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 136 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 137 MemoryRegion *rtc = g_new(MemoryRegion, 1); 138 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 139 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 140 NICInfo *nd; 141 DeviceState *dev, *rc4030; 142 SysBusDevice *sysbus; 143 ISABus *isa_bus; 144 ISADevice *pit; 145 DriveInfo *fds[MAX_FD]; 146 MemoryRegion *bios = g_new(MemoryRegion, 1); 147 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 148 SysBusESPState *sysbus_esp; 149 ESPState *esp; 150 static const struct { 151 unsigned freq_hz; 152 unsigned pll_mult; 153 } ext_clk[] = { 154 [JAZZ_MAGNUM] = {50000000, 2}, 155 [JAZZ_PICA61] = {33333333, 4}, 156 }; 157 158 if (machine->ram_size > 256 * MiB) { 159 error_report("RAM size more than 256Mb is not supported"); 160 exit(EXIT_FAILURE); 161 } 162 163 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 164 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz 165 * ext_clk[jazz_model].pll_mult); 166 167 /* init CPUs */ 168 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 169 env = &cpu->env; 170 qemu_register_reset(main_cpu_reset, cpu); 171 172 /* 173 * Chipset returns 0 in invalid reads and do not raise data exceptions. 174 * However, we can't simply add a global memory region to catch 175 * everything, as this would make all accesses including instruction 176 * accesses be ignored and not raise exceptions. 177 * 178 * NOTE: this behaviour of raising exceptions for bad instruction 179 * fetches but not bad data accesses was added in commit 54e755588cf1e9 180 * to restore behaviour broken by c658b94f6e8c206, but it is not clear 181 * whether the real hardware behaves this way. It is possible that 182 * real hardware ignores bad instruction fetches as well -- if so then 183 * we could replace this hijacking of CPU methods with a simple global 184 * memory region that catches all memory accesses, as we do on Malta. 185 */ 186 mcc = MIPS_CPU_GET_CLASS(cpu); 187 mcc->no_data_aborts = true; 188 189 /* allocate RAM */ 190 memory_region_add_subregion(address_space, 0, machine->ram); 191 192 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 193 &error_fatal); 194 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 195 0, MAGNUM_BIOS_SIZE); 196 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 197 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 198 199 /* load the BIOS image. */ 200 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); 201 if (filename) { 202 bios_size = load_image_targphys(filename, 0xfff00000LL, 203 MAGNUM_BIOS_SIZE); 204 g_free(filename); 205 } else { 206 bios_size = -1; 207 } 208 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) 209 && machine->firmware && !qtest_enabled()) { 210 error_report("Could not load MIPS bios '%s'", machine->firmware); 211 exit(1); 212 } 213 214 /* Init CPU internal devices */ 215 cpu_mips_irq_init_cpu(cpu); 216 cpu_mips_clock_init(cpu); 217 218 /* Chipset */ 219 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 220 sysbus = SYS_BUS_DEVICE(rc4030); 221 sysbus_connect_irq(sysbus, 0, env->irq[6]); 222 sysbus_connect_irq(sysbus, 1, env->irq[3]); 223 memory_region_add_subregion(address_space, 0x80000000, 224 sysbus_mmio_get_region(sysbus, 0)); 225 memory_region_add_subregion(address_space, 0xf0000000, 226 sysbus_mmio_get_region(sysbus, 1)); 227 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, 228 NULL, "dummy_dma", 0x1000); 229 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 230 231 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 232 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 233 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 234 memory_region_add_subregion(address_space, 0x90000000, isa_io); 235 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 236 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 237 238 /* ISA devices */ 239 i8259 = i8259_init(isa_bus, env->irq[4]); 240 isa_bus_irqs(isa_bus, i8259); 241 i8257_dma_init(isa_bus, 0); 242 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 243 pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit); 244 245 /* Video card */ 246 switch (jazz_model) { 247 case JAZZ_MAGNUM: 248 dev = qdev_new("sysbus-g364"); 249 sysbus = SYS_BUS_DEVICE(dev); 250 sysbus_realize_and_unref(sysbus, &error_fatal); 251 sysbus_mmio_map(sysbus, 0, 0x60080000); 252 sysbus_mmio_map(sysbus, 1, 0x40000000); 253 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 254 { 255 /* Simple ROM, so user doesn't have to provide one */ 256 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 257 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, 258 &error_fatal); 259 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 260 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 261 rom[0] = 0x10; /* Mips G364 */ 262 } 263 break; 264 case JAZZ_PICA61: 265 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 266 break; 267 default: 268 break; 269 } 270 271 /* Network controller */ 272 for (n = 0; n < nb_nics; n++) { 273 nd = &nd_table[n]; 274 if (!nd->model) { 275 nd->model = g_strdup("dp83932"); 276 } 277 if (strcmp(nd->model, "dp83932") == 0) { 278 qemu_check_nic_model(nd, "dp83932"); 279 280 dev = qdev_new("dp8393x"); 281 qdev_set_nic_properties(dev, nd); 282 qdev_prop_set_uint8(dev, "it_shift", 2); 283 object_property_set_link(OBJECT(dev), "dma_mr", 284 OBJECT(rc4030_dma_mr), &error_abort); 285 sysbus = SYS_BUS_DEVICE(dev); 286 sysbus_realize_and_unref(sysbus, &error_fatal); 287 sysbus_mmio_map(sysbus, 0, 0x80001000); 288 sysbus_mmio_map(sysbus, 1, 0x8000b000); 289 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 290 break; 291 } else if (is_help_option(nd->model)) { 292 error_report("Supported NICs: dp83932"); 293 exit(1); 294 } else { 295 error_report("Unsupported NIC: %s", nd->model); 296 exit(1); 297 } 298 } 299 300 /* SCSI adapter */ 301 dev = qdev_new(TYPE_SYSBUS_ESP); 302 sysbus_esp = SYSBUS_ESP(dev); 303 esp = &sysbus_esp->esp; 304 esp->dma_memory_read = rc4030_dma_read; 305 esp->dma_memory_write = rc4030_dma_write; 306 esp->dma_opaque = dmas[0]; 307 sysbus_esp->it_shift = 0; 308 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 309 esp->dma_enabled = 1; 310 311 sysbus = SYS_BUS_DEVICE(dev); 312 sysbus_realize_and_unref(sysbus, &error_fatal); 313 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 314 sysbus_mmio_map(sysbus, 0, 0x80002000); 315 316 scsi_bus_legacy_handle_cmdline(&esp->bus); 317 318 /* Floppy */ 319 for (n = 0; n < MAX_FD; n++) { 320 fds[n] = drive_get(IF_FLOPPY, 0, n); 321 } 322 /* FIXME: we should enable DMA with a custom IsaDma device */ 323 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); 324 325 /* Real time clock */ 326 mc146818_rtc_init(isa_bus, 1980, NULL); 327 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 328 memory_region_add_subregion(address_space, 0x80004000, rtc); 329 330 /* Keyboard (i8042) */ 331 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 332 i8042, 0x1000, 0x1); 333 memory_region_add_subregion(address_space, 0x80005000, i8042); 334 335 /* Serial ports */ 336 if (serial_hd(0)) { 337 serial_mm_init(address_space, 0x80006000, 0, 338 qdev_get_gpio_in(rc4030, 8), 8000000 / 16, 339 serial_hd(0), DEVICE_NATIVE_ENDIAN); 340 } 341 if (serial_hd(1)) { 342 serial_mm_init(address_space, 0x80007000, 0, 343 qdev_get_gpio_in(rc4030, 9), 8000000 / 16, 344 serial_hd(1), DEVICE_NATIVE_ENDIAN); 345 } 346 347 /* Parallel port */ 348 if (parallel_hds[0]) 349 parallel_mm_init(address_space, 0x80008000, 0, 350 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 351 352 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 353 354 /* NVRAM */ 355 dev = qdev_new("ds1225y"); 356 sysbus = SYS_BUS_DEVICE(dev); 357 sysbus_realize_and_unref(sysbus, &error_fatal); 358 sysbus_mmio_map(sysbus, 0, 0x80009000); 359 360 /* LED indicator */ 361 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 362 363 g_free(dmas); 364 } 365 366 static 367 void mips_magnum_init(MachineState *machine) 368 { 369 mips_jazz_init(machine, JAZZ_MAGNUM); 370 } 371 372 static 373 void mips_pica61_init(MachineState *machine) 374 { 375 mips_jazz_init(machine, JAZZ_PICA61); 376 } 377 378 static void mips_magnum_class_init(ObjectClass *oc, void *data) 379 { 380 MachineClass *mc = MACHINE_CLASS(oc); 381 382 mc->desc = "MIPS Magnum"; 383 mc->init = mips_magnum_init; 384 mc->block_default_type = IF_SCSI; 385 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 386 mc->default_ram_id = "mips_jazz.ram"; 387 } 388 389 static const TypeInfo mips_magnum_type = { 390 .name = MACHINE_TYPE_NAME("magnum"), 391 .parent = TYPE_MACHINE, 392 .class_init = mips_magnum_class_init, 393 }; 394 395 static void mips_pica61_class_init(ObjectClass *oc, void *data) 396 { 397 MachineClass *mc = MACHINE_CLASS(oc); 398 399 mc->desc = "Acer Pica 61"; 400 mc->init = mips_pica61_init; 401 mc->block_default_type = IF_SCSI; 402 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 403 mc->default_ram_id = "mips_jazz.ram"; 404 } 405 406 static const TypeInfo mips_pica61_type = { 407 .name = MACHINE_TYPE_NAME("pica61"), 408 .parent = TYPE_MACHINE, 409 .class_init = mips_pica61_class_init, 410 }; 411 412 static void mips_jazz_machine_init(void) 413 { 414 type_register_static(&mips_magnum_type); 415 type_register_static(&mips_pica61_type); 416 } 417 418 type_init(mips_jazz_machine_init) 419