1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "hw/clock.h" 28 #include "hw/mips/mips.h" 29 #include "hw/intc/i8259.h" 30 #include "hw/dma/i8257.h" 31 #include "hw/char/serial.h" 32 #include "hw/char/parallel.h" 33 #include "hw/isa/isa.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "hw/boards.h" 37 #include "net/net.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/mips/bios.h" 40 #include "hw/loader.h" 41 #include "hw/rtc/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/display/vga.h" 44 #include "hw/display/bochs-vbe.h" 45 #include "hw/audio/pcspk.h" 46 #include "hw/input/i8042.h" 47 #include "hw/sysbus.h" 48 #include "sysemu/qtest.h" 49 #include "sysemu/reset.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "qemu/help_option.h" 53 #ifdef CONFIG_TCG 54 #include "hw/core/tcg-cpu-ops.h" 55 #endif /* CONFIG_TCG */ 56 57 enum jazz_model_e { 58 JAZZ_MAGNUM, 59 JAZZ_PICA61, 60 }; 61 62 static void main_cpu_reset(void *opaque) 63 { 64 MIPSCPU *cpu = opaque; 65 66 cpu_reset(CPU(cpu)); 67 } 68 69 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 70 { 71 uint8_t val; 72 address_space_read(&address_space_memory, 0x90000071, 73 MEMTXATTRS_UNSPECIFIED, &val, 1); 74 return val; 75 } 76 77 static void rtc_write(void *opaque, hwaddr addr, 78 uint64_t val, unsigned size) 79 { 80 uint8_t buf = val & 0xff; 81 address_space_write(&address_space_memory, 0x90000071, 82 MEMTXATTRS_UNSPECIFIED, &buf, 1); 83 } 84 85 static const MemoryRegionOps rtc_ops = { 86 .read = rtc_read, 87 .write = rtc_write, 88 .endianness = DEVICE_NATIVE_ENDIAN, 89 }; 90 91 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 /* 95 * Nothing to do. That is only to ensure that 96 * the current DMA acknowledge cycle is completed. 97 */ 98 return 0xff; 99 } 100 101 static void dma_dummy_write(void *opaque, hwaddr addr, 102 uint64_t val, unsigned size) 103 { 104 /* 105 * Nothing to do. That is only to ensure that 106 * the current DMA acknowledge cycle is completed. 107 */ 108 } 109 110 static const MemoryRegionOps dma_dummy_ops = { 111 .read = dma_dummy_read, 112 .write = dma_dummy_write, 113 .endianness = DEVICE_NATIVE_ENDIAN, 114 }; 115 116 static void mips_jazz_init_net(NICInfo *nd, IOMMUMemoryRegion *rc4030_dma_mr, 117 DeviceState *rc4030, MemoryRegion *dp8393x_prom) 118 { 119 DeviceState *dev; 120 SysBusDevice *sysbus; 121 int checksum, i; 122 uint8_t *prom; 123 124 qemu_check_nic_model(nd, "dp83932"); 125 126 dev = qdev_new("dp8393x"); 127 qdev_set_nic_properties(dev, nd); 128 qdev_prop_set_uint8(dev, "it_shift", 2); 129 qdev_prop_set_bit(dev, "big_endian", TARGET_BIG_ENDIAN); 130 object_property_set_link(OBJECT(dev), "dma_mr", 131 OBJECT(rc4030_dma_mr), &error_abort); 132 sysbus = SYS_BUS_DEVICE(dev); 133 sysbus_realize_and_unref(sysbus, &error_fatal); 134 sysbus_mmio_map(sysbus, 0, 0x80001000); 135 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 136 137 /* Add MAC address with valid checksum to PROM */ 138 prom = memory_region_get_ram_ptr(dp8393x_prom); 139 checksum = 0; 140 for (i = 0; i < 6; i++) { 141 prom[i] = nd->macaddr.a[i]; 142 checksum += prom[i]; 143 if (checksum > 0xff) { 144 checksum = (checksum + 1) & 0xff; 145 } 146 } 147 prom[7] = 0xff - checksum; 148 } 149 150 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 151 #define MAGNUM_BIOS_SIZE \ 152 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 153 154 #define SONIC_PROM_SIZE 0x1000 155 156 static void mips_jazz_init(MachineState *machine, 157 enum jazz_model_e jazz_model) 158 { 159 MemoryRegion *address_space = get_system_memory(); 160 char *filename; 161 int bios_size, n; 162 Clock *cpuclk; 163 MIPSCPU *cpu; 164 MIPSCPUClass *mcc; 165 CPUMIPSState *env; 166 qemu_irq *i8259; 167 rc4030_dma *dmas; 168 IOMMUMemoryRegion *rc4030_dma_mr; 169 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 170 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 171 MemoryRegion *rtc = g_new(MemoryRegion, 1); 172 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 173 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); 174 DeviceState *dev, *rc4030; 175 MMIOKBDState *i8042; 176 SysBusDevice *sysbus; 177 ISABus *isa_bus; 178 ISADevice *pit; 179 ISADevice *pcspk; 180 DriveInfo *fds[MAX_FD]; 181 MemoryRegion *bios = g_new(MemoryRegion, 1); 182 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 183 SysBusESPState *sysbus_esp; 184 ESPState *esp; 185 static const struct { 186 unsigned freq_hz; 187 unsigned pll_mult; 188 } ext_clk[] = { 189 [JAZZ_MAGNUM] = {50000000, 2}, 190 [JAZZ_PICA61] = {33333333, 4}, 191 }; 192 193 if (machine->ram_size > 256 * MiB) { 194 error_report("RAM size more than 256Mb is not supported"); 195 exit(EXIT_FAILURE); 196 } 197 198 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); 199 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz 200 * ext_clk[jazz_model].pll_mult); 201 202 /* init CPUs */ 203 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); 204 env = &cpu->env; 205 qemu_register_reset(main_cpu_reset, cpu); 206 207 /* 208 * Chipset returns 0 in invalid reads and do not raise data exceptions. 209 * However, we can't simply add a global memory region to catch 210 * everything, as this would make all accesses including instruction 211 * accesses be ignored and not raise exceptions. 212 * 213 * NOTE: this behaviour of raising exceptions for bad instruction 214 * fetches but not bad data accesses was added in commit 54e755588cf1e9 215 * to restore behaviour broken by c658b94f6e8c206, but it is not clear 216 * whether the real hardware behaves this way. It is possible that 217 * real hardware ignores bad instruction fetches as well -- if so then 218 * we could replace this hijacking of CPU methods with a simple global 219 * memory region that catches all memory accesses, as we do on Malta. 220 */ 221 mcc = MIPS_CPU_GET_CLASS(cpu); 222 mcc->no_data_aborts = true; 223 224 /* allocate RAM */ 225 memory_region_add_subregion(address_space, 0, machine->ram); 226 227 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 228 &error_fatal); 229 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 230 0, MAGNUM_BIOS_SIZE); 231 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 232 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 233 234 /* load the BIOS image. */ 235 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); 236 if (filename) { 237 bios_size = load_image_targphys(filename, 0xfff00000LL, 238 MAGNUM_BIOS_SIZE); 239 g_free(filename); 240 } else { 241 bios_size = -1; 242 } 243 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) 244 && machine->firmware && !qtest_enabled()) { 245 error_report("Could not load MIPS bios '%s'", machine->firmware); 246 exit(1); 247 } 248 249 /* Init CPU internal devices */ 250 cpu_mips_irq_init_cpu(cpu); 251 cpu_mips_clock_init(cpu); 252 253 /* Chipset */ 254 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 255 sysbus = SYS_BUS_DEVICE(rc4030); 256 sysbus_connect_irq(sysbus, 0, env->irq[6]); 257 sysbus_connect_irq(sysbus, 1, env->irq[3]); 258 memory_region_add_subregion(address_space, 0x80000000, 259 sysbus_mmio_get_region(sysbus, 0)); 260 memory_region_add_subregion(address_space, 0xf0000000, 261 sysbus_mmio_get_region(sysbus, 1)); 262 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, 263 NULL, "dummy_dma", 0x1000); 264 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 265 266 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom", 267 SONIC_PROM_SIZE, &error_fatal); 268 memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom); 269 270 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 271 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 272 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 273 memory_region_add_subregion(address_space, 0x90000000, isa_io); 274 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 275 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 276 277 /* ISA devices */ 278 i8259 = i8259_init(isa_bus, env->irq[4]); 279 isa_bus_register_input_irqs(isa_bus, i8259); 280 i8257_dma_init(isa_bus, 0); 281 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 282 pcspk = isa_new(TYPE_PC_SPEAKER); 283 object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal); 284 isa_realize_and_unref(pcspk, isa_bus, &error_fatal); 285 286 /* Video card */ 287 switch (jazz_model) { 288 case JAZZ_MAGNUM: 289 dev = qdev_new("sysbus-g364"); 290 sysbus = SYS_BUS_DEVICE(dev); 291 sysbus_realize_and_unref(sysbus, &error_fatal); 292 sysbus_mmio_map(sysbus, 0, 0x60080000); 293 sysbus_mmio_map(sysbus, 1, 0x40000000); 294 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 295 { 296 /* Simple ROM, so user doesn't have to provide one */ 297 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 298 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, 299 &error_fatal); 300 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 301 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 302 rom[0] = 0x10; /* Mips G364 */ 303 } 304 break; 305 case JAZZ_PICA61: 306 dev = qdev_new(TYPE_VGA_MMIO); 307 qdev_prop_set_uint8(dev, "it_shift", 0); 308 sysbus = SYS_BUS_DEVICE(dev); 309 sysbus_realize_and_unref(sysbus, &error_fatal); 310 sysbus_mmio_map(sysbus, 0, 0x60000000); 311 sysbus_mmio_map(sysbus, 1, 0x400a0000); 312 sysbus_mmio_map(sysbus, 2, VBE_DISPI_LFB_PHYSICAL_ADDRESS); 313 break; 314 default: 315 break; 316 } 317 318 /* Network controller */ 319 if (nb_nics == 1) { 320 mips_jazz_init_net(&nd_table[0], rc4030_dma_mr, rc4030, dp8393x_prom); 321 } else if (nb_nics > 1) { 322 error_report("This machine only supports one NIC"); 323 exit(1); 324 } 325 326 /* SCSI adapter */ 327 dev = qdev_new(TYPE_SYSBUS_ESP); 328 sysbus_esp = SYSBUS_ESP(dev); 329 esp = &sysbus_esp->esp; 330 esp->dma_memory_read = rc4030_dma_read; 331 esp->dma_memory_write = rc4030_dma_write; 332 esp->dma_opaque = dmas[0]; 333 sysbus_esp->it_shift = 0; 334 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 335 esp->dma_enabled = 1; 336 337 sysbus = SYS_BUS_DEVICE(dev); 338 sysbus_realize_and_unref(sysbus, &error_fatal); 339 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 340 sysbus_mmio_map(sysbus, 0, 0x80002000); 341 342 scsi_bus_legacy_handle_cmdline(&esp->bus); 343 344 /* Floppy */ 345 for (n = 0; n < MAX_FD; n++) { 346 fds[n] = drive_get(IF_FLOPPY, 0, n); 347 } 348 /* FIXME: we should enable DMA with a custom IsaDma device */ 349 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0x80003000, fds); 350 351 /* Real time clock */ 352 mc146818_rtc_init(isa_bus, 1980, NULL); 353 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 354 memory_region_add_subregion(address_space, 0x80004000, rtc); 355 356 /* Keyboard (i8042) */ 357 i8042 = I8042_MMIO(qdev_new(TYPE_I8042_MMIO)); 358 qdev_prop_set_uint64(DEVICE(i8042), "mask", 1); 359 qdev_prop_set_uint32(DEVICE(i8042), "size", 0x1000); 360 sysbus_realize_and_unref(SYS_BUS_DEVICE(i8042), &error_fatal); 361 362 qdev_connect_gpio_out(DEVICE(i8042), I8042_KBD_IRQ, 363 qdev_get_gpio_in(rc4030, 6)); 364 qdev_connect_gpio_out(DEVICE(i8042), I8042_MOUSE_IRQ, 365 qdev_get_gpio_in(rc4030, 7)); 366 367 memory_region_add_subregion(address_space, 0x80005000, 368 sysbus_mmio_get_region(SYS_BUS_DEVICE(i8042), 369 0)); 370 371 /* Serial ports */ 372 serial_mm_init(address_space, 0x80006000, 0, 373 qdev_get_gpio_in(rc4030, 8), 8000000 / 16, 374 serial_hd(0), DEVICE_NATIVE_ENDIAN); 375 serial_mm_init(address_space, 0x80007000, 0, 376 qdev_get_gpio_in(rc4030, 9), 8000000 / 16, 377 serial_hd(1), DEVICE_NATIVE_ENDIAN); 378 379 /* Parallel port */ 380 if (parallel_hds[0]) 381 parallel_mm_init(address_space, 0x80008000, 0, 382 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 383 384 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 385 386 /* NVRAM */ 387 dev = qdev_new("ds1225y"); 388 sysbus = SYS_BUS_DEVICE(dev); 389 sysbus_realize_and_unref(sysbus, &error_fatal); 390 sysbus_mmio_map(sysbus, 0, 0x80009000); 391 392 /* LED indicator */ 393 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 394 395 g_free(dmas); 396 } 397 398 static 399 void mips_magnum_init(MachineState *machine) 400 { 401 mips_jazz_init(machine, JAZZ_MAGNUM); 402 } 403 404 static 405 void mips_pica61_init(MachineState *machine) 406 { 407 mips_jazz_init(machine, JAZZ_PICA61); 408 } 409 410 static void mips_magnum_class_init(ObjectClass *oc, void *data) 411 { 412 MachineClass *mc = MACHINE_CLASS(oc); 413 414 mc->desc = "MIPS Magnum"; 415 mc->init = mips_magnum_init; 416 mc->block_default_type = IF_SCSI; 417 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 418 mc->default_ram_id = "mips_jazz.ram"; 419 } 420 421 static const TypeInfo mips_magnum_type = { 422 .name = MACHINE_TYPE_NAME("magnum"), 423 .parent = TYPE_MACHINE, 424 .class_init = mips_magnum_class_init, 425 }; 426 427 static void mips_pica61_class_init(ObjectClass *oc, void *data) 428 { 429 MachineClass *mc = MACHINE_CLASS(oc); 430 431 mc->desc = "Acer Pica 61"; 432 mc->init = mips_pica61_init; 433 mc->block_default_type = IF_SCSI; 434 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 435 mc->default_ram_id = "mips_jazz.ram"; 436 } 437 438 static const TypeInfo mips_pica61_type = { 439 .name = MACHINE_TYPE_NAME("pica61"), 440 .parent = TYPE_MACHINE, 441 .class_init = mips_pica61_class_init, 442 }; 443 444 static void mips_jazz_machine_init(void) 445 { 446 type_register_static(&mips_magnum_type); 447 type_register_static(&mips_pica61_type); 448 } 449 450 type_init(mips_jazz_machine_init) 451