1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/mips/cps.h" 23 #include "hw/mips/mips.h" 24 #include "hw/mips/cpudevs.h" 25 #include "sysemu/kvm.h" 26 27 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 28 { 29 MIPSCPU *cpu = MIPS_CPU(first_cpu); 30 CPUMIPSState *env = &cpu->env; 31 32 assert(pin_number < s->num_irq); 33 34 /* TODO: return GIC pins once implemented */ 35 return env->irq[pin_number]; 36 } 37 38 static void mips_cps_init(Object *obj) 39 { 40 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 41 MIPSCPSState *s = MIPS_CPS(obj); 42 43 /* Cover entire address space as there do not seem to be any 44 * constraints for the base address of CPC and GIC. */ 45 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 46 sysbus_init_mmio(sbd, &s->container); 47 } 48 49 static void main_cpu_reset(void *opaque) 50 { 51 MIPSCPU *cpu = opaque; 52 CPUState *cs = CPU(cpu); 53 54 cpu_reset(cs); 55 56 /* All VPs are halted on reset. Leave powering up to CPC. */ 57 cs->halted = 1; 58 } 59 60 static bool cpu_mips_itu_supported(CPUMIPSState *env) 61 { 62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || 63 (env->CP0_Config3 & (1 << CP0C3_MT)); 64 65 return is_mt && !kvm_enabled(); 66 } 67 68 static void mips_cps_realize(DeviceState *dev, Error **errp) 69 { 70 MIPSCPSState *s = MIPS_CPS(dev); 71 CPUMIPSState *env; 72 MIPSCPU *cpu; 73 int i; 74 Error *err = NULL; 75 target_ulong gcr_base; 76 bool itu_present = false; 77 78 for (i = 0; i < s->num_vp; i++) { 79 cpu = cpu_mips_init(s->cpu_model); 80 if (cpu == NULL) { 81 error_setg(errp, "%s: CPU initialization failed\n", __func__); 82 return; 83 } 84 85 /* Init internal devices */ 86 cpu_mips_irq_init_cpu(cpu); 87 cpu_mips_clock_init(cpu); 88 89 env = &cpu->env; 90 if (cpu_mips_itu_supported(env)) { 91 itu_present = true; 92 /* Attach ITC Tag to the VP */ 93 env->itc_tag = mips_itu_get_tag_region(&s->itu); 94 } 95 qemu_register_reset(main_cpu_reset, cpu); 96 } 97 98 cpu = MIPS_CPU(first_cpu); 99 env = &cpu->env; 100 101 /* Inter-Thread Communication Unit */ 102 if (itu_present) { 103 object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); 104 qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); 105 106 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 107 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 108 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 return; 112 } 113 114 memory_region_add_subregion(&s->container, 0, 115 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); 116 } 117 118 /* Cluster Power Controller */ 119 object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); 120 qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); 121 122 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 123 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 124 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 125 if (err != NULL) { 126 error_propagate(errp, err); 127 return; 128 } 129 130 memory_region_add_subregion(&s->container, 0, 131 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 132 133 /* Global Configuration Registers */ 134 gcr_base = env->CP0_CMGCRBase << 4; 135 136 object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); 137 qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); 138 139 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 140 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 141 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 142 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 143 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 144 if (err != NULL) { 145 error_propagate(errp, err); 146 return; 147 } 148 149 memory_region_add_subregion(&s->container, gcr_base, 150 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 151 } 152 153 static Property mips_cps_properties[] = { 154 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 155 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8), 156 DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model), 157 DEFINE_PROP_END_OF_LIST() 158 }; 159 160 static void mips_cps_class_init(ObjectClass *klass, void *data) 161 { 162 DeviceClass *dc = DEVICE_CLASS(klass); 163 164 dc->realize = mips_cps_realize; 165 dc->props = mips_cps_properties; 166 } 167 168 static const TypeInfo mips_cps_info = { 169 .name = TYPE_MIPS_CPS, 170 .parent = TYPE_SYS_BUS_DEVICE, 171 .instance_size = sizeof(MIPSCPSState), 172 .instance_init = mips_cps_init, 173 .class_init = mips_cps_class_init, 174 }; 175 176 static void mips_cps_register_types(void) 177 { 178 type_register_static(&mips_cps_info); 179 } 180 181 type_init(mips_cps_register_types) 182