1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/module.h" 23 #include "hw/mips/cps.h" 24 #include "hw/mips/mips.h" 25 #include "hw/mips/cpudevs.h" 26 #include "sysemu/kvm.h" 27 28 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 29 { 30 assert(pin_number < s->num_irq); 31 return s->gic.irq_state[pin_number].irq; 32 } 33 34 static void mips_cps_init(Object *obj) 35 { 36 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 37 MIPSCPSState *s = MIPS_CPS(obj); 38 39 /* Cover entire address space as there do not seem to be any 40 * constraints for the base address of CPC and GIC. */ 41 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 42 sysbus_init_mmio(sbd, &s->container); 43 } 44 45 static void main_cpu_reset(void *opaque) 46 { 47 MIPSCPU *cpu = opaque; 48 CPUState *cs = CPU(cpu); 49 50 cpu_reset(cs); 51 52 /* All VPs are halted on reset. Leave powering up to CPC. */ 53 cs->halted = 1; 54 } 55 56 static bool cpu_mips_itu_supported(CPUMIPSState *env) 57 { 58 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || 59 (env->CP0_Config3 & (1 << CP0C3_MT)); 60 61 return is_mt && !kvm_enabled(); 62 } 63 64 static void mips_cps_realize(DeviceState *dev, Error **errp) 65 { 66 MIPSCPSState *s = MIPS_CPS(dev); 67 CPUMIPSState *env; 68 MIPSCPU *cpu; 69 int i; 70 Error *err = NULL; 71 target_ulong gcr_base; 72 bool itu_present = false; 73 bool saar_present = false; 74 75 for (i = 0; i < s->num_vp; i++) { 76 cpu = MIPS_CPU(cpu_create(s->cpu_type)); 77 78 /* Init internal devices */ 79 cpu_mips_irq_init_cpu(cpu); 80 cpu_mips_clock_init(cpu); 81 82 env = &cpu->env; 83 if (cpu_mips_itu_supported(env)) { 84 itu_present = true; 85 /* Attach ITC Tag to the VP */ 86 env->itc_tag = mips_itu_get_tag_region(&s->itu); 87 env->itu = &s->itu; 88 } 89 qemu_register_reset(main_cpu_reset, cpu); 90 } 91 92 cpu = MIPS_CPU(first_cpu); 93 env = &cpu->env; 94 saar_present = (bool)env->saarp; 95 96 /* Inter-Thread Communication Unit */ 97 if (itu_present) { 98 sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu), 99 TYPE_MIPS_ITU); 100 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 101 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 102 object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", 103 &err); 104 if (saar_present) { 105 qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR); 106 } 107 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 108 if (err != NULL) { 109 error_propagate(errp, err); 110 return; 111 } 112 113 memory_region_add_subregion(&s->container, 0, 114 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); 115 } 116 117 /* Cluster Power Controller */ 118 sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc), 119 TYPE_MIPS_CPC); 120 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 121 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 122 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 123 if (err != NULL) { 124 error_propagate(errp, err); 125 return; 126 } 127 128 memory_region_add_subregion(&s->container, 0, 129 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 130 131 /* Global Interrupt Controller */ 132 sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic), 133 TYPE_MIPS_GIC); 134 object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); 135 object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); 136 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 137 if (err != NULL) { 138 error_propagate(errp, err); 139 return; 140 } 141 142 memory_region_add_subregion(&s->container, 0, 143 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); 144 145 /* Global Configuration Registers */ 146 gcr_base = env->CP0_CMGCRBase << 4; 147 148 sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr), 149 TYPE_MIPS_GCR); 150 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 151 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 152 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 153 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); 154 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 155 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 156 if (err != NULL) { 157 error_propagate(errp, err); 158 return; 159 } 160 161 memory_region_add_subregion(&s->container, gcr_base, 162 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 163 } 164 165 static Property mips_cps_properties[] = { 166 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 167 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), 168 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), 169 DEFINE_PROP_END_OF_LIST() 170 }; 171 172 static void mips_cps_class_init(ObjectClass *klass, void *data) 173 { 174 DeviceClass *dc = DEVICE_CLASS(klass); 175 176 dc->realize = mips_cps_realize; 177 dc->props = mips_cps_properties; 178 } 179 180 static const TypeInfo mips_cps_info = { 181 .name = TYPE_MIPS_CPS, 182 .parent = TYPE_SYS_BUS_DEVICE, 183 .instance_size = sizeof(MIPSCPSState), 184 .instance_init = mips_cps_init, 185 .class_init = mips_cps_class_init, 186 }; 187 188 static void mips_cps_register_types(void) 189 { 190 type_register_static(&mips_cps_info); 191 } 192 193 type_init(mips_cps_register_types) 194