1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/module.h" 23 #include "hw/mips/cps.h" 24 #include "hw/mips/mips.h" 25 #include "hw/mips/cpudevs.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/reset.h" 28 29 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 30 { 31 assert(pin_number < s->num_irq); 32 return s->gic.irq_state[pin_number].irq; 33 } 34 35 static void mips_cps_init(Object *obj) 36 { 37 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 38 MIPSCPSState *s = MIPS_CPS(obj); 39 40 /* Cover entire address space as there do not seem to be any 41 * constraints for the base address of CPC and GIC. */ 42 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 43 sysbus_init_mmio(sbd, &s->container); 44 } 45 46 static void main_cpu_reset(void *opaque) 47 { 48 MIPSCPU *cpu = opaque; 49 CPUState *cs = CPU(cpu); 50 51 cpu_reset(cs); 52 53 /* All VPs are halted on reset. Leave powering up to CPC. */ 54 cs->halted = 1; 55 } 56 57 static bool cpu_mips_itu_supported(CPUMIPSState *env) 58 { 59 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || 60 (env->CP0_Config3 & (1 << CP0C3_MT)); 61 62 return is_mt && !kvm_enabled(); 63 } 64 65 static void mips_cps_realize(DeviceState *dev, Error **errp) 66 { 67 MIPSCPSState *s = MIPS_CPS(dev); 68 CPUMIPSState *env; 69 MIPSCPU *cpu; 70 int i; 71 Error *err = NULL; 72 target_ulong gcr_base; 73 bool itu_present = false; 74 bool saar_present = false; 75 76 for (i = 0; i < s->num_vp; i++) { 77 cpu = MIPS_CPU(cpu_create(s->cpu_type)); 78 79 /* Init internal devices */ 80 cpu_mips_irq_init_cpu(cpu); 81 cpu_mips_clock_init(cpu); 82 83 env = &cpu->env; 84 if (cpu_mips_itu_supported(env)) { 85 itu_present = true; 86 /* Attach ITC Tag to the VP */ 87 env->itc_tag = mips_itu_get_tag_region(&s->itu); 88 env->itu = &s->itu; 89 } 90 qemu_register_reset(main_cpu_reset, cpu); 91 } 92 93 cpu = MIPS_CPU(first_cpu); 94 env = &cpu->env; 95 saar_present = (bool)env->saarp; 96 97 /* Inter-Thread Communication Unit */ 98 if (itu_present) { 99 sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu), 100 TYPE_MIPS_ITU); 101 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 102 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 103 object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", 104 &err); 105 if (saar_present) { 106 qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR); 107 } 108 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 return; 112 } 113 114 memory_region_add_subregion(&s->container, 0, 115 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); 116 } 117 118 /* Cluster Power Controller */ 119 sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc), 120 TYPE_MIPS_CPC); 121 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 122 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 123 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 124 if (err != NULL) { 125 error_propagate(errp, err); 126 return; 127 } 128 129 memory_region_add_subregion(&s->container, 0, 130 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 131 132 /* Global Interrupt Controller */ 133 sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic), 134 TYPE_MIPS_GIC); 135 object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); 136 object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); 137 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 138 if (err != NULL) { 139 error_propagate(errp, err); 140 return; 141 } 142 143 memory_region_add_subregion(&s->container, 0, 144 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); 145 146 /* Global Configuration Registers */ 147 gcr_base = env->CP0_CMGCRBase << 4; 148 149 sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr), 150 TYPE_MIPS_GCR); 151 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 152 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 153 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 154 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); 155 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 156 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 157 if (err != NULL) { 158 error_propagate(errp, err); 159 return; 160 } 161 162 memory_region_add_subregion(&s->container, gcr_base, 163 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 164 } 165 166 static Property mips_cps_properties[] = { 167 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 168 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), 169 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), 170 DEFINE_PROP_END_OF_LIST() 171 }; 172 173 static void mips_cps_class_init(ObjectClass *klass, void *data) 174 { 175 DeviceClass *dc = DEVICE_CLASS(klass); 176 177 dc->realize = mips_cps_realize; 178 dc->props = mips_cps_properties; 179 } 180 181 static const TypeInfo mips_cps_info = { 182 .name = TYPE_MIPS_CPS, 183 .parent = TYPE_SYS_BUS_DEVICE, 184 .instance_size = sizeof(MIPSCPSState), 185 .instance_init = mips_cps_init, 186 .class_init = mips_cps_class_init, 187 }; 188 189 static void mips_cps_register_types(void) 190 { 191 type_register_static(&mips_cps_info); 192 } 193 194 type_init(mips_cps_register_types) 195