1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/mips/cps.h" 23 #include "hw/mips/mips.h" 24 #include "hw/mips/cpudevs.h" 25 #include "sysemu/kvm.h" 26 27 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 28 { 29 assert(pin_number < s->num_irq); 30 return s->gic.irq_state[pin_number].irq; 31 } 32 33 static void mips_cps_init(Object *obj) 34 { 35 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 36 MIPSCPSState *s = MIPS_CPS(obj); 37 38 /* Cover entire address space as there do not seem to be any 39 * constraints for the base address of CPC and GIC. */ 40 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 41 sysbus_init_mmio(sbd, &s->container); 42 } 43 44 static void main_cpu_reset(void *opaque) 45 { 46 MIPSCPU *cpu = opaque; 47 CPUState *cs = CPU(cpu); 48 49 cpu_reset(cs); 50 51 /* All VPs are halted on reset. Leave powering up to CPC. */ 52 cs->halted = 1; 53 } 54 55 static bool cpu_mips_itu_supported(CPUMIPSState *env) 56 { 57 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || 58 (env->CP0_Config3 & (1 << CP0C3_MT)); 59 60 return is_mt && !kvm_enabled(); 61 } 62 63 static void mips_cps_realize(DeviceState *dev, Error **errp) 64 { 65 MIPSCPSState *s = MIPS_CPS(dev); 66 CPUMIPSState *env; 67 MIPSCPU *cpu; 68 int i; 69 Error *err = NULL; 70 target_ulong gcr_base; 71 bool itu_present = false; 72 73 for (i = 0; i < s->num_vp; i++) { 74 cpu = MIPS_CPU(cpu_create(s->cpu_type)); 75 76 /* Init internal devices */ 77 cpu_mips_irq_init_cpu(cpu); 78 cpu_mips_clock_init(cpu); 79 80 env = &cpu->env; 81 if (cpu_mips_itu_supported(env)) { 82 itu_present = true; 83 /* Attach ITC Tag to the VP */ 84 env->itc_tag = mips_itu_get_tag_region(&s->itu); 85 } 86 qemu_register_reset(main_cpu_reset, cpu); 87 } 88 89 cpu = MIPS_CPU(first_cpu); 90 env = &cpu->env; 91 92 /* Inter-Thread Communication Unit */ 93 if (itu_present) { 94 object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); 95 qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); 96 97 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 98 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 99 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 100 if (err != NULL) { 101 error_propagate(errp, err); 102 return; 103 } 104 105 memory_region_add_subregion(&s->container, 0, 106 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); 107 } 108 109 /* Cluster Power Controller */ 110 object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); 111 qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); 112 113 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 114 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 115 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 116 if (err != NULL) { 117 error_propagate(errp, err); 118 return; 119 } 120 121 memory_region_add_subregion(&s->container, 0, 122 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 123 124 /* Global Interrupt Controller */ 125 object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC); 126 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 127 128 object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); 129 object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); 130 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 131 if (err != NULL) { 132 error_propagate(errp, err); 133 return; 134 } 135 136 memory_region_add_subregion(&s->container, 0, 137 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); 138 139 /* Global Configuration Registers */ 140 gcr_base = env->CP0_CMGCRBase << 4; 141 142 object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); 143 qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); 144 145 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 146 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 147 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 148 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); 149 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 150 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 151 if (err != NULL) { 152 error_propagate(errp, err); 153 return; 154 } 155 156 memory_region_add_subregion(&s->container, gcr_base, 157 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 158 } 159 160 static Property mips_cps_properties[] = { 161 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 162 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), 163 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), 164 DEFINE_PROP_END_OF_LIST() 165 }; 166 167 static void mips_cps_class_init(ObjectClass *klass, void *data) 168 { 169 DeviceClass *dc = DEVICE_CLASS(klass); 170 171 dc->realize = mips_cps_realize; 172 dc->props = mips_cps_properties; 173 } 174 175 static const TypeInfo mips_cps_info = { 176 .name = TYPE_MIPS_CPS, 177 .parent = TYPE_SYS_BUS_DEVICE, 178 .instance_size = sizeof(MIPSCPSState), 179 .instance_init = mips_cps_init, 180 .class_init = mips_cps_class_init, 181 }; 182 183 static void mips_cps_register_types(void) 184 { 185 type_register_static(&mips_cps_info); 186 } 187 188 type_init(mips_cps_register_types) 189