1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/module.h" 23 #include "hw/mips/cps.h" 24 #include "hw/mips/mips.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/mips/cpudevs.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/reset.h" 29 30 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 31 { 32 assert(pin_number < s->num_irq); 33 return s->gic.irq_state[pin_number].irq; 34 } 35 36 static void mips_cps_init(Object *obj) 37 { 38 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 39 MIPSCPSState *s = MIPS_CPS(obj); 40 41 /* Cover entire address space as there do not seem to be any 42 * constraints for the base address of CPC and GIC. */ 43 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 44 sysbus_init_mmio(sbd, &s->container); 45 } 46 47 static void main_cpu_reset(void *opaque) 48 { 49 MIPSCPU *cpu = opaque; 50 CPUState *cs = CPU(cpu); 51 52 cpu_reset(cs); 53 54 /* All VPs are halted on reset. Leave powering up to CPC. */ 55 cs->halted = 1; 56 } 57 58 static bool cpu_mips_itu_supported(CPUMIPSState *env) 59 { 60 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || 61 (env->CP0_Config3 & (1 << CP0C3_MT)); 62 63 return is_mt && !kvm_enabled(); 64 } 65 66 static void mips_cps_realize(DeviceState *dev, Error **errp) 67 { 68 MIPSCPSState *s = MIPS_CPS(dev); 69 CPUMIPSState *env; 70 MIPSCPU *cpu; 71 int i; 72 Error *err = NULL; 73 target_ulong gcr_base; 74 bool itu_present = false; 75 bool saar_present = false; 76 77 for (i = 0; i < s->num_vp; i++) { 78 cpu = MIPS_CPU(cpu_create(s->cpu_type)); 79 80 /* Init internal devices */ 81 cpu_mips_irq_init_cpu(cpu); 82 cpu_mips_clock_init(cpu); 83 84 env = &cpu->env; 85 if (cpu_mips_itu_supported(env)) { 86 itu_present = true; 87 /* Attach ITC Tag to the VP */ 88 env->itc_tag = mips_itu_get_tag_region(&s->itu); 89 env->itu = &s->itu; 90 } 91 qemu_register_reset(main_cpu_reset, cpu); 92 } 93 94 cpu = MIPS_CPU(first_cpu); 95 env = &cpu->env; 96 saar_present = (bool)env->saarp; 97 98 /* Inter-Thread Communication Unit */ 99 if (itu_present) { 100 sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu), 101 TYPE_MIPS_ITU); 102 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 103 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 104 object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", 105 &err); 106 if (saar_present) { 107 qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR); 108 } 109 object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 110 if (err != NULL) { 111 error_propagate(errp, err); 112 return; 113 } 114 115 memory_region_add_subregion(&s->container, 0, 116 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); 117 } 118 119 /* Cluster Power Controller */ 120 sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc), 121 TYPE_MIPS_CPC); 122 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 123 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 124 object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 125 if (err != NULL) { 126 error_propagate(errp, err); 127 return; 128 } 129 130 memory_region_add_subregion(&s->container, 0, 131 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 132 133 /* Global Interrupt Controller */ 134 sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic), 135 TYPE_MIPS_GIC); 136 object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); 137 object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); 138 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 139 if (err != NULL) { 140 error_propagate(errp, err); 141 return; 142 } 143 144 memory_region_add_subregion(&s->container, 0, 145 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); 146 147 /* Global Configuration Registers */ 148 gcr_base = env->CP0_CMGCRBase << 4; 149 150 sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr), 151 TYPE_MIPS_GCR); 152 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 153 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 154 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 155 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); 156 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 157 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 158 if (err != NULL) { 159 error_propagate(errp, err); 160 return; 161 } 162 163 memory_region_add_subregion(&s->container, gcr_base, 164 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 165 } 166 167 static Property mips_cps_properties[] = { 168 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 169 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), 170 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), 171 DEFINE_PROP_END_OF_LIST() 172 }; 173 174 static void mips_cps_class_init(ObjectClass *klass, void *data) 175 { 176 DeviceClass *dc = DEVICE_CLASS(klass); 177 178 dc->realize = mips_cps_realize; 179 dc->props = mips_cps_properties; 180 } 181 182 static const TypeInfo mips_cps_info = { 183 .name = TYPE_MIPS_CPS, 184 .parent = TYPE_SYS_BUS_DEVICE, 185 .instance_size = sizeof(MIPSCPSState), 186 .instance_init = mips_cps_init, 187 .class_init = mips_cps_class_init, 188 }; 189 190 static void mips_cps_register_types(void) 191 { 192 type_register_static(&mips_cps_info); 193 } 194 195 type_init(mips_cps_register_types) 196