1 /* 2 * MIPS Boston development board emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 23 #include "exec/address-spaces.h" 24 #include "hw/boards.h" 25 #include "hw/char/serial.h" 26 #include "hw/ide/pci.h" 27 #include "hw/ide/ahci.h" 28 #include "hw/loader.h" 29 #include "hw/loader-fit.h" 30 #include "hw/mips/cps.h" 31 #include "hw/mips/cpudevs.h" 32 #include "hw/pci-host/xilinx-pcie.h" 33 #include "hw/qdev-clock.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 #include "qemu/error-report.h" 37 #include "qemu/log.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "sysemu/qtest.h" 42 #include "sysemu/runstate.h" 43 44 #include <libfdt.h> 45 #include "qom/object.h" 46 47 #define TYPE_BOSTON "mips-boston" 48 typedef struct BostonState BostonState; 49 DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, 50 TYPE_BOSTON) 51 52 struct BostonState { 53 SysBusDevice parent_obj; 54 55 MachineState *mach; 56 MIPSCPSState cps; 57 SerialMM *uart; 58 Clock *cpuclk; 59 60 CharBackend lcd_display; 61 char lcd_content[8]; 62 bool lcd_inited; 63 64 hwaddr kernel_entry; 65 hwaddr fdt_base; 66 }; 67 68 enum boston_plat_reg { 69 PLAT_FPGA_BUILD = 0x00, 70 PLAT_CORE_CL = 0x04, 71 PLAT_WRAPPER_CL = 0x08, 72 PLAT_SYSCLK_STATUS = 0x0c, 73 PLAT_SOFTRST_CTL = 0x10, 74 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) 75 PLAT_DDR3_STATUS = 0x14, 76 #define PLAT_DDR3_STATUS_LOCKED (1 << 0) 77 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) 78 PLAT_PCIE_STATUS = 0x18, 79 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) 80 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) 81 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) 82 PLAT_FLASH_CTL = 0x1c, 83 PLAT_SPARE0 = 0x20, 84 PLAT_SPARE1 = 0x24, 85 PLAT_SPARE2 = 0x28, 86 PLAT_SPARE3 = 0x2c, 87 PLAT_MMCM_DIV = 0x30, 88 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 89 #define PLAT_MMCM_DIV_INPUT_SHIFT 8 90 #define PLAT_MMCM_DIV_MUL_SHIFT 16 91 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 92 PLAT_BUILD_CFG = 0x34, 93 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) 94 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) 95 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) 96 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) 97 PLAT_DDR_CFG = 0x38, 98 #define PLAT_DDR_CFG_SIZE (0xf << 0) 99 #define PLAT_DDR_CFG_MHZ (0xfff << 4) 100 PLAT_NOC_PCIE0_ADDR = 0x3c, 101 PLAT_NOC_PCIE1_ADDR = 0x40, 102 PLAT_NOC_PCIE2_ADDR = 0x44, 103 PLAT_SYS_CTL = 0x48, 104 }; 105 106 static void boston_lcd_event(void *opaque, QEMUChrEvent event) 107 { 108 BostonState *s = opaque; 109 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { 110 qemu_chr_fe_printf(&s->lcd_display, " "); 111 s->lcd_inited = true; 112 } 113 } 114 115 static uint64_t boston_lcd_read(void *opaque, hwaddr addr, 116 unsigned size) 117 { 118 BostonState *s = opaque; 119 uint64_t val = 0; 120 121 switch (size) { 122 case 8: 123 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; 124 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; 125 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; 126 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; 127 /* fall through */ 128 case 4: 129 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; 130 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; 131 /* fall through */ 132 case 2: 133 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; 134 /* fall through */ 135 case 1: 136 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; 137 break; 138 } 139 140 return val; 141 } 142 143 static void boston_lcd_write(void *opaque, hwaddr addr, 144 uint64_t val, unsigned size) 145 { 146 BostonState *s = opaque; 147 148 switch (size) { 149 case 8: 150 s->lcd_content[(addr + 7) & 0x7] = val >> 56; 151 s->lcd_content[(addr + 6) & 0x7] = val >> 48; 152 s->lcd_content[(addr + 5) & 0x7] = val >> 40; 153 s->lcd_content[(addr + 4) & 0x7] = val >> 32; 154 /* fall through */ 155 case 4: 156 s->lcd_content[(addr + 3) & 0x7] = val >> 24; 157 s->lcd_content[(addr + 2) & 0x7] = val >> 16; 158 /* fall through */ 159 case 2: 160 s->lcd_content[(addr + 1) & 0x7] = val >> 8; 161 /* fall through */ 162 case 1: 163 s->lcd_content[(addr + 0) & 0x7] = val; 164 break; 165 } 166 167 qemu_chr_fe_printf(&s->lcd_display, 168 "\r%-8.8s", s->lcd_content); 169 } 170 171 static const MemoryRegionOps boston_lcd_ops = { 172 .read = boston_lcd_read, 173 .write = boston_lcd_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 }; 176 177 static uint64_t boston_platreg_read(void *opaque, hwaddr addr, 178 unsigned size) 179 { 180 BostonState *s = opaque; 181 uint32_t gic_freq, val; 182 183 if (size != 4) { 184 qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); 185 return 0; 186 } 187 188 switch (addr & 0xffff) { 189 case PLAT_FPGA_BUILD: 190 case PLAT_CORE_CL: 191 case PLAT_WRAPPER_CL: 192 return 0; 193 case PLAT_DDR3_STATUS: 194 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; 195 case PLAT_MMCM_DIV: 196 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; 197 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; 198 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; 199 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; 200 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; 201 return val; 202 case PLAT_BUILD_CFG: 203 val = PLAT_BUILD_CFG_PCIE0_EN; 204 val |= PLAT_BUILD_CFG_PCIE1_EN; 205 val |= PLAT_BUILD_CFG_PCIE2_EN; 206 return val; 207 case PLAT_DDR_CFG: 208 val = s->mach->ram_size / GiB; 209 assert(!(val & ~PLAT_DDR_CFG_SIZE)); 210 val |= PLAT_DDR_CFG_MHZ; 211 return val; 212 default: 213 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", 214 addr & 0xffff); 215 return 0; 216 } 217 } 218 219 static void boston_platreg_write(void *opaque, hwaddr addr, 220 uint64_t val, unsigned size) 221 { 222 if (size != 4) { 223 qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); 224 return; 225 } 226 227 switch (addr & 0xffff) { 228 case PLAT_FPGA_BUILD: 229 case PLAT_CORE_CL: 230 case PLAT_WRAPPER_CL: 231 case PLAT_DDR3_STATUS: 232 case PLAT_PCIE_STATUS: 233 case PLAT_MMCM_DIV: 234 case PLAT_BUILD_CFG: 235 case PLAT_DDR_CFG: 236 /* read only */ 237 break; 238 case PLAT_SOFTRST_CTL: 239 if (val & PLAT_SOFTRST_CTL_SYSRESET) { 240 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 241 } 242 break; 243 default: 244 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx 245 " = 0x%" PRIx64 "\n", addr & 0xffff, val); 246 break; 247 } 248 } 249 250 static const MemoryRegionOps boston_platreg_ops = { 251 .read = boston_platreg_read, 252 .write = boston_platreg_write, 253 .endianness = DEVICE_NATIVE_ENDIAN, 254 }; 255 256 static void mips_boston_instance_init(Object *obj) 257 { 258 BostonState *s = BOSTON(obj); 259 260 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 261 clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ 262 } 263 264 static const TypeInfo boston_device = { 265 .name = TYPE_BOSTON, 266 .parent = TYPE_SYS_BUS_DEVICE, 267 .instance_size = sizeof(BostonState), 268 .instance_init = mips_boston_instance_init, 269 }; 270 271 static void boston_register_types(void) 272 { 273 type_register_static(&boston_device); 274 } 275 type_init(boston_register_types) 276 277 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, 278 bool is_64b) 279 { 280 const uint32_t cm_base = 0x16100000; 281 const uint32_t gic_base = 0x16120000; 282 const uint32_t cpc_base = 0x16200000; 283 284 /* Move CM GCRs */ 285 if (is_64b) { 286 stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ 287 stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ 288 } else { 289 stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ 290 stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ 291 } 292 stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ 293 stl_p(p++, 0x01094025); /* or $8, $9 */ 294 stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ 295 if (is_64b) { 296 stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ 297 } else { 298 stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ 299 } 300 stl_p(p++, 0x012a4025); /* or $8, $10 */ 301 302 /* Move & enable GIC GCRs */ 303 stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ 304 stl_p(p++, 0x35290001); /* ori $9, 0x1 */ 305 if (is_64b) { 306 stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ 307 } else { 308 stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ 309 } 310 311 /* Move & enable CPC GCRs */ 312 stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ 313 stl_p(p++, 0x35290001); /* ori $9, 0x1 */ 314 if (is_64b) { 315 stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ 316 } else { 317 stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ 318 } 319 320 /* 321 * Setup argument registers to follow the UHI boot protocol: 322 * 323 * a0/$4 = -2 324 * a1/$5 = virtual address of FDT 325 * a2/$6 = 0 326 * a3/$7 = 0 327 */ 328 stl_p(p++, 0x2404fffe); /* li $4, -2 */ 329 /* lui $5, hi(fdt_addr) */ 330 stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); 331 if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ 332 stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); 333 } 334 stl_p(p++, 0x34060000); /* li $6, 0 */ 335 stl_p(p++, 0x34070000); /* li $7, 0 */ 336 337 /* Load kernel entry address & jump to it */ 338 /* lui $25, hi(kernel_entry) */ 339 stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); 340 /* ori $25, lo(kernel_entry) */ 341 stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); 342 stl_p(p++, 0x03200009); /* jr $25 */ 343 } 344 345 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, 346 const void *match_data, hwaddr *load_addr) 347 { 348 BostonState *s = BOSTON(opaque); 349 MachineState *machine = s->mach; 350 const char *cmdline; 351 int err; 352 size_t ram_low_sz, ram_high_sz; 353 size_t fdt_sz = fdt_totalsize(fdt_orig) * 2; 354 g_autofree void *fdt = g_malloc0(fdt_sz); 355 356 err = fdt_open_into(fdt_orig, fdt, fdt_sz); 357 if (err) { 358 fprintf(stderr, "unable to open FDT\n"); 359 return NULL; 360 } 361 362 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) 363 ? machine->kernel_cmdline : " "; 364 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 365 if (err < 0) { 366 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 367 return NULL; 368 } 369 370 ram_low_sz = MIN(256 * MiB, machine->ram_size); 371 ram_high_sz = machine->ram_size - ram_low_sz; 372 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", 373 1, 0x00000000, 1, ram_low_sz, 374 1, 0x90000000, 1, ram_high_sz); 375 376 fdt = g_realloc(fdt, fdt_totalsize(fdt)); 377 qemu_fdt_dumpdtb(fdt, fdt_sz); 378 379 s->fdt_base = *load_addr; 380 381 return g_steal_pointer(&fdt); 382 } 383 384 static const void *boston_kernel_filter(void *opaque, const void *kernel, 385 hwaddr *load_addr, hwaddr *entry_addr) 386 { 387 BostonState *s = BOSTON(opaque); 388 389 s->kernel_entry = *entry_addr; 390 391 return kernel; 392 } 393 394 static const struct fit_loader_match boston_matches[] = { 395 { "img,boston" }, 396 { NULL }, 397 }; 398 399 static const struct fit_loader boston_fit_loader = { 400 .matches = boston_matches, 401 .addr_to_phys = cpu_mips_kseg0_to_phys, 402 .fdt_filter = boston_fdt_filter, 403 .kernel_filter = boston_kernel_filter, 404 }; 405 406 static inline XilinxPCIEHost * 407 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, 408 hwaddr cfg_base, uint64_t cfg_size, 409 hwaddr mmio_base, uint64_t mmio_size, 410 qemu_irq irq, bool link_up) 411 { 412 DeviceState *dev; 413 MemoryRegion *cfg, *mmio; 414 415 dev = qdev_new(TYPE_XILINX_PCIE_HOST); 416 417 qdev_prop_set_uint32(dev, "bus_nr", bus_nr); 418 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); 419 qdev_prop_set_uint64(dev, "cfg_size", cfg_size); 420 qdev_prop_set_uint64(dev, "mmio_base", mmio_base); 421 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 422 qdev_prop_set_bit(dev, "link_up", link_up); 423 424 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 425 426 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 427 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); 428 429 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 430 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); 431 432 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); 433 434 return XILINX_PCIE_HOST(dev); 435 } 436 437 static void boston_mach_init(MachineState *machine) 438 { 439 DeviceState *dev; 440 BostonState *s; 441 MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; 442 MemoryRegion *sys_mem = get_system_memory(); 443 XilinxPCIEHost *pcie2; 444 PCIDevice *ahci; 445 DriveInfo *hd[6]; 446 Chardev *chr; 447 int fw_size, fit_err; 448 bool is_64b; 449 450 if ((machine->ram_size % GiB) || 451 (machine->ram_size > (2 * GiB))) { 452 error_report("Memory size must be 1GB or 2GB"); 453 exit(1); 454 } 455 456 dev = qdev_new(TYPE_BOSTON); 457 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 458 459 s = BOSTON(dev); 460 s->mach = machine; 461 462 if (!cpu_supports_cps_smp(machine->cpu_type)) { 463 error_report("Boston requires CPUs which support CPS"); 464 exit(1); 465 } 466 467 is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); 468 469 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); 470 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, 471 &error_fatal); 472 object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, 473 &error_fatal); 474 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", 475 qdev_get_clock_out(dev, "cpu-refclk")); 476 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 477 478 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 479 480 flash = g_new(MemoryRegion, 1); 481 memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, 482 &error_fatal); 483 memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); 484 485 memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); 486 487 ddr_low_alias = g_new(MemoryRegion, 1); 488 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", 489 machine->ram, 0, 490 MIN(machine->ram_size, (256 * MiB))); 491 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); 492 493 xilinx_pcie_init(sys_mem, 0, 494 0x10000000, 32 * MiB, 495 0x40000000, 1 * GiB, 496 get_cps_irq(&s->cps, 2), false); 497 498 xilinx_pcie_init(sys_mem, 1, 499 0x12000000, 32 * MiB, 500 0x20000000, 512 * MiB, 501 get_cps_irq(&s->cps, 1), false); 502 503 pcie2 = xilinx_pcie_init(sys_mem, 2, 504 0x14000000, 32 * MiB, 505 0x16000000, 1 * MiB, 506 get_cps_irq(&s->cps, 0), true); 507 508 platreg = g_new(MemoryRegion, 1); 509 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, 510 "boston-platregs", 0x1000); 511 memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); 512 513 s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, 514 get_cps_irq(&s->cps, 3), 10000000, 515 serial_hd(0), DEVICE_NATIVE_ENDIAN); 516 517 lcd = g_new(MemoryRegion, 1); 518 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); 519 memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); 520 521 chr = qemu_chr_new("lcd", "vc:320x240", NULL); 522 qemu_chr_fe_init(&s->lcd_display, chr, NULL); 523 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, 524 boston_lcd_event, NULL, s, NULL, true); 525 526 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, 527 PCI_DEVFN(0, 0), 528 true, TYPE_ICH9_AHCI); 529 g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); 530 ide_drive_get(hd, ahci_get_num_ports(ahci)); 531 ahci_ide_create_devs(ahci, hd); 532 533 if (machine->firmware) { 534 fw_size = load_image_targphys(machine->firmware, 535 0x1fc00000, 4 * MiB); 536 if (fw_size == -1) { 537 error_report("unable to load firmware image '%s'", 538 machine->firmware); 539 exit(1); 540 } 541 } else if (machine->kernel_filename) { 542 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); 543 if (fit_err) { 544 error_report("unable to load FIT image"); 545 exit(1); 546 } 547 548 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, 549 s->kernel_entry, s->fdt_base, is_64b); 550 } else if (!qtest_enabled()) { 551 error_report("Please provide either a -kernel or -bios argument"); 552 exit(1); 553 } 554 } 555 556 static void boston_mach_class_init(MachineClass *mc) 557 { 558 mc->desc = "MIPS Boston"; 559 mc->init = boston_mach_init; 560 mc->block_default_type = IF_IDE; 561 mc->default_ram_size = 1 * GiB; 562 mc->default_ram_id = "boston.ddr"; 563 mc->max_cpus = 16; 564 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); 565 } 566 567 DEFINE_MACHINE("boston", boston_mach_class_init) 568