1 /* 2 * MIPS Boston development board emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 23 #include "exec/address-spaces.h" 24 #include "hw/boards.h" 25 #include "hw/char/serial.h" 26 #include "hw/hw.h" 27 #include "hw/ide/pci.h" 28 #include "hw/ide/ahci.h" 29 #include "hw/loader.h" 30 #include "hw/loader-fit.h" 31 #include "hw/mips/cps.h" 32 #include "hw/mips/cpudevs.h" 33 #include "hw/pci-host/xilinx-pcie.h" 34 #include "qapi/error.h" 35 #include "qemu/cutils.h" 36 #include "qemu/error-report.h" 37 #include "qemu/log.h" 38 #include "sysemu/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "sysemu/qtest.h" 42 43 #include <libfdt.h> 44 45 #define TYPE_MIPS_BOSTON "mips-boston" 46 #define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON) 47 48 typedef struct { 49 SysBusDevice parent_obj; 50 51 MachineState *mach; 52 MIPSCPSState *cps; 53 SerialState *uart; 54 55 CharBackend lcd_display; 56 char lcd_content[8]; 57 bool lcd_inited; 58 59 hwaddr kernel_entry; 60 hwaddr fdt_base; 61 } BostonState; 62 63 enum boston_plat_reg { 64 PLAT_FPGA_BUILD = 0x00, 65 PLAT_CORE_CL = 0x04, 66 PLAT_WRAPPER_CL = 0x08, 67 PLAT_SYSCLK_STATUS = 0x0c, 68 PLAT_SOFTRST_CTL = 0x10, 69 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) 70 PLAT_DDR3_STATUS = 0x14, 71 #define PLAT_DDR3_STATUS_LOCKED (1 << 0) 72 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) 73 PLAT_PCIE_STATUS = 0x18, 74 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) 75 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) 76 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) 77 PLAT_FLASH_CTL = 0x1c, 78 PLAT_SPARE0 = 0x20, 79 PLAT_SPARE1 = 0x24, 80 PLAT_SPARE2 = 0x28, 81 PLAT_SPARE3 = 0x2c, 82 PLAT_MMCM_DIV = 0x30, 83 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 84 #define PLAT_MMCM_DIV_INPUT_SHIFT 8 85 #define PLAT_MMCM_DIV_MUL_SHIFT 16 86 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 87 PLAT_BUILD_CFG = 0x34, 88 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) 89 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) 90 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) 91 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) 92 PLAT_DDR_CFG = 0x38, 93 #define PLAT_DDR_CFG_SIZE (0xf << 0) 94 #define PLAT_DDR_CFG_MHZ (0xfff << 4) 95 PLAT_NOC_PCIE0_ADDR = 0x3c, 96 PLAT_NOC_PCIE1_ADDR = 0x40, 97 PLAT_NOC_PCIE2_ADDR = 0x44, 98 PLAT_SYS_CTL = 0x48, 99 }; 100 101 static void boston_lcd_event(void *opaque, int event) 102 { 103 BostonState *s = opaque; 104 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { 105 qemu_chr_fe_printf(&s->lcd_display, " "); 106 s->lcd_inited = true; 107 } 108 } 109 110 static uint64_t boston_lcd_read(void *opaque, hwaddr addr, 111 unsigned size) 112 { 113 BostonState *s = opaque; 114 uint64_t val = 0; 115 116 switch (size) { 117 case 8: 118 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; 119 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; 120 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; 121 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; 122 /* fall through */ 123 case 4: 124 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; 125 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; 126 /* fall through */ 127 case 2: 128 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; 129 /* fall through */ 130 case 1: 131 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; 132 break; 133 } 134 135 return val; 136 } 137 138 static void boston_lcd_write(void *opaque, hwaddr addr, 139 uint64_t val, unsigned size) 140 { 141 BostonState *s = opaque; 142 143 switch (size) { 144 case 8: 145 s->lcd_content[(addr + 7) & 0x7] = val >> 56; 146 s->lcd_content[(addr + 6) & 0x7] = val >> 48; 147 s->lcd_content[(addr + 5) & 0x7] = val >> 40; 148 s->lcd_content[(addr + 4) & 0x7] = val >> 32; 149 /* fall through */ 150 case 4: 151 s->lcd_content[(addr + 3) & 0x7] = val >> 24; 152 s->lcd_content[(addr + 2) & 0x7] = val >> 16; 153 /* fall through */ 154 case 2: 155 s->lcd_content[(addr + 1) & 0x7] = val >> 8; 156 /* fall through */ 157 case 1: 158 s->lcd_content[(addr + 0) & 0x7] = val; 159 break; 160 } 161 162 qemu_chr_fe_printf(&s->lcd_display, 163 "\r%-8.8s", s->lcd_content); 164 } 165 166 static const MemoryRegionOps boston_lcd_ops = { 167 .read = boston_lcd_read, 168 .write = boston_lcd_write, 169 .endianness = DEVICE_NATIVE_ENDIAN, 170 }; 171 172 static uint64_t boston_platreg_read(void *opaque, hwaddr addr, 173 unsigned size) 174 { 175 BostonState *s = opaque; 176 uint32_t gic_freq, val; 177 178 if (size != 4) { 179 qemu_log_mask(LOG_UNIMP, "%uB platform register read", size); 180 return 0; 181 } 182 183 switch (addr & 0xffff) { 184 case PLAT_FPGA_BUILD: 185 case PLAT_CORE_CL: 186 case PLAT_WRAPPER_CL: 187 return 0; 188 case PLAT_DDR3_STATUS: 189 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; 190 case PLAT_MMCM_DIV: 191 gic_freq = mips_gictimer_get_freq(s->cps->gic.gic_timer) / 1000000; 192 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; 193 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; 194 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; 195 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; 196 return val; 197 case PLAT_BUILD_CFG: 198 val = PLAT_BUILD_CFG_PCIE0_EN; 199 val |= PLAT_BUILD_CFG_PCIE1_EN; 200 val |= PLAT_BUILD_CFG_PCIE2_EN; 201 return val; 202 case PLAT_DDR_CFG: 203 val = s->mach->ram_size / G_BYTE; 204 assert(!(val & ~PLAT_DDR_CFG_SIZE)); 205 val |= PLAT_DDR_CFG_MHZ; 206 return val; 207 default: 208 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx, 209 addr & 0xffff); 210 return 0; 211 } 212 } 213 214 static void boston_platreg_write(void *opaque, hwaddr addr, 215 uint64_t val, unsigned size) 216 { 217 if (size != 4) { 218 qemu_log_mask(LOG_UNIMP, "%uB platform register write", size); 219 return; 220 } 221 222 switch (addr & 0xffff) { 223 case PLAT_FPGA_BUILD: 224 case PLAT_CORE_CL: 225 case PLAT_WRAPPER_CL: 226 case PLAT_DDR3_STATUS: 227 case PLAT_PCIE_STATUS: 228 case PLAT_MMCM_DIV: 229 case PLAT_BUILD_CFG: 230 case PLAT_DDR_CFG: 231 /* read only */ 232 break; 233 case PLAT_SOFTRST_CTL: 234 if (val & PLAT_SOFTRST_CTL_SYSRESET) { 235 qemu_system_reset_request(); 236 } 237 break; 238 default: 239 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx 240 " = 0x%" PRIx64, addr & 0xffff, val); 241 break; 242 } 243 } 244 245 static const MemoryRegionOps boston_platreg_ops = { 246 .read = boston_platreg_read, 247 .write = boston_platreg_write, 248 .endianness = DEVICE_NATIVE_ENDIAN, 249 }; 250 251 static void boston_flash_write(void *opaque, hwaddr addr, 252 uint64_t val, unsigned size) 253 { 254 } 255 256 static const MemoryRegionOps boston_flash_ops = { 257 .write = boston_flash_write, 258 .endianness = DEVICE_NATIVE_ENDIAN, 259 }; 260 261 static const TypeInfo boston_device = { 262 .name = TYPE_MIPS_BOSTON, 263 .parent = TYPE_SYS_BUS_DEVICE, 264 .instance_size = sizeof(BostonState), 265 }; 266 267 static void boston_register_types(void) 268 { 269 type_register_static(&boston_device); 270 } 271 type_init(boston_register_types) 272 273 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, 274 bool is_64b) 275 { 276 const uint32_t cm_base = 0x16100000; 277 const uint32_t gic_base = 0x16120000; 278 const uint32_t cpc_base = 0x16200000; 279 280 /* Move CM GCRs */ 281 if (is_64b) { 282 stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ 283 stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ 284 } else { 285 stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ 286 stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ 287 } 288 stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ 289 stl_p(p++, 0x01094025); /* or $8, $9 */ 290 stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ 291 if (is_64b) { 292 stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ 293 } else { 294 stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ 295 } 296 stl_p(p++, 0x012a4025); /* or $8, $10 */ 297 298 /* Move & enable GIC GCRs */ 299 stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ 300 stl_p(p++, 0x35290001); /* ori $9, 0x1 */ 301 if (is_64b) { 302 stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ 303 } else { 304 stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ 305 } 306 307 /* Move & enable CPC GCRs */ 308 stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ 309 stl_p(p++, 0x35290001); /* ori $9, 0x1 */ 310 if (is_64b) { 311 stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ 312 } else { 313 stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ 314 } 315 316 /* 317 * Setup argument registers to follow the UHI boot protocol: 318 * 319 * a0/$4 = -2 320 * a1/$5 = virtual address of FDT 321 * a2/$6 = 0 322 * a3/$7 = 0 323 */ 324 stl_p(p++, 0x2404fffe); /* li $4, -2 */ 325 /* lui $5, hi(fdt_addr) */ 326 stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); 327 if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ 328 stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); 329 } 330 stl_p(p++, 0x34060000); /* li $6, 0 */ 331 stl_p(p++, 0x34070000); /* li $7, 0 */ 332 333 /* Load kernel entry address & jump to it */ 334 /* lui $25, hi(kernel_entry) */ 335 stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); 336 /* ori $25, lo(kernel_entry) */ 337 stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); 338 stl_p(p++, 0x03200009); /* jr $25 */ 339 } 340 341 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, 342 const void *match_data, hwaddr *load_addr) 343 { 344 BostonState *s = BOSTON(opaque); 345 MachineState *machine = s->mach; 346 const char *cmdline; 347 int err; 348 void *fdt; 349 size_t fdt_sz, ram_low_sz, ram_high_sz; 350 351 fdt_sz = fdt_totalsize(fdt_orig) * 2; 352 fdt = g_malloc0(fdt_sz); 353 354 err = fdt_open_into(fdt_orig, fdt, fdt_sz); 355 if (err) { 356 fprintf(stderr, "unable to open FDT\n"); 357 return NULL; 358 } 359 360 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) 361 ? machine->kernel_cmdline : " "; 362 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 363 if (err < 0) { 364 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 365 return NULL; 366 } 367 368 ram_low_sz = MIN(256 * M_BYTE, machine->ram_size); 369 ram_high_sz = machine->ram_size - ram_low_sz; 370 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", 371 1, 0x00000000, 1, ram_low_sz, 372 1, 0x90000000, 1, ram_high_sz); 373 374 fdt = g_realloc(fdt, fdt_totalsize(fdt)); 375 qemu_fdt_dumpdtb(fdt, fdt_sz); 376 377 s->fdt_base = *load_addr; 378 379 return fdt; 380 } 381 382 static const void *boston_kernel_filter(void *opaque, const void *kernel, 383 hwaddr *load_addr, hwaddr *entry_addr) 384 { 385 BostonState *s = BOSTON(opaque); 386 387 s->kernel_entry = *entry_addr; 388 389 return kernel; 390 } 391 392 static const struct fit_loader_match boston_matches[] = { 393 { "img,boston" }, 394 { NULL }, 395 }; 396 397 static const struct fit_loader boston_fit_loader = { 398 .matches = boston_matches, 399 .addr_to_phys = cpu_mips_kseg0_to_phys, 400 .fdt_filter = boston_fdt_filter, 401 .kernel_filter = boston_kernel_filter, 402 }; 403 404 static inline XilinxPCIEHost * 405 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, 406 hwaddr cfg_base, uint64_t cfg_size, 407 hwaddr mmio_base, uint64_t mmio_size, 408 qemu_irq irq, bool link_up) 409 { 410 DeviceState *dev; 411 MemoryRegion *cfg, *mmio; 412 413 dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); 414 415 qdev_prop_set_uint32(dev, "bus_nr", bus_nr); 416 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); 417 qdev_prop_set_uint64(dev, "cfg_size", cfg_size); 418 qdev_prop_set_uint64(dev, "mmio_base", mmio_base); 419 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 420 qdev_prop_set_bit(dev, "link_up", link_up); 421 422 qdev_init_nofail(dev); 423 424 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 425 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); 426 427 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 428 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); 429 430 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); 431 432 return XILINX_PCIE_HOST(dev); 433 } 434 435 static void boston_mach_init(MachineState *machine) 436 { 437 DeviceState *dev; 438 BostonState *s; 439 Error *err = NULL; 440 const char *cpu_model; 441 MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; 442 MemoryRegion *sys_mem = get_system_memory(); 443 XilinxPCIEHost *pcie2; 444 PCIDevice *ahci; 445 DriveInfo *hd[6]; 446 Chardev *chr; 447 int fw_size, fit_err; 448 bool is_64b; 449 450 if ((machine->ram_size % G_BYTE) || 451 (machine->ram_size > (2 * G_BYTE))) { 452 error_report("Memory size must be 1GB or 2GB"); 453 exit(1); 454 } 455 456 cpu_model = machine->cpu_model ?: "I6400"; 457 458 dev = qdev_create(NULL, TYPE_MIPS_BOSTON); 459 qdev_init_nofail(dev); 460 461 s = BOSTON(dev); 462 s->mach = machine; 463 s->cps = g_new0(MIPSCPSState, 1); 464 465 if (!cpu_supports_cps_smp(cpu_model)) { 466 error_report("Boston requires CPUs which support CPS"); 467 exit(1); 468 } 469 470 is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64); 471 472 object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS); 473 qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); 474 475 object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err); 476 object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); 477 object_property_set_bool(OBJECT(s->cps), true, "realized", &err); 478 479 if (err != NULL) { 480 error_report("%s", error_get_pretty(err)); 481 exit(1); 482 } 483 484 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); 485 486 flash = g_new(MemoryRegion, 1); 487 memory_region_init_rom_device(flash, NULL, &boston_flash_ops, s, 488 "boston.flash", 128 * M_BYTE, &err); 489 memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); 490 491 ddr = g_new(MemoryRegion, 1); 492 memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", 493 machine->ram_size); 494 memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); 495 496 ddr_low_alias = g_new(MemoryRegion, 1); 497 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", 498 ddr, 0, MIN(machine->ram_size, (256 * M_BYTE))); 499 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); 500 501 xilinx_pcie_init(sys_mem, 0, 502 0x10000000, 32 * M_BYTE, 503 0x40000000, 1 * G_BYTE, 504 get_cps_irq(s->cps, 2), false); 505 506 xilinx_pcie_init(sys_mem, 1, 507 0x12000000, 32 * M_BYTE, 508 0x20000000, 512 * M_BYTE, 509 get_cps_irq(s->cps, 1), false); 510 511 pcie2 = xilinx_pcie_init(sys_mem, 2, 512 0x14000000, 32 * M_BYTE, 513 0x16000000, 1 * M_BYTE, 514 get_cps_irq(s->cps, 0), true); 515 516 platreg = g_new(MemoryRegion, 1); 517 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, 518 "boston-platregs", 0x1000); 519 memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); 520 521 if (!serial_hds[0]) { 522 serial_hds[0] = qemu_chr_new("serial0", "null"); 523 } 524 525 s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, 526 get_cps_irq(s->cps, 3), 10000000, 527 serial_hds[0], DEVICE_NATIVE_ENDIAN); 528 529 lcd = g_new(MemoryRegion, 1); 530 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); 531 memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); 532 533 chr = qemu_chr_new("lcd", "vc:320x240"); 534 qemu_chr_fe_init(&s->lcd_display, chr, NULL); 535 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, 536 boston_lcd_event, s, NULL, true); 537 538 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, 539 PCI_DEVFN(0, 0), 540 true, TYPE_ICH9_AHCI); 541 g_assert(ARRAY_SIZE(hd) == ICH_AHCI(ahci)->ahci.ports); 542 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 543 ahci_ide_create_devs(ahci, hd); 544 545 if (machine->firmware) { 546 fw_size = load_image_targphys(machine->firmware, 547 0x1fc00000, 4 * M_BYTE); 548 if (fw_size == -1) { 549 error_printf("unable to load firmware image '%s'\n", 550 machine->firmware); 551 exit(1); 552 } 553 } else if (machine->kernel_filename) { 554 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); 555 if (fit_err) { 556 error_printf("unable to load FIT image\n"); 557 exit(1); 558 } 559 560 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, 561 s->kernel_entry, s->fdt_base, is_64b); 562 } else if (!qtest_enabled()) { 563 error_printf("Please provide either a -kernel or -bios argument\n"); 564 exit(1); 565 } 566 } 567 568 static void boston_mach_class_init(MachineClass *mc) 569 { 570 mc->desc = "MIPS Boston"; 571 mc->init = boston_mach_init; 572 mc->block_default_type = IF_IDE; 573 mc->default_ram_size = 1 * G_BYTE; 574 mc->max_cpus = 16; 575 } 576 577 DEFINE_MACHINE("boston", boston_mach_class_init) 578