1 /* 2 * MIPS Boston development board emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 23 #include "elf.h" 24 #include "hw/boards.h" 25 #include "hw/char/serial.h" 26 #include "hw/ide/pci.h" 27 #include "hw/ide/ahci.h" 28 #include "hw/loader.h" 29 #include "hw/loader-fit.h" 30 #include "hw/mips/bootloader.h" 31 #include "hw/mips/cps.h" 32 #include "hw/pci-host/xilinx-pcie.h" 33 #include "hw/qdev-clock.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 #include "qemu/error-report.h" 37 #include "qemu/guest-random.h" 38 #include "qemu/log.h" 39 #include "chardev/char.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/sysemu.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/runstate.h" 44 45 #include <libfdt.h> 46 #include "qom/object.h" 47 48 #define TYPE_BOSTON "mips-boston" 49 typedef struct BostonState BostonState; 50 DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, 51 TYPE_BOSTON) 52 53 #define FDT_IRQ_TYPE_NONE 0 54 #define FDT_IRQ_TYPE_LEVEL_HIGH 4 55 #define FDT_GIC_SHARED 0 56 #define FDT_GIC_LOCAL 1 57 #define FDT_BOSTON_CLK_SYS 1 58 #define FDT_BOSTON_CLK_CPU 2 59 #define FDT_PCI_IRQ_MAP_PINS 4 60 #define FDT_PCI_IRQ_MAP_DESCS 6 61 62 struct BostonState { 63 SysBusDevice parent_obj; 64 65 MachineState *mach; 66 MIPSCPSState cps; 67 SerialMM *uart; 68 Clock *cpuclk; 69 70 CharBackend lcd_display; 71 char lcd_content[8]; 72 bool lcd_inited; 73 74 hwaddr kernel_entry; 75 hwaddr fdt_base; 76 }; 77 78 enum { 79 BOSTON_LOWDDR, 80 BOSTON_PCIE0, 81 BOSTON_PCIE1, 82 BOSTON_PCIE2, 83 BOSTON_PCIE2_MMIO, 84 BOSTON_CM, 85 BOSTON_GIC, 86 BOSTON_CDMM, 87 BOSTON_CPC, 88 BOSTON_PLATREG, 89 BOSTON_UART, 90 BOSTON_LCD, 91 BOSTON_FLASH, 92 BOSTON_PCIE1_MMIO, 93 BOSTON_PCIE0_MMIO, 94 BOSTON_HIGHDDR, 95 }; 96 97 static const MemMapEntry boston_memmap[] = { 98 [BOSTON_LOWDDR] = { 0x0, 0x10000000 }, 99 [BOSTON_PCIE0] = { 0x10000000, 0x2000000 }, 100 [BOSTON_PCIE1] = { 0x12000000, 0x2000000 }, 101 [BOSTON_PCIE2] = { 0x14000000, 0x2000000 }, 102 [BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 }, 103 [BOSTON_CM] = { 0x16100000, 0x20000 }, 104 [BOSTON_GIC] = { 0x16120000, 0x20000 }, 105 [BOSTON_CDMM] = { 0x16140000, 0x8000 }, 106 [BOSTON_CPC] = { 0x16200000, 0x8000 }, 107 [BOSTON_PLATREG] = { 0x17ffd000, 0x1000 }, 108 [BOSTON_UART] = { 0x17ffe000, 0x20 }, 109 [BOSTON_LCD] = { 0x17fff000, 0x8 }, 110 [BOSTON_FLASH] = { 0x18000000, 0x8000000 }, 111 [BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 }, 112 [BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 }, 113 [BOSTON_HIGHDDR] = { 0x80000000, 0x0 }, 114 }; 115 116 enum boston_plat_reg { 117 PLAT_FPGA_BUILD = 0x00, 118 PLAT_CORE_CL = 0x04, 119 PLAT_WRAPPER_CL = 0x08, 120 PLAT_SYSCLK_STATUS = 0x0c, 121 PLAT_SOFTRST_CTL = 0x10, 122 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) 123 PLAT_DDR3_STATUS = 0x14, 124 #define PLAT_DDR3_STATUS_LOCKED (1 << 0) 125 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) 126 PLAT_PCIE_STATUS = 0x18, 127 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) 128 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) 129 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) 130 PLAT_FLASH_CTL = 0x1c, 131 PLAT_SPARE0 = 0x20, 132 PLAT_SPARE1 = 0x24, 133 PLAT_SPARE2 = 0x28, 134 PLAT_SPARE3 = 0x2c, 135 PLAT_MMCM_DIV = 0x30, 136 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 137 #define PLAT_MMCM_DIV_INPUT_SHIFT 8 138 #define PLAT_MMCM_DIV_MUL_SHIFT 16 139 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 140 PLAT_BUILD_CFG = 0x34, 141 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) 142 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) 143 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) 144 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) 145 PLAT_DDR_CFG = 0x38, 146 #define PLAT_DDR_CFG_SIZE (0xf << 0) 147 #define PLAT_DDR_CFG_MHZ (0xfff << 4) 148 PLAT_NOC_PCIE0_ADDR = 0x3c, 149 PLAT_NOC_PCIE1_ADDR = 0x40, 150 PLAT_NOC_PCIE2_ADDR = 0x44, 151 PLAT_SYS_CTL = 0x48, 152 }; 153 154 static void boston_lcd_event(void *opaque, QEMUChrEvent event) 155 { 156 BostonState *s = opaque; 157 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { 158 qemu_chr_fe_printf(&s->lcd_display, " "); 159 s->lcd_inited = true; 160 } 161 } 162 163 static uint64_t boston_lcd_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 BostonState *s = opaque; 167 uint64_t val = 0; 168 169 switch (size) { 170 case 8: 171 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; 172 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; 173 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; 174 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; 175 /* fall through */ 176 case 4: 177 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; 178 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; 179 /* fall through */ 180 case 2: 181 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; 182 /* fall through */ 183 case 1: 184 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; 185 break; 186 } 187 188 return val; 189 } 190 191 static void boston_lcd_write(void *opaque, hwaddr addr, 192 uint64_t val, unsigned size) 193 { 194 BostonState *s = opaque; 195 196 switch (size) { 197 case 8: 198 s->lcd_content[(addr + 7) & 0x7] = val >> 56; 199 s->lcd_content[(addr + 6) & 0x7] = val >> 48; 200 s->lcd_content[(addr + 5) & 0x7] = val >> 40; 201 s->lcd_content[(addr + 4) & 0x7] = val >> 32; 202 /* fall through */ 203 case 4: 204 s->lcd_content[(addr + 3) & 0x7] = val >> 24; 205 s->lcd_content[(addr + 2) & 0x7] = val >> 16; 206 /* fall through */ 207 case 2: 208 s->lcd_content[(addr + 1) & 0x7] = val >> 8; 209 /* fall through */ 210 case 1: 211 s->lcd_content[(addr + 0) & 0x7] = val; 212 break; 213 } 214 215 qemu_chr_fe_printf(&s->lcd_display, 216 "\r%-8.8s", s->lcd_content); 217 } 218 219 static const MemoryRegionOps boston_lcd_ops = { 220 .read = boston_lcd_read, 221 .write = boston_lcd_write, 222 .endianness = DEVICE_NATIVE_ENDIAN, 223 }; 224 225 static uint64_t boston_platreg_read(void *opaque, hwaddr addr, 226 unsigned size) 227 { 228 BostonState *s = opaque; 229 uint32_t gic_freq, val; 230 231 if (size != 4) { 232 qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); 233 return 0; 234 } 235 236 switch (addr & 0xffff) { 237 case PLAT_FPGA_BUILD: 238 case PLAT_CORE_CL: 239 case PLAT_WRAPPER_CL: 240 return 0; 241 case PLAT_DDR3_STATUS: 242 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; 243 case PLAT_MMCM_DIV: 244 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; 245 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; 246 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; 247 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; 248 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; 249 return val; 250 case PLAT_BUILD_CFG: 251 val = PLAT_BUILD_CFG_PCIE0_EN; 252 val |= PLAT_BUILD_CFG_PCIE1_EN; 253 val |= PLAT_BUILD_CFG_PCIE2_EN; 254 return val; 255 case PLAT_DDR_CFG: 256 val = s->mach->ram_size / GiB; 257 assert(!(val & ~PLAT_DDR_CFG_SIZE)); 258 val |= PLAT_DDR_CFG_MHZ; 259 return val; 260 default: 261 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", 262 addr & 0xffff); 263 return 0; 264 } 265 } 266 267 static void boston_platreg_write(void *opaque, hwaddr addr, 268 uint64_t val, unsigned size) 269 { 270 if (size != 4) { 271 qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); 272 return; 273 } 274 275 switch (addr & 0xffff) { 276 case PLAT_FPGA_BUILD: 277 case PLAT_CORE_CL: 278 case PLAT_WRAPPER_CL: 279 case PLAT_DDR3_STATUS: 280 case PLAT_PCIE_STATUS: 281 case PLAT_MMCM_DIV: 282 case PLAT_BUILD_CFG: 283 case PLAT_DDR_CFG: 284 /* read only */ 285 break; 286 case PLAT_SOFTRST_CTL: 287 if (val & PLAT_SOFTRST_CTL_SYSRESET) { 288 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 289 } 290 break; 291 default: 292 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx 293 " = 0x%" PRIx64 "\n", addr & 0xffff, val); 294 break; 295 } 296 } 297 298 static const MemoryRegionOps boston_platreg_ops = { 299 .read = boston_platreg_read, 300 .write = boston_platreg_write, 301 .endianness = DEVICE_NATIVE_ENDIAN, 302 }; 303 304 static void mips_boston_instance_init(Object *obj) 305 { 306 BostonState *s = BOSTON(obj); 307 308 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 309 clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ 310 } 311 312 static const TypeInfo boston_device = { 313 .name = TYPE_BOSTON, 314 .parent = TYPE_SYS_BUS_DEVICE, 315 .instance_size = sizeof(BostonState), 316 .instance_init = mips_boston_instance_init, 317 }; 318 319 static void boston_register_types(void) 320 { 321 type_register_static(&boston_device); 322 } 323 type_init(boston_register_types) 324 325 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr) 326 { 327 uint64_t regaddr; 328 329 /* Move CM GCRs */ 330 regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), 331 bl_gen_write_ulong(&p, regaddr, 332 boston_memmap[BOSTON_CM].base); 333 334 /* Move & enable GIC GCRs */ 335 regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base 336 + GCR_GIC_BASE_OFS), 337 bl_gen_write_ulong(&p, regaddr, 338 boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); 339 340 /* Move & enable CPC GCRs */ 341 regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base 342 + GCR_CPC_BASE_OFS), 343 bl_gen_write_ulong(&p, regaddr, 344 boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); 345 346 /* 347 * Setup argument registers to follow the UHI boot protocol: 348 * 349 * a0/$4 = -2 350 * a1/$5 = virtual address of FDT 351 * a2/$6 = 0 352 * a3/$7 = 0 353 */ 354 bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry); 355 } 356 357 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, 358 const void *match_data, hwaddr *load_addr) 359 { 360 BostonState *s = BOSTON(opaque); 361 MachineState *machine = s->mach; 362 const char *cmdline; 363 int err; 364 size_t ram_low_sz, ram_high_sz; 365 size_t fdt_sz = fdt_totalsize(fdt_orig) * 2; 366 g_autofree void *fdt = g_malloc0(fdt_sz); 367 uint8_t rng_seed[32]; 368 369 err = fdt_open_into(fdt_orig, fdt, fdt_sz); 370 if (err) { 371 fprintf(stderr, "unable to open FDT\n"); 372 return NULL; 373 } 374 375 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 376 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 377 378 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) 379 ? machine->kernel_cmdline : " "; 380 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 381 if (err < 0) { 382 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 383 return NULL; 384 } 385 386 ram_low_sz = MIN(256 * MiB, machine->ram_size); 387 ram_high_sz = machine->ram_size - ram_low_sz; 388 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", 389 1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz, 390 1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz, 391 1, ram_high_sz); 392 393 fdt = g_realloc(fdt, fdt_totalsize(fdt)); 394 qemu_fdt_dumpdtb(fdt, fdt_sz); 395 396 s->fdt_base = *load_addr; 397 398 return g_steal_pointer(&fdt); 399 } 400 401 static const void *boston_kernel_filter(void *opaque, const void *kernel, 402 hwaddr *load_addr, hwaddr *entry_addr) 403 { 404 BostonState *s = BOSTON(opaque); 405 406 s->kernel_entry = *entry_addr; 407 408 return kernel; 409 } 410 411 static const struct fit_loader_match boston_matches[] = { 412 { "img,boston" }, 413 { NULL }, 414 }; 415 416 static const struct fit_loader boston_fit_loader = { 417 .matches = boston_matches, 418 .addr_to_phys = cpu_mips_kseg0_to_phys, 419 .fdt_filter = boston_fdt_filter, 420 .kernel_filter = boston_kernel_filter, 421 }; 422 423 static inline XilinxPCIEHost * 424 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, 425 hwaddr cfg_base, uint64_t cfg_size, 426 hwaddr mmio_base, uint64_t mmio_size, 427 qemu_irq irq, bool link_up) 428 { 429 DeviceState *dev; 430 MemoryRegion *cfg, *mmio; 431 432 dev = qdev_new(TYPE_XILINX_PCIE_HOST); 433 434 qdev_prop_set_uint32(dev, "bus_nr", bus_nr); 435 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); 436 qdev_prop_set_uint64(dev, "cfg_size", cfg_size); 437 qdev_prop_set_uint64(dev, "mmio_base", mmio_base); 438 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 439 qdev_prop_set_bit(dev, "link_up", link_up); 440 441 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 442 443 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 444 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); 445 446 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 447 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); 448 449 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); 450 451 return XILINX_PCIE_HOST(dev); 452 } 453 454 455 static void fdt_create_pcie(void *fdt, int gic_ph, int irq, hwaddr reg_base, 456 hwaddr reg_size, hwaddr mmio_base, hwaddr mmio_size) 457 { 458 int i; 459 char *name, *intc_name; 460 uint32_t intc_ph; 461 uint32_t interrupt_map[FDT_PCI_IRQ_MAP_PINS][FDT_PCI_IRQ_MAP_DESCS]; 462 463 intc_ph = qemu_fdt_alloc_phandle(fdt); 464 name = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, reg_base); 465 qemu_fdt_add_subnode(fdt, name); 466 qemu_fdt_setprop_string(fdt, name, "compatible", 467 "xlnx,axi-pcie-host-1.00.a"); 468 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 469 qemu_fdt_setprop_cells(fdt, name, "reg", reg_base, reg_size); 470 471 qemu_fdt_setprop_cell(fdt, name, "#address-cells", 3); 472 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 2); 473 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 1); 474 475 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); 476 qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, irq, 477 FDT_IRQ_TYPE_LEVEL_HIGH); 478 479 qemu_fdt_setprop_cells(fdt, name, "ranges", 0x02000000, 0, mmio_base, 480 mmio_base, 0, mmio_size); 481 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0x00, 0xff); 482 483 484 485 intc_name = g_strdup_printf("%s/interrupt-controller", name); 486 qemu_fdt_add_subnode(fdt, intc_name); 487 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 488 qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0); 489 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 490 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_ph); 491 492 qemu_fdt_setprop_cells(fdt, name, "interrupt-map-mask", 0, 0, 0, 7); 493 for (i = 0; i < FDT_PCI_IRQ_MAP_PINS; i++) { 494 uint32_t *irqmap = interrupt_map[i]; 495 496 irqmap[0] = cpu_to_be32(0); 497 irqmap[1] = cpu_to_be32(0); 498 irqmap[2] = cpu_to_be32(0); 499 irqmap[3] = cpu_to_be32(i + 1); 500 irqmap[4] = cpu_to_be32(intc_ph); 501 irqmap[5] = cpu_to_be32(i + 1); 502 } 503 qemu_fdt_setprop(fdt, name, "interrupt-map", 504 &interrupt_map, sizeof(interrupt_map)); 505 506 g_free(intc_name); 507 g_free(name); 508 } 509 510 static const void *create_fdt(BostonState *s, 511 const MemMapEntry *memmap, int *dt_size) 512 { 513 void *fdt; 514 int cpu; 515 MachineState *mc = s->mach; 516 uint32_t platreg_ph, gic_ph, clk_ph; 517 char *name, *gic_name, *platreg_name, *stdout_name; 518 static const char * const syscon_compat[2] = { 519 "img,boston-platform-regs", "syscon" 520 }; 521 522 fdt = create_device_tree(dt_size); 523 if (!fdt) { 524 error_report("create_device_tree() failed"); 525 exit(1); 526 } 527 528 platreg_ph = qemu_fdt_alloc_phandle(fdt); 529 gic_ph = qemu_fdt_alloc_phandle(fdt); 530 clk_ph = qemu_fdt_alloc_phandle(fdt); 531 532 qemu_fdt_setprop_string(fdt, "/", "model", "img,boston"); 533 qemu_fdt_setprop_string(fdt, "/", "compatible", "img,boston"); 534 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); 535 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); 536 537 538 qemu_fdt_add_subnode(fdt, "/cpus"); 539 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 540 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 541 542 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 543 name = g_strdup_printf("/cpus/cpu@%d", cpu); 544 qemu_fdt_add_subnode(fdt, name); 545 qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips"); 546 qemu_fdt_setprop_string(fdt, name, "status", "okay"); 547 qemu_fdt_setprop_cell(fdt, name, "reg", cpu); 548 qemu_fdt_setprop_string(fdt, name, "device_type", "cpu"); 549 qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU); 550 g_free(name); 551 } 552 553 qemu_fdt_add_subnode(fdt, "/soc"); 554 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 555 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 556 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); 557 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1); 558 559 fdt_create_pcie(fdt, gic_ph, 2, 560 memmap[BOSTON_PCIE0].base, memmap[BOSTON_PCIE0].size, 561 memmap[BOSTON_PCIE0_MMIO].base, memmap[BOSTON_PCIE0_MMIO].size); 562 563 fdt_create_pcie(fdt, gic_ph, 1, 564 memmap[BOSTON_PCIE1].base, memmap[BOSTON_PCIE1].size, 565 memmap[BOSTON_PCIE1_MMIO].base, memmap[BOSTON_PCIE1_MMIO].size); 566 567 fdt_create_pcie(fdt, gic_ph, 0, 568 memmap[BOSTON_PCIE2].base, memmap[BOSTON_PCIE2].size, 569 memmap[BOSTON_PCIE2_MMIO].base, memmap[BOSTON_PCIE2_MMIO].size); 570 571 /* GIC with it's timer node */ 572 gic_name = g_strdup_printf("/soc/interrupt-controller@%" HWADDR_PRIx, 573 memmap[BOSTON_GIC].base); 574 qemu_fdt_add_subnode(fdt, gic_name); 575 qemu_fdt_setprop_string(fdt, gic_name, "compatible", "mti,gic"); 576 qemu_fdt_setprop_cells(fdt, gic_name, "reg", memmap[BOSTON_GIC].base, 577 memmap[BOSTON_GIC].size); 578 qemu_fdt_setprop(fdt, gic_name, "interrupt-controller", NULL, 0); 579 qemu_fdt_setprop_cell(fdt, gic_name, "#interrupt-cells", 3); 580 qemu_fdt_setprop_cell(fdt, gic_name, "phandle", gic_ph); 581 582 name = g_strdup_printf("%s/timer", gic_name); 583 qemu_fdt_add_subnode(fdt, name); 584 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,gic-timer"); 585 qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_LOCAL, 1, 586 FDT_IRQ_TYPE_NONE); 587 qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU); 588 g_free(name); 589 g_free(gic_name); 590 591 /* CDMM node */ 592 name = g_strdup_printf("/soc/cdmm@%" HWADDR_PRIx, memmap[BOSTON_CDMM].base); 593 qemu_fdt_add_subnode(fdt, name); 594 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cdmm"); 595 qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CDMM].base, 596 memmap[BOSTON_CDMM].size); 597 g_free(name); 598 599 /* CPC node */ 600 name = g_strdup_printf("/soc/cpc@%" HWADDR_PRIx, memmap[BOSTON_CPC].base); 601 qemu_fdt_add_subnode(fdt, name); 602 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cpc"); 603 qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CPC].base, 604 memmap[BOSTON_CPC].size); 605 g_free(name); 606 607 /* platreg and it's clk node */ 608 platreg_name = g_strdup_printf("/soc/system-controller@%" HWADDR_PRIx, 609 memmap[BOSTON_PLATREG].base); 610 qemu_fdt_add_subnode(fdt, platreg_name); 611 qemu_fdt_setprop_string_array(fdt, platreg_name, "compatible", 612 (char **)&syscon_compat, 613 ARRAY_SIZE(syscon_compat)); 614 qemu_fdt_setprop_cells(fdt, platreg_name, "reg", 615 memmap[BOSTON_PLATREG].base, 616 memmap[BOSTON_PLATREG].size); 617 qemu_fdt_setprop_cell(fdt, platreg_name, "phandle", platreg_ph); 618 619 name = g_strdup_printf("%s/clock", platreg_name); 620 qemu_fdt_add_subnode(fdt, name); 621 qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-clock"); 622 qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); 623 qemu_fdt_setprop_cell(fdt, name, "phandle", clk_ph); 624 g_free(name); 625 g_free(platreg_name); 626 627 /* reboot node */ 628 name = g_strdup_printf("/soc/reboot"); 629 qemu_fdt_add_subnode(fdt, name); 630 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 631 qemu_fdt_setprop_cell(fdt, name, "regmap", platreg_ph); 632 qemu_fdt_setprop_cell(fdt, name, "offset", 0x10); 633 qemu_fdt_setprop_cell(fdt, name, "mask", 0x10); 634 g_free(name); 635 636 /* uart node */ 637 name = g_strdup_printf("/soc/uart@%" HWADDR_PRIx, memmap[BOSTON_UART].base); 638 qemu_fdt_add_subnode(fdt, name); 639 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 640 qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_UART].base, 641 memmap[BOSTON_UART].size); 642 qemu_fdt_setprop_cell(fdt, name, "reg-shift", 0x2); 643 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); 644 qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, 3, 645 FDT_IRQ_TYPE_LEVEL_HIGH); 646 qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_SYS); 647 648 qemu_fdt_add_subnode(fdt, "/chosen"); 649 stdout_name = g_strdup_printf("%s:115200", name); 650 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", stdout_name); 651 g_free(stdout_name); 652 g_free(name); 653 654 /* lcd node */ 655 name = g_strdup_printf("/soc/lcd@%" HWADDR_PRIx, memmap[BOSTON_LCD].base); 656 qemu_fdt_add_subnode(fdt, name); 657 qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-lcd"); 658 qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_LCD].base, 659 memmap[BOSTON_LCD].size); 660 g_free(name); 661 662 name = g_strdup_printf("/memory@0"); 663 qemu_fdt_add_subnode(fdt, name); 664 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 665 g_free(name); 666 667 return fdt; 668 } 669 670 static void boston_mach_init(MachineState *machine) 671 { 672 DeviceState *dev; 673 BostonState *s; 674 MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; 675 MemoryRegion *sys_mem = get_system_memory(); 676 XilinxPCIEHost *pcie2; 677 PCIDevice *ahci; 678 DriveInfo *hd[6]; 679 Chardev *chr; 680 int fw_size, fit_err; 681 682 if ((machine->ram_size % GiB) || 683 (machine->ram_size > (2 * GiB))) { 684 error_report("Memory size must be 1GB or 2GB"); 685 exit(1); 686 } 687 688 dev = qdev_new(TYPE_BOSTON); 689 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 690 691 s = BOSTON(dev); 692 s->mach = machine; 693 694 if (!cpu_type_supports_cps_smp(machine->cpu_type)) { 695 error_report("Boston requires CPUs which support CPS"); 696 exit(1); 697 } 698 699 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); 700 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, 701 &error_fatal); 702 object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, 703 &error_fatal); 704 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", 705 qdev_get_clock_out(dev, "cpu-refclk")); 706 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 707 708 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 709 710 flash = g_new(MemoryRegion, 1); 711 memory_region_init_rom(flash, NULL, "boston.flash", 712 boston_memmap[BOSTON_FLASH].size, &error_fatal); 713 memory_region_add_subregion_overlap(sys_mem, 714 boston_memmap[BOSTON_FLASH].base, 715 flash, 0); 716 717 memory_region_add_subregion_overlap(sys_mem, 718 boston_memmap[BOSTON_HIGHDDR].base, 719 machine->ram, 0); 720 721 ddr_low_alias = g_new(MemoryRegion, 1); 722 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", 723 machine->ram, 0, 724 MIN(machine->ram_size, (256 * MiB))); 725 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); 726 727 xilinx_pcie_init(sys_mem, 0, 728 boston_memmap[BOSTON_PCIE0].base, 729 boston_memmap[BOSTON_PCIE0].size, 730 boston_memmap[BOSTON_PCIE0_MMIO].base, 731 boston_memmap[BOSTON_PCIE0_MMIO].size, 732 get_cps_irq(&s->cps, 2), false); 733 734 xilinx_pcie_init(sys_mem, 1, 735 boston_memmap[BOSTON_PCIE1].base, 736 boston_memmap[BOSTON_PCIE1].size, 737 boston_memmap[BOSTON_PCIE1_MMIO].base, 738 boston_memmap[BOSTON_PCIE1_MMIO].size, 739 get_cps_irq(&s->cps, 1), false); 740 741 pcie2 = xilinx_pcie_init(sys_mem, 2, 742 boston_memmap[BOSTON_PCIE2].base, 743 boston_memmap[BOSTON_PCIE2].size, 744 boston_memmap[BOSTON_PCIE2_MMIO].base, 745 boston_memmap[BOSTON_PCIE2_MMIO].size, 746 get_cps_irq(&s->cps, 0), true); 747 748 platreg = g_new(MemoryRegion, 1); 749 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, 750 "boston-platregs", 751 boston_memmap[BOSTON_PLATREG].size); 752 memory_region_add_subregion_overlap(sys_mem, 753 boston_memmap[BOSTON_PLATREG].base, platreg, 0); 754 755 s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2, 756 get_cps_irq(&s->cps, 3), 10000000, 757 serial_hd(0), DEVICE_NATIVE_ENDIAN); 758 759 lcd = g_new(MemoryRegion, 1); 760 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); 761 memory_region_add_subregion_overlap(sys_mem, 762 boston_memmap[BOSTON_LCD].base, lcd, 0); 763 764 chr = qemu_chr_new("lcd", "vc:320x240", NULL); 765 qemu_chr_fe_init(&s->lcd_display, chr, NULL); 766 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, 767 boston_lcd_event, NULL, s, NULL, true); 768 769 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, 770 PCI_DEVFN(0, 0), 771 true, TYPE_ICH9_AHCI); 772 g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); 773 ide_drive_get(hd, ahci_get_num_ports(ahci)); 774 ahci_ide_create_devs(ahci, hd); 775 776 if (machine->firmware) { 777 fw_size = load_image_targphys(machine->firmware, 778 0x1fc00000, 4 * MiB); 779 if (fw_size == -1) { 780 error_report("unable to load firmware image '%s'", 781 machine->firmware); 782 exit(1); 783 } 784 } else if (machine->kernel_filename) { 785 uint64_t kernel_entry, kernel_high; 786 ssize_t kernel_size; 787 788 kernel_size = load_elf(machine->kernel_filename, NULL, 789 cpu_mips_kseg0_to_phys, NULL, 790 &kernel_entry, NULL, &kernel_high, 791 NULL, 0, EM_MIPS, 1, 0); 792 793 if (kernel_size > 0) { 794 int dt_size; 795 g_autofree const void *dtb_file_data = NULL; 796 g_autofree const void *dtb_load_data = NULL; 797 hwaddr dtb_paddr = QEMU_ALIGN_UP(kernel_high, 64 * KiB); 798 hwaddr dtb_vaddr = cpu_mips_phys_to_kseg0(NULL, dtb_paddr); 799 800 s->kernel_entry = kernel_entry; 801 if (machine->dtb) { 802 dtb_file_data = load_device_tree(machine->dtb, &dt_size); 803 } else { 804 dtb_file_data = create_fdt(s, boston_memmap, &dt_size); 805 } 806 807 dtb_load_data = boston_fdt_filter(s, dtb_file_data, 808 NULL, &dtb_vaddr); 809 810 /* Calculate real fdt size after filter */ 811 dt_size = fdt_totalsize(dtb_load_data); 812 rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_paddr); 813 } else { 814 /* Try to load file as FIT */ 815 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); 816 if (fit_err) { 817 error_report("unable to load kernel image"); 818 exit(1); 819 } 820 } 821 822 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, 823 s->kernel_entry, s->fdt_base); 824 } else if (!qtest_enabled()) { 825 error_report("Please provide either a -kernel or -bios argument"); 826 exit(1); 827 } 828 } 829 830 static void boston_mach_class_init(MachineClass *mc) 831 { 832 mc->desc = "MIPS Boston"; 833 mc->init = boston_mach_init; 834 mc->block_default_type = IF_IDE; 835 mc->default_ram_size = 1 * GiB; 836 mc->default_ram_id = "boston.ddr"; 837 mc->max_cpus = 16; 838 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); 839 } 840 841 DEFINE_MACHINE("boston", boston_mach_class_init) 842