1 /*
2  * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
3  *
4  * Copyright (C) 2017 Xilinx Inc
5  * Written by Alistair Francis <alistair.francis@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "exec/address-spaces.h"
21 #include "hw/boards.h"
22 #include "cpu.h"
23 #include "boot.h"
24 
25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
27 #include "qom/object.h"
28 
29 /* Define the PMU device */
30 
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc"
32 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPPMUSoCState, XLNX_ZYNQMP_PMU_SOC)
33 
34 #define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
35 #define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
36 #define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
37 
38 #define XLNX_ZYNQMP_PMU_INTC_ADDR   0xFFD40000
39 
40 #define XLNX_ZYNQMP_PMU_NUM_IPIS    4
41 
42 static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
43     0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
44 };
45 static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
46     19, 20, 21, 22,
47 };
48 
49 struct XlnxZynqMPPMUSoCState {
50     /*< private >*/
51     DeviceState parent_obj;
52 
53     /*< public >*/
54     MicroBlazeCPU cpu;
55     XlnxPMUIOIntc intc;
56     XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
57 };
58 
59 
60 static void xlnx_zynqmp_pmu_soc_init(Object *obj)
61 {
62     XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
63 
64     object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU);
65 
66     object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC);
67 
68     /* Create the IPI device */
69     for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
70         char *name = g_strdup_printf("ipi%d", i);
71         object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI);
72         g_free(name);
73     }
74 }
75 
76 static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
77 {
78     XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
79 
80     object_property_set_uint(OBJECT(&s->cpu), "base-vectors",
81                              XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort);
82     object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true,
83                              &error_abort);
84     object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort);
85     object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort);
86     object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true,
87                              &error_abort);
88     object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true,
89                              &error_abort);
90     object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
91                              &error_abort);
92     object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
93     object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
94                              &error_abort);
95     object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
96                             &error_abort);
97     object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort);
98     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
99         return;
100     }
101 
102     object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10,
103                              &error_abort);
104     object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0,
105                              &error_abort);
106     object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff,
107                              &error_abort);
108     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
109         return;
110     }
111     sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
112     sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
113                        qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
114 
115     /* Connect the IPI device */
116     for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
117         sysbus_realize(SYS_BUS_DEVICE(&s->ipi[i]), &error_abort);
118         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
119         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
120                            qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
121     }
122 }
123 
124 static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
125 {
126     DeviceClass *dc = DEVICE_CLASS(oc);
127 
128     dc->realize = xlnx_zynqmp_pmu_soc_realize;
129 }
130 
131 static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
132     .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
133     .parent = TYPE_DEVICE,
134     .instance_size = sizeof(XlnxZynqMPPMUSoCState),
135     .instance_init = xlnx_zynqmp_pmu_soc_init,
136     .class_init = xlnx_zynqmp_pmu_soc_class_init,
137 };
138 
139 static void xlnx_zynqmp_pmu_soc_register_types(void)
140 {
141     type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
142 }
143 
144 type_init(xlnx_zynqmp_pmu_soc_register_types)
145 
146 /* Define the PMU Machine */
147 
148 static void xlnx_zynqmp_pmu_init(MachineState *machine)
149 {
150     XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
151     MemoryRegion *address_space_mem = get_system_memory();
152     MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
153     MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
154 
155     /* Create the ROM */
156     memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
157                            XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
158     memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
159                                 pmu_rom);
160 
161     /* Create the RAM */
162     memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
163                            machine->ram_size, &error_fatal);
164     memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
165                                 pmu_ram);
166 
167     /* Create the PMU device */
168     object_initialize_child(OBJECT(machine), "pmu", pmu,
169                             TYPE_XLNX_ZYNQMP_PMU_SOC);
170     qdev_realize(DEVICE(pmu), NULL, &error_fatal);
171 
172     /* Load the kernel */
173     microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
174                            machine->ram_size,
175                            machine->initrd_filename,
176                            machine->dtb,
177                            NULL);
178 }
179 
180 static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
181 {
182     mc->desc = "Xilinx ZynqMP PMU machine";
183     mc->init = xlnx_zynqmp_pmu_init;
184 }
185 
186 DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
187 
188