1 /*
2  * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
3  *
4  * Copyright (C) 2017 Xilinx Inc
5  * Written by Alistair Francis <alistair.francis@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "exec/address-spaces.h"
21 #include "hw/boards.h"
22 #include "hw/qdev-properties.h"
23 #include "cpu.h"
24 #include "boot.h"
25 
26 #include "hw/intc/xlnx-zynqmp-ipi.h"
27 #include "hw/intc/xlnx-pmu-iomod-intc.h"
28 
29 /* Define the PMU device */
30 
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
32 #define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
33                                               TYPE_XLNX_ZYNQMP_PMU_SOC)
34 
35 #define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
36 #define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
37 #define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
38 
39 #define XLNX_ZYNQMP_PMU_INTC_ADDR   0xFFD40000
40 
41 #define XLNX_ZYNQMP_PMU_NUM_IPIS    4
42 
43 static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
44     0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
45 };
46 static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
47     19, 20, 21, 22,
48 };
49 
50 typedef struct XlnxZynqMPPMUSoCState {
51     /*< private >*/
52     DeviceState parent_obj;
53 
54     /*< public >*/
55     MicroBlazeCPU cpu;
56     XlnxPMUIOIntc intc;
57     XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
58 }  XlnxZynqMPPMUSoCState;
59 
60 
61 static void xlnx_zynqmp_pmu_soc_init(Object *obj)
62 {
63     XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
64 
65     object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
66                             TYPE_MICROBLAZE_CPU, &error_abort, NULL);
67 
68     sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
69                           TYPE_XLNX_PMU_IO_INTC);
70 
71     /* Create the IPI device */
72     for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
73         char *name = g_strdup_printf("ipi%d", i);
74         sysbus_init_child_obj(obj, name, &s->ipi[i],
75                               sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
76         g_free(name);
77     }
78 }
79 
80 static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
81 {
82     XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
83     Error *err = NULL;
84 
85     object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
86                              "base-vectors", &error_abort);
87     object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
88                              &error_abort);
89     object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
90     object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
91     object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
92                              &error_abort);
93     object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
94                              &error_abort);
95     object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
96                              &error_abort);
97     object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
98     object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
99                              &error_abort);
100     object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
101                             &error_abort);
102     object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
103     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
104     if (err) {
105         error_propagate(errp, err);
106         return;
107     }
108 
109     object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
110                              &error_abort);
111     object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
112                              &error_abort);
113     object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
114                              &error_abort);
115     object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
116     if (err) {
117         error_propagate(errp, err);
118         return;
119     }
120     sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
121     sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
122                        qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
123 
124     /* Connect the IPI device */
125     for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
126         object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized",
127                                  &error_abort);
128         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
129         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
130                            qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
131     }
132 }
133 
134 static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
135 {
136     DeviceClass *dc = DEVICE_CLASS(oc);
137 
138     dc->realize = xlnx_zynqmp_pmu_soc_realize;
139 }
140 
141 static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
142     .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
143     .parent = TYPE_DEVICE,
144     .instance_size = sizeof(XlnxZynqMPPMUSoCState),
145     .instance_init = xlnx_zynqmp_pmu_soc_init,
146     .class_init = xlnx_zynqmp_pmu_soc_class_init,
147 };
148 
149 static void xlnx_zynqmp_pmu_soc_register_types(void)
150 {
151     type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
152 }
153 
154 type_init(xlnx_zynqmp_pmu_soc_register_types)
155 
156 /* Define the PMU Machine */
157 
158 static void xlnx_zynqmp_pmu_init(MachineState *machine)
159 {
160     XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
161     MemoryRegion *address_space_mem = get_system_memory();
162     MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
163     MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
164 
165     /* Create the ROM */
166     memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
167                            XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
168     memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
169                                 pmu_rom);
170 
171     /* Create the RAM */
172     memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
173                            machine->ram_size, &error_fatal);
174     memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
175                                 pmu_ram);
176 
177     /* Create the PMU device */
178     object_initialize_child(OBJECT(machine), "pmu", pmu,
179                             sizeof(XlnxZynqMPPMUSoCState),
180                             TYPE_XLNX_ZYNQMP_PMU_SOC, &error_abort, NULL);
181     object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
182 
183     /* Load the kernel */
184     microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
185                            machine->ram_size,
186                            machine->initrd_filename,
187                            machine->dtb,
188                            NULL);
189 }
190 
191 static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
192 {
193     mc->desc = "Xilinx ZynqMP PMU machine";
194     mc->init = xlnx_zynqmp_pmu_init;
195 }
196 
197 DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
198 
199