1 /*
2  * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
3  * board.
4  *
5  * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
6  * Copyright (c) 2011 PetaLogix
7  * Copyright (c) 2009 Edgar E. Iglesias.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a copy
10  * of this software and associated documentation files (the "Software"), to deal
11  * in the Software without restriction, including without limitation the rights
12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13  * copies of the Software, and to permit persons to whom the Software is
14  * furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included in
17  * all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25  * THE SOFTWARE.
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "qemu-common.h"
32 #include "cpu.h"
33 #include "hw/sysbus.h"
34 #include "hw/hw.h"
35 #include "net/net.h"
36 #include "hw/block/flash.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/boards.h"
39 #include "hw/char/serial.h"
40 #include "exec/address-spaces.h"
41 #include "hw/ssi/ssi.h"
42 
43 #include "boot.h"
44 
45 #include "hw/stream.h"
46 
47 #define LMB_BRAM_SIZE  (128 * KiB)
48 #define FLASH_SIZE     (32 * MiB)
49 
50 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
51 
52 #define NUM_SPI_FLASHES 4
53 
54 #define SPI_BASEADDR 0x40a00000
55 #define MEMORY_BASEADDR 0x50000000
56 #define FLASH_BASEADDR 0x86000000
57 #define INTC_BASEADDR 0x81800000
58 #define TIMER_BASEADDR 0x83c00000
59 #define UART16550_BASEADDR 0x83e00000
60 #define AXIENET_BASEADDR 0x82780000
61 #define AXIDMA_BASEADDR 0x84600000
62 
63 #define AXIDMA_IRQ1         0
64 #define AXIDMA_IRQ0         1
65 #define TIMER_IRQ           2
66 #define AXIENET_IRQ         3
67 #define SPI_IRQ             4
68 #define UART16550_IRQ       5
69 
70 static void
71 petalogix_ml605_init(MachineState *machine)
72 {
73     ram_addr_t ram_size = machine->ram_size;
74     MemoryRegion *address_space_mem = get_system_memory();
75     DeviceState *dev, *dma, *eth0;
76     Object *ds, *cs;
77     MicroBlazeCPU *cpu;
78     SysBusDevice *busdev;
79     DriveInfo *dinfo;
80     int i;
81     MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
82     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
83     qemu_irq irq[32];
84 
85     /* init CPUs */
86     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
87     object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
88     /* Use FPU but don't use floating point conversion and square
89      * root instructions
90      */
91     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
92     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
93                              &error_abort);
94     object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
95     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
96 
97     /* Attach emulated BRAM through the LMB.  */
98     memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
99                            LMB_BRAM_SIZE, &error_fatal);
100     memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
101 
102     memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
103                            &error_fatal);
104     memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
105 
106     dinfo = drive_get(IF_PFLASH, 0, 0);
107     /* 5th parameter 2 means bank-width
108      * 10th paremeter 0 means little-endian */
109     pflash_cfi01_register(FLASH_BASEADDR,
110                           NULL, "petalogix_ml605.flash", FLASH_SIZE,
111                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
112                           64 * KiB, FLASH_SIZE >> 16,
113                           2, 0x89, 0x18, 0x0000, 0x0, 0);
114 
115 
116     dev = qdev_create(NULL, "xlnx.xps-intc");
117     qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
118     qdev_init_nofail(dev);
119     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
120     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
121                        qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
122     for (i = 0; i < 32; i++) {
123         irq[i] = qdev_get_gpio_in(dev, i);
124     }
125 
126     serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
127                    irq[UART16550_IRQ], 115200, serial_hd(0),
128                    DEVICE_LITTLE_ENDIAN);
129 
130     /* 2 timers at irq 2 @ 100 Mhz.  */
131     dev = qdev_create(NULL, "xlnx.xps-timer");
132     qdev_prop_set_uint32(dev, "one-timer-only", 0);
133     qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
134     qdev_init_nofail(dev);
135     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
136     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
137 
138     /* axi ethernet and dma initialization. */
139     qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
140     eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
141     dma = qdev_create(NULL, "xlnx.axi-dma");
142 
143     /* FIXME: attach to the sysbus instead */
144     object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
145                               NULL);
146     object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
147                               NULL);
148 
149     ds = object_property_get_link(OBJECT(dma),
150                                   "axistream-connected-target", NULL);
151     cs = object_property_get_link(OBJECT(dma),
152                                   "axistream-control-connected-target", NULL);
153     qdev_set_nic_properties(eth0, &nd_table[0]);
154     qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
155     qdev_prop_set_uint32(eth0, "txmem", 0x1000);
156     object_property_set_link(OBJECT(eth0), OBJECT(ds),
157                              "axistream-connected", &error_abort);
158     object_property_set_link(OBJECT(eth0), OBJECT(cs),
159                              "axistream-control-connected", &error_abort);
160     qdev_init_nofail(eth0);
161     sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
162     sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
163 
164     ds = object_property_get_link(OBJECT(eth0),
165                                   "axistream-connected-target", NULL);
166     cs = object_property_get_link(OBJECT(eth0),
167                                   "axistream-control-connected-target", NULL);
168     qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
169     object_property_set_link(OBJECT(dma), OBJECT(ds),
170                              "axistream-connected", &error_abort);
171     object_property_set_link(OBJECT(dma), OBJECT(cs),
172                              "axistream-control-connected", &error_abort);
173     qdev_init_nofail(dma);
174     sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
175     sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
176     sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
177 
178     {
179         SSIBus *spi;
180 
181         dev = qdev_create(NULL, "xlnx.xps-spi");
182         qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
183         qdev_init_nofail(dev);
184         busdev = SYS_BUS_DEVICE(dev);
185         sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
186         sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
187 
188         spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
189 
190         for (i = 0; i < NUM_SPI_FLASHES; i++) {
191             DriveInfo *dinfo = drive_get_next(IF_MTD);
192             qemu_irq cs_line;
193 
194             dev = ssi_create_slave_no_init(spi, "n25q128");
195             if (dinfo) {
196                 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
197                                     &error_fatal);
198             }
199             qdev_init_nofail(dev);
200 
201             cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
202             sysbus_connect_irq(busdev, i+1, cs_line);
203         }
204     }
205 
206     /* setup PVR to match kernel settings */
207     cpu->env.pvr.regs[4] = 0xc56b8000;
208     cpu->env.pvr.regs[5] = 0xc56be000;
209     cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
210 
211     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
212                            machine->initrd_filename,
213                            BINARY_DEVICE_TREE_FILE,
214                            NULL);
215 
216 }
217 
218 static void petalogix_ml605_machine_init(MachineClass *mc)
219 {
220     mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
221     mc->init = petalogix_ml605_init;
222     mc->is_default = 0;
223 }
224 
225 DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init)
226